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Mohamed IssaSandhya Viswanathan
Mohamed Issa
authored and
Sandhya Viswanathan
committed
8364305: Support AVX10 saturating floating point conversion instructions
Reviewed-by: sviswanathan, sparasa, jbhateja
1 parent cedc011 commit 37f0e74

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11 files changed

+816
-48
lines changed

11 files changed

+816
-48
lines changed

‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 152 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2225,6 +2225,44 @@ void Assembler::cvttss2sil(Register dst, XMMRegister src) {
22252225
emit_int16(0x2C, (0xC0 | encode));
22262226
}
22272227

2228+
void Assembler::evcvttss2sisl(Register dst, XMMRegister src) {
2229+
assert(VM_Version::supports_avx10_2(), "");
2230+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2231+
attributes.set_is_evex_instruction();
2232+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
2233+
emit_int16(0x6D, (0xC0 | encode));
2234+
}
2235+
2236+
void Assembler::evcvttss2sisl(Register dst, Address src) {
2237+
assert(VM_Version::supports_avx10_2(), "");
2238+
InstructionMark im(this);
2239+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2240+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2241+
attributes.set_is_evex_instruction();
2242+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
2243+
emit_int8((unsigned char)0x6D);
2244+
emit_operand(dst, src, 0);
2245+
}
2246+
2247+
void Assembler::evcvttss2sisq(Register dst, XMMRegister src) {
2248+
assert(VM_Version::supports_avx10_2(), "");
2249+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2250+
attributes.set_is_evex_instruction();
2251+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
2252+
emit_int16(0x6D, (0xC0 | encode));
2253+
}
2254+
2255+
void Assembler::evcvttss2sisq(Register dst, Address src) {
2256+
assert(VM_Version::supports_avx10_2(), "");
2257+
InstructionMark im(this);
2258+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2259+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2260+
attributes.set_is_evex_instruction();
2261+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
2262+
emit_int8((unsigned char)0x6D);
2263+
emit_operand(dst, src, 0);
2264+
}
2265+
22282266
void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
22292267
int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
22302268
InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -2310,13 +2348,51 @@ void Assembler::vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
23102348
emit_int16(0x5B, (0xC0 | encode));
23112349
}
23122350

2351+
void Assembler::evcvttps2dqs(XMMRegister dst, XMMRegister src, int vector_len) {
2352+
assert(VM_Version::supports_avx10_2(), "");
2353+
InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2354+
attributes.set_is_evex_instruction();
2355+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_MAP5, &attributes);
2356+
emit_int16(0x6D, (0xC0 | encode));
2357+
}
2358+
2359+
void Assembler::evcvttps2dqs(XMMRegister dst, Address src, int vector_len) {
2360+
assert(VM_Version::supports_avx10_2(), "");
2361+
InstructionMark im(this);
2362+
InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2363+
attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
2364+
attributes.set_is_evex_instruction();
2365+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_MAP5, &attributes);
2366+
emit_int8((unsigned char)0x6D);
2367+
emit_operand(dst, src, 0);
2368+
}
2369+
23132370
void Assembler::vcvttpd2dq(XMMRegister dst, XMMRegister src, int vector_len) {
23142371
assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
23152372
InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
23162373
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
23172374
emit_int16((unsigned char)0xE6, (0xC0 | encode));
23182375
}
23192376

2377+
void Assembler::evcvttpd2dqs(XMMRegister dst, XMMRegister src, int vector_len) {
2378+
assert(VM_Version::supports_avx10_2(), "");
2379+
InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2380+
attributes.set_is_evex_instruction();
2381+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_MAP5, &attributes);
2382+
emit_int16(0x6D, (0xC0 | encode));
2383+
}
2384+
2385+
void Assembler::evcvttpd2dqs(XMMRegister dst, Address src, int vector_len) {
2386+
assert(VM_Version::supports_avx10_2(), "");
2387+
InstructionMark im(this);
2388+
InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2389+
attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
2390+
attributes.set_is_evex_instruction();
2391+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_MAP5, &attributes);
2392+
emit_int8((unsigned char)0x6D);
2393+
emit_operand(dst, src, 0);
2394+
}
2395+
23202396
void Assembler::vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
23212397
assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
23222398
InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -2332,6 +2408,25 @@ void Assembler::evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len) {
23322408
emit_int16(0x7A, (0xC0 | encode));
23332409
}
23342410

2411+
void Assembler::evcvttps2qqs(XMMRegister dst, XMMRegister src, int vector_len) {
2412+
assert(VM_Version::supports_avx10_2(), "");
2413+
InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2414+
attributes.set_is_evex_instruction();
2415+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_MAP5, &attributes);
2416+
emit_int16(0x6D, (0xC0 | encode));
2417+
}
2418+
2419+
void Assembler::evcvttps2qqs(XMMRegister dst, Address src, int vector_len) {
2420+
assert(VM_Version::supports_avx10_2(), "");
2421+
InstructionMark im(this);
2422+
InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2423+
attributes.set_address_attributes(/* tuple_type */ EVEX_HV, /* input_size_in_bits */ EVEX_32bit);
2424+
attributes.set_is_evex_instruction();
2425+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_MAP5, &attributes);
2426+
emit_int8((unsigned char)0x6D);
2427+
emit_operand(dst, src, 0);
2428+
}
2429+
23352430
void Assembler::evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
23362431
assert(VM_Version::supports_avx512dq(), "");
23372432
InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -2356,6 +2451,25 @@ void Assembler::evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
23562451
emit_int16(0x7A, (0xC0 | encode));
23572452
}
23582453

2454+
void Assembler::evcvttpd2qqs(XMMRegister dst, XMMRegister src, int vector_len) {
2455+
assert(VM_Version::supports_avx10_2(), "");
2456+
InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2457+
attributes.set_is_evex_instruction();
2458+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_MAP5, &attributes);
2459+
emit_int16(0x6D, (0xC0 | encode));
2460+
}
2461+
2462+
void Assembler::evcvttpd2qqs(XMMRegister dst, Address src, int vector_len) {
2463+
assert(VM_Version::supports_avx10_2(), "");
2464+
InstructionMark im(this);
2465+
InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2466+
attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
2467+
attributes.set_is_evex_instruction();
2468+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_MAP5, &attributes);
2469+
emit_int8((unsigned char)0x6D);
2470+
emit_operand(dst, src, 0);
2471+
}
2472+
23592473
void Assembler::evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
23602474
assert(VM_Version::supports_avx512dq(), "");
23612475
InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
@@ -14988,6 +15102,44 @@ void Assembler::cvttsd2siq(Register dst, Address src) {
1498815102
emit_operand(dst, src, 0);
1498915103
}
1499015104

15105+
void Assembler::evcvttsd2sisl(Register dst, XMMRegister src) {
15106+
assert(VM_Version::supports_avx10_2(), "");
15107+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
15108+
attributes.set_is_evex_instruction();
15109+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_MAP5, &attributes);
15110+
emit_int16(0x6D, (0xC0 | encode));
15111+
}
15112+
15113+
void Assembler::evcvttsd2sisl(Register dst, Address src) {
15114+
assert(VM_Version::supports_avx10_2(), "");
15115+
InstructionMark im(this);
15116+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
15117+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
15118+
attributes.set_is_evex_instruction();
15119+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_MAP5, &attributes);
15120+
emit_int8((unsigned char)0x6D);
15121+
emit_operand(dst, src, 0);
15122+
}
15123+
15124+
void Assembler::evcvttsd2sisq(Register dst, XMMRegister src) {
15125+
assert(VM_Version::supports_avx10_2(), "");
15126+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
15127+
attributes.set_is_evex_instruction();
15128+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_MAP5, &attributes);
15129+
emit_int16(0x6D, (0xC0 | encode));
15130+
}
15131+
15132+
void Assembler::evcvttsd2sisq(Register dst, Address src) {
15133+
assert(VM_Version::supports_avx10_2(), "");
15134+
InstructionMark im(this);
15135+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
15136+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
15137+
attributes.set_is_evex_instruction();
15138+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_MAP5, &attributes);
15139+
emit_int8((unsigned char)0x6D);
15140+
emit_operand(dst, src, 0);
15141+
}
15142+
1499115143
void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
1499215144
InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1499315145
int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);

‎src/hotspot/cpu/x86/assembler_x86.hpp‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1316,11 +1316,19 @@ class Assembler : public AbstractAssembler {
13161316
void cvttsd2sil(Register dst, XMMRegister src);
13171317
void cvttsd2siq(Register dst, Address src);
13181318
void cvttsd2siq(Register dst, XMMRegister src);
1319+
void evcvttsd2sisl(Register dst, XMMRegister src);
1320+
void evcvttsd2sisl(Register dst, Address src);
1321+
void evcvttsd2sisq(Register dst, XMMRegister src);
1322+
void evcvttsd2sisq(Register dst, Address src);
13191323

13201324
// Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
13211325
void cvttss2sil(Register dst, XMMRegister src);
13221326
void cvttss2siq(Register dst, XMMRegister src);
13231327
void cvtss2sil(Register dst, XMMRegister src);
1328+
void evcvttss2sisl(Register dst, XMMRegister src);
1329+
void evcvttss2sisl(Register dst, Address src);
1330+
void evcvttss2sisq(Register dst, XMMRegister src);
1331+
void evcvttss2sisq(Register dst, Address src);
13241332

13251333
// Convert vector double to int
13261334
void cvttpd2dq(XMMRegister dst, XMMRegister src);
@@ -1332,7 +1340,11 @@ class Assembler : public AbstractAssembler {
13321340
// Convert vector float to int/long
13331341
void vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len);
13341342
void vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len);
1343+
void evcvttps2dqs(XMMRegister dst, XMMRegister src, int vector_len);
1344+
void evcvttps2dqs(XMMRegister dst, Address src, int vector_len);
13351345
void evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len);
1346+
void evcvttps2qqs(XMMRegister dst, XMMRegister src, int vector_len);
1347+
void evcvttps2qqs(XMMRegister dst, Address src, int vector_len);
13361348

13371349
// Convert vector long to vector FP
13381350
void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len);
@@ -1341,9 +1353,13 @@ class Assembler : public AbstractAssembler {
13411353
// Convert vector double to long
13421354
void evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len);
13431355
void evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len);
1356+
void evcvttpd2qqs(XMMRegister dst, XMMRegister src, int vector_len);
1357+
void evcvttpd2qqs(XMMRegister dst, Address src, int vector_len);
13441358

13451359
// Convert vector double to int
13461360
void vcvttpd2dq(XMMRegister dst, XMMRegister src, int vector_len);
1361+
void evcvttpd2dqs(XMMRegister dst, XMMRegister src, int vector_len);
1362+
void evcvttpd2dqs(XMMRegister dst, Address src, int vector_len);
13471363

13481364
// Evex casts with truncation
13491365
void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len);

‎src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp‎

Lines changed: 85 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5053,12 +5053,12 @@ void C2_MacroAssembler::vector_cast_int_to_subword(BasicType to_elem_bt, XMMRegi
50535053
}
50545054
vpackuswb(dst, dst, zero, vec_enc);
50555055
break;
5056-
default: assert(false, "%s", type2name(to_elem_bt));
5056+
default: assert(false, "Unexpected basic type for target of vector cast int to subword: %s", type2name(to_elem_bt));
50575057
}
50585058
}
50595059

50605060
/*
5061-
* Algorithm for vector D2L and F2I conversions:-
5061+
* Algorithm for vector D2L and F2I conversions (AVX 10.2 unsupported):-
50625062
* a) Perform vector D2L/F2I cast.
50635063
* b) Choose fast path if none of the result vector lane contains 0x80000000 value.
50645064
* It signifies that source value could be any of the special floating point
@@ -5096,7 +5096,7 @@ void C2_MacroAssembler::vector_castF2X_evex(BasicType to_elem_bt, XMMRegister ds
50965096
case T_BYTE:
50975097
evpmovdb(dst, dst, vec_enc);
50985098
break;
5099-
default: assert(false, "%s", type2name(to_elem_bt));
5099+
default: assert(false, "Unexpected basic type for target of vector castF2X EVEX: %s", type2name(to_elem_bt));
51005100
}
51015101
}
51025102

@@ -5143,7 +5143,7 @@ void C2_MacroAssembler::vector_castD2X_evex(BasicType to_elem_bt, XMMRegister ds
51435143
evpmovsqd(dst, dst, vec_enc);
51445144
evpmovdb(dst, dst, vec_enc);
51455145
break;
5146-
default: assert(false, "%s", type2name(to_elem_bt));
5146+
default: assert(false, "Unexpected basic type for target of vector castD2X AVX512DQ EVEX: %s", type2name(to_elem_bt));
51475147
}
51485148
} else {
51495149
assert(type2aelembytes(to_elem_bt) <= 4, "");
@@ -5158,11 +5158,91 @@ void C2_MacroAssembler::vector_castD2X_evex(BasicType to_elem_bt, XMMRegister ds
51585158
case T_BYTE:
51595159
evpmovdb(dst, dst, vec_enc);
51605160
break;
5161-
default: assert(false, "%s", type2name(to_elem_bt));
5161+
default: assert(false, "Unexpected basic type for target of vector castD2X EVEX: %s", type2name(to_elem_bt));
51625162
}
51635163
}
51645164
}
51655165

5166+
void C2_MacroAssembler::vector_castF2X_avx10(BasicType to_elem_bt, XMMRegister dst, XMMRegister src, int vec_enc) {
5167+
switch(to_elem_bt) {
5168+
case T_LONG:
5169+
evcvttps2qqs(dst, src, vec_enc);
5170+
break;
5171+
case T_INT:
5172+
evcvttps2dqs(dst, src, vec_enc);
5173+
break;
5174+
case T_SHORT:
5175+
evcvttps2dqs(dst, src, vec_enc);
5176+
evpmovdw(dst, dst, vec_enc);
5177+
break;
5178+
case T_BYTE:
5179+
evcvttps2dqs(dst, src, vec_enc);
5180+
evpmovdb(dst, dst, vec_enc);
5181+
break;
5182+
default: assert(false, "Unexpected basic type for target of vector castF2X AVX10 (reg src): %s", type2name(to_elem_bt));
5183+
}
5184+
}
5185+
5186+
void C2_MacroAssembler::vector_castF2X_avx10(BasicType to_elem_bt, XMMRegister dst, Address src, int vec_enc) {
5187+
switch(to_elem_bt) {
5188+
case T_LONG:
5189+
evcvttps2qqs(dst, src, vec_enc);
5190+
break;
5191+
case T_INT:
5192+
evcvttps2dqs(dst, src, vec_enc);
5193+
break;
5194+
case T_SHORT:
5195+
evcvttps2dqs(dst, src, vec_enc);
5196+
evpmovdw(dst, dst, vec_enc);
5197+
break;
5198+
case T_BYTE:
5199+
evcvttps2dqs(dst, src, vec_enc);
5200+
evpmovdb(dst, dst, vec_enc);
5201+
break;
5202+
default: assert(false, "Unexpected basic type for target of vector castF2X AVX10 (mem src): %s", type2name(to_elem_bt));
5203+
}
5204+
}
5205+
5206+
void C2_MacroAssembler::vector_castD2X_avx10(BasicType to_elem_bt, XMMRegister dst, XMMRegister src, int vec_enc) {
5207+
switch(to_elem_bt) {
5208+
case T_LONG:
5209+
evcvttpd2qqs(dst, src, vec_enc);
5210+
break;
5211+
case T_INT:
5212+
evcvttpd2dqs(dst, src, vec_enc);
5213+
break;
5214+
case T_SHORT:
5215+
evcvttpd2dqs(dst, src, vec_enc);
5216+
evpmovdw(dst, dst, vec_enc);
5217+
break;
5218+
case T_BYTE:
5219+
evcvttpd2dqs(dst, src, vec_enc);
5220+
evpmovdb(dst, dst, vec_enc);
5221+
break;
5222+
default: assert(false, "Unexpected basic type for target of vector castD2X AVX10 (reg src): %s", type2name(to_elem_bt));
5223+
}
5224+
}
5225+
5226+
void C2_MacroAssembler::vector_castD2X_avx10(BasicType to_elem_bt, XMMRegister dst, Address src, int vec_enc) {
5227+
switch(to_elem_bt) {
5228+
case T_LONG:
5229+
evcvttpd2qqs(dst, src, vec_enc);
5230+
break;
5231+
case T_INT:
5232+
evcvttpd2dqs(dst, src, vec_enc);
5233+
break;
5234+
case T_SHORT:
5235+
evcvttpd2dqs(dst, src, vec_enc);
5236+
evpmovdw(dst, dst, vec_enc);
5237+
break;
5238+
case T_BYTE:
5239+
evcvttpd2dqs(dst, src, vec_enc);
5240+
evpmovdb(dst, dst, vec_enc);
5241+
break;
5242+
default: assert(false, "Unexpected basic type for target of vector castD2X AVX10 (mem src): %s", type2name(to_elem_bt));
5243+
}
5244+
}
5245+
51665246
void C2_MacroAssembler::vector_round_double_evex(XMMRegister dst, XMMRegister src,
51675247
AddressLiteral double_sign_flip, AddressLiteral new_mxcsr, int vec_enc,
51685248
Register tmp, XMMRegister xtmp1, XMMRegister xtmp2, KRegister ktmp1, KRegister ktmp2) {

‎src/hotspot/cpu/x86/c2_MacroAssembler_x86.hpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -347,6 +347,13 @@
347347
XMMRegister xtmp2, XMMRegister xtmp3, XMMRegister xtmp4, XMMRegister xtmp5,
348348
AddressLiteral float_sign_flip, Register rscratch, int vec_enc);
349349

350+
void vector_castF2X_avx10(BasicType to_elem_bt, XMMRegister dst, XMMRegister src, int vec_enc);
351+
352+
void vector_castF2X_avx10(BasicType to_elem_bt, XMMRegister dst, Address src, int vec_enc);
353+
354+
void vector_castD2X_avx10(BasicType to_elem_bt, XMMRegister dst, XMMRegister src, int vec_enc);
355+
356+
void vector_castD2X_avx10(BasicType to_elem_bt, XMMRegister dst, Address src, int vec_enc);
350357

351358
void vector_cast_double_to_int_special_cases_avx(XMMRegister dst, XMMRegister src, XMMRegister xtmp1, XMMRegister xtmp2,
352359
XMMRegister xtmp3, XMMRegister xtmp4, XMMRegister xtmp5, Register rscratch,

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