Merge branch 'upstream-master'

Author: Datadog Syncup Service

make/jdk/src/classes/build/tools/module/GenModuleInfoSource.java

@@ -473,6 +473,11 @@ private void process(Parser parser, boolean extraFile) throws IOException {
                     if (parser.peekToken() != null) {  // must be EOF
                         throw parser.newError("is malformed");
                     }
+                } else if (token.equals("import")) {
+                    nextIdentifier(parser);
+                    skipTokenOrThrow(parser, ";", "missing semicolon");
+                } else if (token.startsWith("@")) {
+                    continue;
                 } else {
                     throw parser.newError("missing keyword");
                 }

make/modules/java.base/Java.gmk

@@ -36,8 +36,8 @@ EXCLUDE_FILES += \
   $(TOPDIR)/src/java.base/share/classes/jdk/internal/module/ModuleLoaderMap.java
 
 EXCLUDES += java/lang/doc-files \
-    jdk/internal/classfile/snippet-files \
-    jdk/internal/classfile/components/snippet-files
+    java/lang/classfile/snippet-files \
+    java/lang/classfile/components/snippet-files
 
 # Exclude BreakIterator classes that are just used in compile process to generate
 # data files and shouldn't go in the product

make/test/BuildMicrobenchmark.gmk

@@ -98,11 +98,6 @@ $(eval $(call SetupJavaCompilation, BUILD_JDK_MICROBENCHMARK, \
     BIN := $(MICROBENCHMARK_CLASSES), \
     JAVAC_FLAGS := --add-exports java.base/sun.security.util=ALL-UNNAMED \
         --add-exports java.base/sun.invoke.util=ALL-UNNAMED \
-        --add-exports java.base/jdk.internal.classfile=ALL-UNNAMED \
-        --add-exports java.base/jdk.internal.classfile.attribute=ALL-UNNAMED \
-        --add-exports java.base/jdk.internal.classfile.constantpool=ALL-UNNAMED \
-        --add-exports java.base/jdk.internal.classfile.instruction=ALL-UNNAMED \
-        --add-exports java.base/jdk.internal.classfile.components=ALL-UNNAMED \
         --add-exports java.base/jdk.internal.classfile.impl=ALL-UNNAMED \
         --add-exports java.base/jdk.internal.org.objectweb.asm=ALL-UNNAMED \
         --add-exports java.base/jdk.internal.org.objectweb.asm.tree=ALL-UNNAMED \

src/hotspot/cpu/aarch64/aarch64_vector.ad

@@ -3742,6 +3742,68 @@ instruct reinterpret_resize_gt128b(vReg dst, vReg src, pReg ptmp, rFlagsReg cr)
   ins_pipe(pipe_slow);
 %}
 
+// ---------------------------- Vector zero extend --------------------------------
+
+instruct vzeroExtBtoX(vReg dst, vReg src) %{
+  match(Set dst (VectorUCastB2X src));
+  format %{ "vzeroExtBtoX $dst, $src" %}
+  ins_encode %{
+    BasicType bt = Matcher::vector_element_basic_type(this);
+    assert(bt == T_SHORT || bt == T_INT || bt == T_LONG, "must be");
+    uint length_in_bytes = Matcher::vector_length_in_bytes(this);
+    if (VM_Version::use_neon_for_vector(length_in_bytes)) {
+      // 4B to 4S/4I, 8B to 8S
+      __ neon_vector_extend($dst$$FloatRegister, bt, length_in_bytes,
+                            $src$$FloatRegister, T_BYTE, /* is_unsigned */ true);
+    } else {
+      assert(UseSVE > 0, "must be sve");
+      __ sve_vector_extend($dst$$FloatRegister, __ elemType_to_regVariant(bt),
+                           $src$$FloatRegister, __ B, /* is_unsigned */ true);
+    }
+  %}
+  ins_pipe(pipe_slow);
+%}
+
+instruct vzeroExtStoX(vReg dst, vReg src) %{
+  match(Set dst (VectorUCastS2X src));
+  format %{ "vzeroExtStoX $dst, $src" %}
+  ins_encode %{
+    BasicType bt = Matcher::vector_element_basic_type(this);
+    assert(bt == T_INT || bt == T_LONG, "must be");
+    uint length_in_bytes = Matcher::vector_length_in_bytes(this);
+    if (VM_Version::use_neon_for_vector(length_in_bytes)) {
+      // 4S to 4I
+      __ neon_vector_extend($dst$$FloatRegister, T_INT, length_in_bytes,
+                            $src$$FloatRegister, T_SHORT, /* is_unsigned */ true);
+    } else {
+      assert(UseSVE > 0, "must be sve");
+      __ sve_vector_extend($dst$$FloatRegister, __ elemType_to_regVariant(bt),
+                           $src$$FloatRegister, __ H, /* is_unsigned */ true);
+    }
+  %}
+  ins_pipe(pipe_slow);
+%}
+
+instruct vzeroExtItoX(vReg dst, vReg src) %{
+  match(Set dst (VectorUCastI2X src));
+  format %{ "vzeroExtItoX $dst, $src" %}
+  ins_encode %{
+    BasicType bt = Matcher::vector_element_basic_type(this);
+    assert(bt == T_LONG, "must be");
+    uint length_in_bytes = Matcher::vector_length_in_bytes(this);
+    if (VM_Version::use_neon_for_vector(length_in_bytes)) {
+      // 2I to 2L
+      __ neon_vector_extend($dst$$FloatRegister, T_LONG, length_in_bytes,
+                            $src$$FloatRegister, T_INT, /* is_unsigned */ true);
+    } else {
+      assert(UseSVE > 0, "must be sve");
+      __ sve_vector_extend($dst$$FloatRegister, __ D,
+                           $src$$FloatRegister, __ S, /* is_unsigned */ true);
+    }
+  %}
+  ins_pipe(pipe_slow);
+%}
+
 // ------------------------------ Vector cast ----------------------------------
 
 // VectorCastB2X

src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

@@ -2276,6 +2276,33 @@ instruct reinterpret_resize_gt128b(vReg dst, vReg src, pReg ptmp, rFlagsReg cr)
   ins_pipe(pipe_slow);
 %}
 
+// ---------------------------- Vector zero extend --------------------------------
+dnl VECTOR_ZERO_EXTEND($1,      $2,     $3,      $4,       $5        $6,        $7,         )
+dnl VECTOR_ZERO_EXTEND(op_name, dst_bt, src_bt,  dst_size, src_size, assertion, neon_comment)
+define(`VECTOR_ZERO_EXTEND', `
+instruct vzeroExt$1toX(vReg dst, vReg src) %{
+  match(Set dst (VectorUCast`$1'2X src));
+  format %{ "vzeroExt$1toX $dst, $src" %}
+  ins_encode %{
+    BasicType bt = Matcher::vector_element_basic_type(this);
+    assert($6, "must be");
+    uint length_in_bytes = Matcher::vector_length_in_bytes(this);
+    if (VM_Version::use_neon_for_vector(length_in_bytes)) {
+      // $7
+      __ neon_vector_extend($dst$$FloatRegister, $2, length_in_bytes,
+                            $src$$FloatRegister, $3, /* is_unsigned */ true);
+    } else {
+      assert(UseSVE > 0, "must be sve");
+      __ sve_vector_extend($dst$$FloatRegister, __ $4,
+                           $src$$FloatRegister, __ $5, /* is_unsigned */ true);
+    }
+  %}
+  ins_pipe(pipe_slow);
+%}')dnl
+VECTOR_ZERO_EXTEND(B, bt,     T_BYTE,  elemType_to_regVariant(bt), B, bt == T_SHORT || bt == T_INT || bt == T_LONG, `4B to 4S/4I, 8B to 8S')
+VECTOR_ZERO_EXTEND(S, T_INT,  T_SHORT, elemType_to_regVariant(bt), H, bt == T_INT || bt == T_LONG,                  `4S to 4I')
+VECTOR_ZERO_EXTEND(I, T_LONG, T_INT,   D,                          S, bt == T_LONG,                                 `2I to 2L')
+
 // ------------------------------ Vector cast ----------------------------------
 
 // VectorCastB2X

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@@ -2196,41 +2196,20 @@ void mvnw(Register Rd, Register Rm,
 
 #undef INSN
 
-  enum sign_kind { SIGNED, UNSIGNED };
-
 private:
-  void _xcvtf_scalar_integer(sign_kind sign, unsigned sz,
-                             FloatRegister Rd, FloatRegister Rn) {
-    starti;
-    f(0b01, 31, 30), f(sign == SIGNED ? 0 : 1, 29);
-    f(0b111100, 27, 23), f((sz >> 1) & 1, 22), f(0b100001110110, 21, 10);
-    rf(Rn, 5), rf(Rd, 0);
-  }
-
-public:
-#define INSN(NAME, sign, sz)                        \
-  void NAME(FloatRegister Rd, FloatRegister Rn) {   \
-    _xcvtf_scalar_integer(sign, sz, Rd, Rn);        \
-  }
-
-  INSN(scvtfs, SIGNED, 0);
-  INSN(scvtfd, SIGNED, 1);
-
-#undef INSN
-
-private:
-  void _xcvtf_vector_integer(sign_kind sign, SIMD_Arrangement T,
+  void _xcvtf_vector_integer(bool is_unsigned, SIMD_Arrangement T,
                              FloatRegister Rd, FloatRegister Rn) {
     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
     starti;
-    f(0, 31), f(T & 1, 30), f(sign == SIGNED ? 0 : 1, 29);
+    f(0, 31), f(T & 1, 30), f(is_unsigned ? 1 : 0, 29);
     f(0b011100, 28, 23), f((T >> 1) & 1, 22), f(0b100001110110, 21, 10);
     rf(Rn, 5), rf(Rd, 0);
   }
 
 public:
+
   void scvtfv(SIMD_Arrangement T, FloatRegister Rd, FloatRegister Rn) {
-    _xcvtf_vector_integer(SIGNED, T, Rd, Rn);
+    _xcvtf_vector_integer(/* is_unsigned */ false, T, Rd, Rn);
   }
 
   // Floating-point compare
@@ -2991,8 +2970,8 @@ template<typename R, typename... Rx>
 
 #undef INSN
 
-private:
-  void _xshll(sign_kind sign, FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
+protected:
+  void _xshll(bool is_unsigned, FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
     starti;
     /* The encodings for the immh:immb fields (bits 22:16) are
      *   0001 xxx       8H, 8B/16B shift = xxx
@@ -3002,20 +2981,20 @@ template<typename R, typename... Rx>
      */
     assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
     assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
-    f(0, 31), f(Tb & 1, 30), f(sign == SIGNED ? 0 : 1, 29), f(0b011110, 28, 23);
+    f(0, 31), f(Tb & 1, 30), f(is_unsigned ? 1 : 0, 29), f(0b011110, 28, 23);
     f((1 << ((Tb>>1)+3))|shift, 22, 16);
     f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
   }
 
 public:
   void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
     assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
-    _xshll(UNSIGNED, Vd, Ta, Vn, Tb, shift);
+    _xshll(/* is_unsigned */ true, Vd, Ta, Vn, Tb, shift);
   }
 
   void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
     assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
-    _xshll(UNSIGNED, Vd, Ta, Vn, Tb, shift);
+    _xshll(/* is_unsigned */ true, Vd, Ta, Vn, Tb, shift);
   }
 
   void uxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb) {
@@ -3024,12 +3003,12 @@ template<typename R, typename... Rx>
 
   void sshll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
     assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
-    _xshll(SIGNED, Vd, Ta, Vn, Tb, shift);
+    _xshll(/* is_unsigned */ false, Vd, Ta, Vn, Tb, shift);
   }
 
   void sshll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
     assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
-    _xshll(SIGNED, Vd, Ta, Vn, Tb, shift);
+    _xshll(/* is_unsigned */ false, Vd, Ta, Vn, Tb, shift);
   }
 
   void sxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb) {
@@ -3862,18 +3841,25 @@ template<typename R, typename... Rx>
   }
 
 // SVE unpack vector elements
-#define INSN(NAME, op) \
-  void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn) { \
-    starti;                                                          \
-    assert(T != B && T != Q, "invalid size");                        \
-    f(0b00000101, 31, 24), f(T, 23, 22), f(0b1100, 21, 18);          \
-    f(op, 17, 16), f(0b001110, 15, 10), rf(Zn, 5), rf(Zd, 0);        \
+protected:
+  void _sve_xunpk(bool is_unsigned, bool is_high, FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn) {
+    starti;
+    assert(T != B && T != Q, "invalid size");
+    f(0b00000101, 31, 24), f(T, 23, 22), f(0b1100, 21, 18);
+    f(is_unsigned ? 1 : 0, 17), f(is_high ? 1 : 0, 16),
+    f(0b001110, 15, 10), rf(Zn, 5), rf(Zd, 0);
+  }
+
+public:
+#define INSN(NAME, is_unsigned, is_high)                                  \
+  void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn) {      \
+    _sve_xunpk(is_unsigned, is_high, Zd, T, Zn);                          \
   }
 
-  INSN(sve_uunpkhi, 0b11); // Signed unpack and extend half of vector - high half
-  INSN(sve_uunpklo, 0b10); // Signed unpack and extend half of vector - low half
-  INSN(sve_sunpkhi, 0b01); // Unsigned unpack and extend half of vector - high half
-  INSN(sve_sunpklo, 0b00); // Unsigned unpack and extend half of vector - low half
+  INSN(sve_uunpkhi, true,  true ); // Unsigned unpack and extend half of vector - high half
+  INSN(sve_uunpklo, true,  false); // Unsigned unpack and extend half of vector - low half
+  INSN(sve_sunpkhi, false, true ); // Signed unpack and extend half of vector - high half
+  INSN(sve_sunpklo, false, false); // Signed unpack and extend half of vector - low half
 #undef INSN
 
 // SVE unpack predicate elements

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp

@@ -1340,26 +1340,25 @@ void C2_MacroAssembler::sve_vmask_lasttrue(Register dst, BasicType bt, PRegister
 // Extend integer vector src to dst with the same lane count
 // but larger element size, e.g. 4B -> 4I
 void C2_MacroAssembler::neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes,
-                                           FloatRegister src, BasicType src_bt) {
+                                           FloatRegister src, BasicType src_bt, bool is_unsigned) {
   if (src_bt == T_BYTE) {
     if (dst_bt == T_SHORT) {
       // 4B/8B to 4S/8S
-      assert(dst_vlen_in_bytes == 8 || dst_vlen_in_bytes == 16, "unsupported");
-      sxtl(dst, T8H, src, T8B);
+      _xshll(is_unsigned, dst, T8H, src, T8B, 0);
     } else {
       // 4B to 4I
       assert(dst_vlen_in_bytes == 16 && dst_bt == T_INT, "unsupported");
-      sxtl(dst, T8H, src, T8B);
-      sxtl(dst, T4S, dst, T4H);
+      _xshll(is_unsigned, dst, T8H, src, T8B, 0);
+      _xshll(is_unsigned, dst, T4S, dst, T4H, 0);
     }
   } else if (src_bt == T_SHORT) {
     // 4S to 4I
     assert(dst_vlen_in_bytes == 16 && dst_bt == T_INT, "unsupported");
-    sxtl(dst, T4S, src, T4H);
+    _xshll(is_unsigned, dst, T4S, src, T4H, 0);
   } else if (src_bt == T_INT) {
     // 2I to 2L
     assert(dst_vlen_in_bytes == 16 && dst_bt == T_LONG, "unsupported");
-    sxtl(dst, T2D, src, T2S);
+    _xshll(is_unsigned, dst, T2D, src, T2S, 0);
   } else {
     ShouldNotReachHere();
   }
@@ -1393,34 +1392,36 @@ void C2_MacroAssembler::neon_vector_narrow(FloatRegister dst, BasicType dst_bt,
 }
 
 void C2_MacroAssembler::sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
-                                          FloatRegister src, SIMD_RegVariant src_size) {
+                                          FloatRegister src, SIMD_RegVariant src_size,
+                                          bool is_unsigned) {
   assert(dst_size > src_size && dst_size <= D && src_size <= S, "invalid element size");
+
   if (src_size == B) {
     switch (dst_size) {
     case H:
-      sve_sunpklo(dst, H, src);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, H, src);
       break;
     case S:
-      sve_sunpklo(dst, H, src);
-      sve_sunpklo(dst, S, dst);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, H, src);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, S, dst);
       break;
     case D:
-      sve_sunpklo(dst, H, src);
-      sve_sunpklo(dst, S, dst);
-      sve_sunpklo(dst, D, dst);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, H, src);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, S, dst);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, D, dst);
       break;
     default:
       ShouldNotReachHere();
     }
   } else if (src_size == H) {
     if (dst_size == S) {
-      sve_sunpklo(dst, S, src);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, S, src);
     } else { // D
-      sve_sunpklo(dst, S, src);
-      sve_sunpklo(dst, D, dst);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, S, src);
+      _sve_xunpk(is_unsigned, /* is_high */ false, dst, D, dst);
     }
   } else if (src_size == S) {
-    sve_sunpklo(dst, D, src);
+    _sve_xunpk(is_unsigned, /* is_high */ false, dst, D, src);
   }
 }
 

src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

@@ -94,13 +94,13 @@
 
   // Vector cast
   void neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes,
-                          FloatRegister src, BasicType src_bt);
+                          FloatRegister src, BasicType src_bt, bool is_unsigned = false);
 
   void neon_vector_narrow(FloatRegister dst, BasicType dst_bt,
                           FloatRegister src, BasicType src_bt, unsigned src_vlen_in_bytes);
 
   void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
-                         FloatRegister src, SIMD_RegVariant src_size);
+                         FloatRegister src, SIMD_RegVariant src_size, bool is_unsigned = false);
 
   void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
                          FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);

src/hotspot/share/gc/parallel/psParallelCompact.hpp

@@ -176,9 +176,6 @@ class SpaceInfo
   // Allows new_top to be set.
   HeapWord** new_top_addr() { return &_new_top; }
 
-  // Where the smallest allowable dense prefix ends (used only for perm gen).
-  HeapWord* min_dense_prefix() const { return _min_dense_prefix; }
-
   // Where the dense prefix ends, or the compacted region begins.
   HeapWord* dense_prefix() const { return _dense_prefix; }
 
@@ -190,7 +187,6 @@ class SpaceInfo
 
   void set_space(MutableSpace* s)           { _space = s; }
   void set_new_top(HeapWord* addr)          { _new_top = addr; }
-  void set_min_dense_prefix(HeapWord* addr) { _min_dense_prefix = addr; }
   void set_dense_prefix(HeapWord* addr)     { _dense_prefix = addr; }
   void set_start_array(ObjectStartArray* s) { _start_array = s; }
 
@@ -199,7 +195,6 @@ class SpaceInfo
  private:
   MutableSpace*     _space;
   HeapWord*         _new_top;
-  HeapWord*         _min_dense_prefix;
   HeapWord*         _dense_prefix;
   ObjectStartArray* _start_array;
   SplitInfo         _split_info;