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Datadog Syncup Service
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‎make/ZipSecurity.gmk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
#
2-
# Copyright (c) 2014, 2023, Oracle and/or its affiliates. All rights reserved.
2+
# Copyright (c) 2014, 2024, Oracle and/or its affiliates. All rights reserved.
33
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
#
55
# This code is free software; you can redistribute it and/or modify it
@@ -27,7 +27,7 @@ default: all
2727

2828
include $(SPEC)
2929
include MakeBase.gmk
30-
include JavaCompilation.gmk
30+
include ZipArchive.gmk
3131

3232
################################################################################
3333
#

‎make/ZipSource.gmk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
#
2-
# Copyright (c) 2014, 2022, Oracle and/or its affiliates. All rights reserved.
2+
# Copyright (c) 2014, 2024, Oracle and/or its affiliates. All rights reserved.
33
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
#
55
# This code is free software; you can redistribute it and/or modify it
@@ -27,8 +27,8 @@ default: all
2727

2828
include $(SPEC)
2929
include MakeBase.gmk
30-
include JavaCompilation.gmk
3130
include Modules.gmk
31+
include ZipArchive.gmk
3232

3333
SRC_ZIP_WORK_DIR := $(SUPPORT_OUTPUTDIR)/src
3434
$(if $(filter $(TOPDIR)/%, $(SUPPORT_OUTPUTDIR)), $(eval SRC_ZIP_BASE := $(TOPDIR)), $(eval SRC_ZIP_BASE := $(SUPPORT_OUTPUTDIR)))

‎make/common/modules/LauncherCommon.gmk‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -178,10 +178,8 @@ ifeq ($(call isTargetOsType, unix)+$(MAKEFILE_PREFIX), true+Launcher)
178178
# We assume all our man pages should reside in section 1.
179179

180180
MAN_FILES_MD := $(wildcard $(addsuffix /*.md, $(call FindModuleManDirs, $(MODULE))))
181-
MAN_FILES_TROFF := $(wildcard $(addsuffix /*.1, $(call FindModuleManDirs, $(MODULE))))
182181

183182
ifneq ($(MAN_FILES_MD), )
184-
# If we got markdown files, ignore the troff files
185183
ifeq ($(ENABLE_PANDOC), false)
186184
$(info Warning: pandoc not found. Not generating man pages)
187185
else
@@ -226,13 +224,5 @@ ifeq ($(call isTargetOsType, unix)+$(MAKEFILE_PREFIX), true+Launcher)
226224

227225
TARGETS += $(BUILD_MAN_PAGES)
228226
endif
229-
else
230-
# No markdown man pages present
231-
$(eval $(call SetupCopyFiles, COPY_MAN_PAGES, \
232-
DEST := $(SUPPORT_OUTPUTDIR)/modules_man/$(MODULE)/man1, \
233-
FILES := $(MAN_FILES_TROFF), \
234-
))
235-
236-
TARGETS += $(COPY_MAN_PAGES)
237227
endif
238228
endif

‎make/test/BuildMicrobenchmark.gmk‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ include $(SPEC)
3030
include MakeBase.gmk
3131

3232
include CopyFiles.gmk
33+
include JarArchive.gmk
3334
include JavaCompilation.gmk
3435
include TestFilesCompilation.gmk
3536

‎src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1602,7 +1602,6 @@ static void fill_continuation_entry(MacroAssembler* masm, Register reg_cont_obj,
16021602
#ifdef ASSERT
16031603
__ load_const_optimized(tmp2, ContinuationEntry::cookie_value());
16041604
__ stw(tmp2, in_bytes(ContinuationEntry::cookie_offset()), R1_SP);
1605-
__ std(tmp2, _abi0(cr), R1_SP);
16061605
#endif //ASSERT
16071606

16081607
__ li(zero, 0);
@@ -1646,10 +1645,6 @@ static void continuation_enter_cleanup(MacroAssembler* masm) {
16461645
__ ld_ptr(tmp1, JavaThread::cont_entry_offset(), R16_thread);
16471646
__ cmpd(CCR0, R1_SP, tmp1);
16481647
__ asm_assert_eq(FILE_AND_LINE ": incorrect R1_SP");
1649-
__ load_const_optimized(tmp1, ContinuationEntry::cookie_value());
1650-
__ ld(tmp2, _abi0(cr), R1_SP);
1651-
__ cmpd(CCR0, tmp1, tmp2);
1652-
__ asm_assert_eq(FILE_AND_LINE ": cookie not found");
16531648
#endif
16541649

16551650
__ ld_ptr(tmp1, ContinuationEntry::parent_cont_fastpath_offset(), R1_SP);

‎src/hotspot/cpu/riscv/stubRoutines_riscv.cpp‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -34,16 +34,6 @@
3434
// Implementation of the platform-specific part of StubRoutines - for
3535
// a description of how to extend it, see the stubRoutines.hpp file.
3636

37-
address StubRoutines::riscv::_get_previous_sp_entry = nullptr;
38-
39-
address StubRoutines::riscv::_f2i_fixup = nullptr;
40-
address StubRoutines::riscv::_f2l_fixup = nullptr;
41-
address StubRoutines::riscv::_d2i_fixup = nullptr;
42-
address StubRoutines::riscv::_d2l_fixup = nullptr;
43-
address StubRoutines::riscv::_float_sign_mask = nullptr;
44-
address StubRoutines::riscv::_float_sign_flip = nullptr;
45-
address StubRoutines::riscv::_double_sign_mask = nullptr;
46-
address StubRoutines::riscv::_double_sign_flip = nullptr;
4737
address StubRoutines::riscv::_zero_blocks = nullptr;
4838
address StubRoutines::riscv::_compare_long_string_LL = nullptr;
4939
address StubRoutines::riscv::_compare_long_string_UU = nullptr;
@@ -52,7 +42,6 @@ address StubRoutines::riscv::_compare_long_string_UL = nullptr;
5242
address StubRoutines::riscv::_string_indexof_linear_ll = nullptr;
5343
address StubRoutines::riscv::_string_indexof_linear_uu = nullptr;
5444
address StubRoutines::riscv::_string_indexof_linear_ul = nullptr;
55-
address StubRoutines::riscv::_large_byte_array_inflate = nullptr;
5645

5746
bool StubRoutines::riscv::_completed = false;
5847

‎src/hotspot/cpu/riscv/stubRoutines_riscv.hpp‎

Lines changed: 0 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -47,18 +47,6 @@ class riscv {
4747
friend class StubGenerator;
4848

4949
private:
50-
static address _get_previous_sp_entry;
51-
52-
static address _f2i_fixup;
53-
static address _f2l_fixup;
54-
static address _d2i_fixup;
55-
static address _d2l_fixup;
56-
57-
static address _float_sign_mask;
58-
static address _float_sign_flip;
59-
static address _double_sign_mask;
60-
static address _double_sign_flip;
61-
6250
static address _zero_blocks;
6351

6452
static address _compare_long_string_LL;
@@ -68,48 +56,11 @@ class riscv {
6856
static address _string_indexof_linear_ll;
6957
static address _string_indexof_linear_uu;
7058
static address _string_indexof_linear_ul;
71-
static address _large_byte_array_inflate;
7259

7360
static bool _completed;
7461

7562
public:
7663

77-
static address get_previous_sp_entry() {
78-
return _get_previous_sp_entry;
79-
}
80-
81-
static address f2i_fixup() {
82-
return _f2i_fixup;
83-
}
84-
85-
static address f2l_fixup() {
86-
return _f2l_fixup;
87-
}
88-
89-
static address d2i_fixup() {
90-
return _d2i_fixup;
91-
}
92-
93-
static address d2l_fixup() {
94-
return _d2l_fixup;
95-
}
96-
97-
static address float_sign_mask() {
98-
return _float_sign_mask;
99-
}
100-
101-
static address float_sign_flip() {
102-
return _float_sign_flip;
103-
}
104-
105-
static address double_sign_mask() {
106-
return _double_sign_mask;
107-
}
108-
109-
static address double_sign_flip() {
110-
return _double_sign_flip;
111-
}
112-
11364
static address zero_blocks() {
11465
return _zero_blocks;
11566
}
@@ -142,10 +93,6 @@ class riscv {
14293
return _string_indexof_linear_uu;
14394
}
14495

145-
static address large_byte_array_inflate() {
146-
return _large_byte_array_inflate;
147-
}
148-
14996
static bool complete() {
15097
return _completed;
15198
}

‎src/hotspot/cpu/s390/assembler_s390.hpp‎

Lines changed: 79 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1236,6 +1236,9 @@ class Assembler : public AbstractAssembler {
12361236
// NOR
12371237
#define VNO_ZOPC (unsigned long)(0xe7L << 40 | 0x6bL << 0) // V1 := !(V2 | V3), element size = 2**m
12381238

1239+
//NOT-XOR
1240+
#define VNX_ZOPC (unsigned long)(0xe7L << 40 | 0x6cL << 0) // V1 := !(V2 | V3), element size = 2**m
1241+
12391242
// OR
12401243
#define VO_ZOPC (unsigned long)(0xe7L << 40 | 0x6aL << 0) // V1 := V2 | V3, element size = 2**m
12411244

@@ -1287,6 +1290,13 @@ class Assembler : public AbstractAssembler {
12871290
#define VSTRC_ZOPC (unsigned long)(0xe7L << 40 | 0x8aL << 0) // String range compare
12881291
#define VISTR_ZOPC (unsigned long)(0xe7L << 40 | 0x5cL << 0) // Isolate String
12891292

1293+
#define VFA_ZOPC (unsigned long)(0xe7L << 40 | 0xE3L << 0) // V1 := V2 + V3, element size = 2**m
1294+
#define VFS_ZOPC (unsigned long)(0xe7L << 40 | 0xE2L << 0) // V1 := V2 - V3, element size = 2**m
1295+
#define VFM_ZOPC (unsigned long)(0xe7L << 40 | 0xE7L << 0) // V1 := V2 * V3, element size = 2**m
1296+
#define VFD_ZOPC (unsigned long)(0xe7L << 40 | 0xE5L << 0) // V1 := V2 / V3, element size = 2**m
1297+
#define VFSQ_ZOPC (unsigned long)(0xe7L << 40 | 0xCEL << 0) // V1 := sqrt of V2, element size = 2**m
1298+
#define VFLR_ZOPC (unsigned long)(0xe7L << 40 | 0xC5L << 0) // vector fp load rounded, element size = 2**m
1299+
12901300

12911301
//--------------------------------
12921302
//-- Miscellaneous Operations --
@@ -2322,22 +2332,22 @@ class Assembler : public AbstractAssembler {
23222332
inline void z_xilf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 32-63
23232333

23242334
// shift
2325-
inline void z_sla( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
2326-
inline void z_slak(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
2327-
inline void z_slag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved!
2328-
inline void z_sra( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended
2329-
inline void z_srak(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int32, sign extended
2330-
inline void z_srag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended
2331-
inline void z_sll( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added
2332-
inline void z_sllk(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int32, zeros added
2333-
inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added
2334-
inline void z_srl( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended
2335-
inline void z_srlk(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int32, zero extended
2336-
inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended
2335+
inline void z_sla( Register r1, int64_t d2, Register b2 = Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
2336+
inline void z_slak(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
2337+
inline void z_slag(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved!
2338+
inline void z_sra( Register r1, int64_t d2, Register b2 = Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended
2339+
inline void z_srak(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int32, sign extended
2340+
inline void z_srag(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended
2341+
inline void z_sll( Register r1, int64_t d2, Register b2 = Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added
2342+
inline void z_sllk(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int32, zeros added
2343+
inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added
2344+
inline void z_srl( Register r1, int64_t d2, Register b2 = Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended
2345+
inline void z_srlk(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int32, zero extended
2346+
inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended
23372347

23382348
// rotate
2339-
inline void z_rll( Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10
2340-
inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10
2349+
inline void z_rll( Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10
2350+
inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10
23412351

23422352
// rotate the AND/XOR/OR/insert
23432353
inline void z_rnsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then AND selected bits -- z196
@@ -2459,7 +2469,7 @@ class Assembler : public AbstractAssembler {
24592469
inline void z_mvc(const Address& d, const Address& s, int64_t l); // move l bytes
24602470
inline void z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes
24612471
inline void z_mvcin(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes
2462-
inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // move region of memory
2472+
inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2 = Z_R0); // move region of memory
24632473

24642474
inline void z_stfle(int64_t d2, Register b2); // store facility list extended
24652475

@@ -2491,6 +2501,7 @@ class Assembler : public AbstractAssembler {
24912501
// Load (transfer from memory)
24922502
inline void z_vlm( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
24932503
inline void z_vl( VectorRegister v1, int64_t d2, Register x2, Register b2);
2504+
inline void z_vl( VectorRegister v1, const Address& a);
24942505
inline void z_vleb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
24952506
inline void z_vleh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
24962507
inline void z_vlef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
@@ -2529,10 +2540,10 @@ class Assembler : public AbstractAssembler {
25292540
inline void z_vlgvg( Register r1, VectorRegister v3, int64_t d2, Register b2);
25302541

25312542
inline void z_vlvg( VectorRegister v1, Register r3, int64_t d2, Register b2, int64_t m4);
2532-
inline void z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2);
2533-
inline void z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2);
2534-
inline void z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2);
2535-
inline void z_vlvgg( VectorRegister v1, Register r3, int64_t d2, Register b2);
2543+
inline void z_vlvgb( VectorRegister v1, Register r3, int64_t d2, Register b2 = Z_R0);
2544+
inline void z_vlvgh( VectorRegister v1, Register r3, int64_t d2, Register b2 = Z_R0);
2545+
inline void z_vlvgf( VectorRegister v1, Register r3, int64_t d2, Register b2 = Z_R0);
2546+
inline void z_vlvgg( VectorRegister v1, Register r3, int64_t d2, Register b2 = Z_R0);
25362547

25372548
inline void z_vlvgp( VectorRegister v1, Register r2, Register r3);
25382549

@@ -2619,6 +2630,7 @@ class Assembler : public AbstractAssembler {
26192630
// Store
26202631
inline void z_vstm( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2);
26212632
inline void z_vst( VectorRegister v1, int64_t d2, Register x2, Register b2);
2633+
inline void z_vst( VectorRegister v1, const Address& a);
26222634
inline void z_vsteb( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
26232635
inline void z_vsteh( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
26242636
inline void z_vstef( VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t m3);
@@ -2679,13 +2691,16 @@ class Assembler : public AbstractAssembler {
26792691
inline void z_vscbiq( VectorRegister v1, VectorRegister v2, VectorRegister v3);
26802692

26812693
// MULTIPLY
2682-
inline void z_vml( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2683-
inline void z_vmh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2684-
inline void z_vmlh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2685-
inline void z_vme( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2686-
inline void z_vmle( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2687-
inline void z_vmo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2688-
inline void z_vmlo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2694+
inline void z_vml( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2695+
inline void z_vmlb( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2696+
inline void z_vmlhw(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2697+
inline void z_vmlf( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2698+
inline void z_vmh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2699+
inline void z_vmlh( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2700+
inline void z_vme( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2701+
inline void z_vmle( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2702+
inline void z_vmo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2703+
inline void z_vmlo( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
26892704

26902705
// MULTIPLY & ADD
26912706
inline void z_vmal( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5);
@@ -2744,6 +2759,9 @@ class Assembler : public AbstractAssembler {
27442759
// NOR
27452760
inline void z_vno( VectorRegister v1, VectorRegister v2, VectorRegister v3);
27462761

2762+
//NOT-XOR
2763+
inline void z_vnx( VectorRegister v1, VectorRegister v2, VectorRegister v3);
2764+
27472765
// OR
27482766
inline void z_vo( VectorRegister v1, VectorRegister v2, VectorRegister v3);
27492767

@@ -2810,6 +2828,10 @@ class Assembler : public AbstractAssembler {
28102828
inline void z_vctzf( VectorRegister v1, VectorRegister v2);
28112829
inline void z_vctzg( VectorRegister v1, VectorRegister v2);
28122830
inline void z_vpopct( VectorRegister v1, VectorRegister v2, int64_t m3);
2831+
inline void z_vpopctb(VectorRegister v1, VectorRegister v2);
2832+
inline void z_vpopcth(VectorRegister v1, VectorRegister v2);
2833+
inline void z_vpopctf(VectorRegister v1, VectorRegister v2);
2834+
inline void z_vpopctg(VectorRegister v1, VectorRegister v2);
28132835

28142836
// Rotate/Shift
28152837
inline void z_verllv( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
@@ -2898,9 +2920,39 @@ class Assembler : public AbstractAssembler {
28982920
inline void z_vistrfs(VectorRegister v1, VectorRegister v2);
28992921

29002922

2901-
// Floatingpoint instructions
2923+
// Vector Floatingpoint instructions
29022924
// ==========================
2925+
// Add
2926+
inline void z_vfa( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2927+
inline void z_vfasb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2928+
inline void z_vfadb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2929+
2930+
//SUB
2931+
inline void z_vfs( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2932+
inline void z_vfssb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2933+
inline void z_vfsdb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2934+
2935+
//MUL
2936+
inline void z_vfm( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2937+
inline void z_vfmsb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2938+
inline void z_vfmdb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2939+
2940+
//DIV
2941+
inline void z_vfd( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4);
2942+
inline void z_vfdsb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2943+
inline void z_vfddb(VectorRegister v1, VectorRegister v2, VectorRegister v3);
2944+
2945+
//square root
2946+
inline void z_vfsq( VectorRegister v1, VectorRegister v2, int64_t m3);
2947+
inline void z_vfsqsb(VectorRegister v1, VectorRegister v2);
2948+
inline void z_vfsqdb(VectorRegister v1, VectorRegister v2);
2949+
2950+
//vector fp load rounded
2951+
inline void z_vflr( VectorRegister v1, VectorRegister v2, int64_t m3, int64_t m5);
2952+
inline void z_vflrd( VectorRegister v1, VectorRegister v2, int64_t m5);
29032953

2954+
// Floatingpoint instructions
2955+
// ==========================
29042956
// compare instructions
29052957
inline void z_cebr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; float
29062958
inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; float

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