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| 1 | +/**************************************************************************** |
| 2 | +*File Name: spi_fram_apis.h |
| 3 | +* |
| 4 | +* Version: 1.0 |
| 5 | +* |
| 6 | +* Description: |
| 7 | +* This file contains high-level functions for the F-RAM access in SPI mode. |
| 8 | +* |
| 9 | +* |
| 10 | +******************************************************************************* |
| 11 | +* Copyright (2019), Cypress Semiconductor Corporation. All rights reserved. |
| 12 | +******************************************************************************* |
| 13 | +* This software, including source code, documentation and related materials |
| 14 | +* (“Software”), is owned by Cypress Semiconductor Corporation or one of its |
| 15 | +* subsidiaries (“Cypress”) and is protected by and subject to worldwide patent |
| 16 | +* protection (United States and foreign), United States copyright laws and |
| 17 | +* international treaty provisions. Therefore, you may use this Software only |
| 18 | +* as provided in the license agreement accompanying the software package from |
| 19 | +* which you obtained this Software (“EULA”). |
| 20 | +* |
| 21 | +* If no EULA applies, Cypress hereby grants you a personal, nonexclusive, |
| 22 | +* non-transferable license to copy, modify, and compile the Software source |
| 23 | +* code solely for use in connection with Cypress’s integrated circuit products. |
| 24 | +* Any reproduction, modification, translation, compilation, or representation |
| 25 | +* of this Software except as specified above is prohibited without the express |
| 26 | +* written permission of Cypress. |
| 27 | +* |
| 28 | +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF ANY KIND, |
| 29 | +* EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED |
| 30 | +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress |
| 31 | +* reserves the right to make changes to the Software without notice. Cypress |
| 32 | +* does not assume any liability arising out of the application or use of the |
| 33 | +* Software or any product or circuit described in the Software. Cypress does |
| 34 | +* not authorize its products for use in any products where a malfunction or |
| 35 | +* failure of the Cypress product may reasonably be expected to result in |
| 36 | +* significant property damage, injury or death (“High Risk Product”). By |
| 37 | +* including Cypress’s product in a High Risk Product, the manufacturer of such |
| 38 | +* system or application assumes all risk of such use and in doing so agrees to |
| 39 | +* indemnify Cypress against all liability. |
| 40 | +*******************************************************************************/ |
| 41 | +#ifndef SPI_FRAM_APIS_H |
| 42 | +#define SPI_FRAM_APIS_H |
| 43 | + |
| 44 | + |
| 45 | +#include "cy_sysint.h" |
| 46 | +#include "cy_device_headers.h" |
| 47 | +#include "cy_smif_memslot.h" |
| 48 | +#include "cy_pdl.h" |
| 49 | +#include "cycfg.h" |
| 50 | + |
| 51 | + |
| 52 | +/*************************************** |
| 53 | +* SMIF Function Prototypes |
| 54 | +***************************************/ |
| 55 | + |
| 56 | +/*Register and buffer Length*/ |
| 57 | +#define SR_SIZE (1u) /* Status register1 size */ |
| 58 | +#define DID_REG_SIZE (9u) /* SPI F-RAM device ID status register size */ |
| 59 | +#define SN_BUF_SIZE (8u) /* Serial Number register size */ |
| 60 | + |
| 61 | +/*************************************** |
| 62 | +* SPIM specific constants |
| 63 | +***************************************/ |
| 64 | +#define CMD_WITHOUT_PARAM (0u) /* Opcode only commands */ |
| 65 | +#define TX_LAST_BYTE (1u) /* The last byte in command transmission |
| 66 | + * (SS is set to high after transmission)*/ |
| 67 | +#define TX_NOT_LAST_BYTE (0u) /* Not the last byte in command transmission |
| 68 | + * (SS remains low after transmission) */ |
| 69 | +#define ADDRESS_SIZE (3u) /* F-RAM memory address size */ |
| 70 | +#define ADDRESS_PLUS_MODE_SIZE (4u) /* F-RAM memory address size with mode byte combined*/ |
| 71 | + |
| 72 | +/*************************************** |
| 73 | +* SPIM specific constants |
| 74 | +***************************************/ |
| 75 | + |
| 76 | +/* Memory Read*/ |
| 77 | +#define MEM_CMD_READ (0x03) /* Read in the single mode */ |
| 78 | +#define MEM_CMD_FAST_READ (0x0B) /* Read in the single mode */ |
| 79 | +#define MEM_CMD_SSRD (0x4B) /* Special sector -256 byte read */ |
| 80 | + |
| 81 | +/* Memory Write*/ |
| 82 | +#define MEM_CMD_WRITE (0x02) /* The memory write in the single mode */ |
| 83 | +#define MEM_CMD_WREN (0x06) /* Write Enable */ |
| 84 | +#define MEM_CMD_SSWR (0x42) /* Special sector -256 byte write */ |
| 85 | + |
| 86 | +/* Status*/ |
| 87 | +#define MEM_CMD_RDSR (0x05) /* Read the status register */ |
| 88 | +#define MEM_CMD_WRSR (0x01) /* Write the status register */ |
| 89 | +#define MEM_CMD_WRDI (0x04) /* Write disable */ |
| 90 | + |
| 91 | +/* Device ID Write*/ |
| 92 | +#define MEM_CMD_RDID (0x9F) /* Read device ID */ |
| 93 | +#define MEM_CMD_RDSN (0xC3) /* Read serial number */ |
| 94 | +#define MEM_CMD_RUID (0x4C) /* Read unique device ID */ |
| 95 | +#define MEM_CMD_WRSN (0xC2) /* Write tserial number */ |
| 96 | + |
| 97 | +/* Power Mode Commands*/ |
| 98 | +#define MEM_CMD_ENTDPD (0xBA) /* Enter DPD - Ramtron mode*/ |
| 99 | +#define MEM_CMD_ENTHBN (0xB9) /* Enter Hibernate - Ramtron Mode */ |
| 100 | + |
| 101 | +/* Constants */ |
| 102 | +#define PACKET_SIZE (256u) /* The emory Read/Write packet */ |
| 103 | + |
| 104 | +#define TX_RX_EQUAL (1u) /* The transmitted and received arrays are equal */ |
| 105 | +#define TX_RX_NOT_EQUAL (0u) /* The transmitted and received arrays are not equal */ |
| 106 | +#define TIMEOUT_1_MS (1000ul)/* 1 ms timeout for all blocking functions */ |
| 107 | + |
| 108 | +cy_en_sysint_status_t FramCmdWRSR(cy_en_smif_slave_select_t fram_slave_select, /* Change the Status Register */ |
| 109 | + SMIF_Type *baseaddr, |
| 110 | + cy_stc_smif_context_t *smifContext, |
| 111 | + uint8_t cmdParam[], |
| 112 | + uint32_t cmdSize); |
| 113 | + |
| 114 | +cy_en_sysint_status_t FramCmdRDSR(cy_en_smif_slave_select_t fram_slave_select,/* Read the status register */ |
| 115 | + SMIF_Type *baseaddr, |
| 116 | + cy_stc_smif_context_t *smifContextuint8_t, |
| 117 | + uint8_t tst_rxBuffer[], |
| 118 | + uint32_t rxSize); |
| 119 | + |
| 120 | +cy_en_sysint_status_t FramCmdWRITE(cy_en_smif_slave_select_t fram_slave_select,/* Write to F-RAM memory */ |
| 121 | + SMIF_Type *baseaddr, |
| 122 | + cy_stc_smif_context_t *smifContext, |
| 123 | + uint8_t tst_txBuffer[], |
| 124 | + uint32_t txSize, |
| 125 | + uint8_t *address); |
| 126 | + |
| 127 | +cy_en_sysint_status_t FramCmdREAD(cy_en_smif_slave_select_t fram_slave_select,/* Read data from F-RAM */ |
| 128 | + SMIF_Type *baseaddr, |
| 129 | + cy_stc_smif_context_t *smifContext, |
| 130 | + uint8_t tst_rxBuffer[], |
| 131 | + uint32_t rxSize, |
| 132 | + uint8_t *address); |
| 133 | + |
| 134 | +cy_en_sysint_status_t FramCmdFSTRD(cy_en_smif_slave_select_t fram_slave_select,/*Fast Read data from F-RAM with Fast Read opcode*/ |
| 135 | + SMIF_Type *baseaddr, |
| 136 | + cy_stc_smif_context_t *smifContext, |
| 137 | + uint8_t tst_rxBuffer[], |
| 138 | + uint32_t rxSize, |
| 139 | + uint8_t *address); |
| 140 | + |
| 141 | +cy_en_sysint_status_t FramCmdWREN(cy_en_smif_slave_select_t fram_slave_select,/* Memory Write Enable */ |
| 142 | + SMIF_Type *baseaddr, |
| 143 | + cy_stc_smif_context_t *smifContext); |
| 144 | + |
| 145 | +cy_en_sysint_status_t FramCmdWRDI(cy_en_smif_slave_select_t fram_slave_select,/* Memory Write Disable */ |
| 146 | + SMIF_Type *baseaddr, |
| 147 | + cy_stc_smif_context_t *smifContext); |
| 148 | + |
| 149 | + |
| 150 | +cy_en_sysint_status_t FramCmdSSWR(cy_en_smif_slave_select_t fram_slave_select,/* Wtite 256-byte Special Sector */ |
| 151 | + SMIF_Type *baseaddr, |
| 152 | + cy_stc_smif_context_t *smifContext, |
| 153 | + uint8_t tst_txBuffer[], |
| 154 | + uint32_t txSize, |
| 155 | + uint8_t *address); |
| 156 | + |
| 157 | +cy_en_sysint_status_t FramCmdSSRD(cy_en_smif_slave_select_t fram_slave_select,/* Read 256-byte Special Sector */ |
| 158 | + SMIF_Type *baseaddr, |
| 159 | + cy_stc_smif_context_t *smifContext, |
| 160 | + uint8_t tst_rxBuffer[], |
| 161 | + uint32_t rxSize, |
| 162 | + uint8_t *address); |
| 163 | + |
| 164 | +cy_en_sysint_status_t FramCmdWRSN(cy_en_smif_slave_select_t fram_slave_select,/* Wrire 8-byte Serial Number */ |
| 165 | + SMIF_Type *baseaddr, |
| 166 | + cy_stc_smif_context_t *smifContext, |
| 167 | + uint8_t cmdParam[], |
| 168 | + uint32_t cmdSize); |
| 169 | + |
| 170 | +cy_en_sysint_status_t FramCmdRDSN(cy_en_smif_slave_select_t fram_slave_select, /* Read 8-byte Serial Number */ |
| 171 | + SMIF_Type *baseaddr, |
| 172 | + cy_stc_smif_context_t *smifContext, |
| 173 | + uint8_t tst_rxBuffer[], |
| 174 | + uint32_t rxSize); |
| 175 | + |
| 176 | +cy_en_sysint_status_t FramCmdRDID(cy_en_smif_slave_select_t fram_slave_select,/* Read Device ID */ |
| 177 | + SMIF_Type *baseaddr, |
| 178 | + cy_stc_smif_context_t *smifContext, |
| 179 | + uint8_t tst_rxBuffer[], |
| 180 | + uint32_t rxSize); |
| 181 | + |
| 182 | +cy_en_sysint_status_t FramCmdRUID(cy_en_smif_slave_select_t fram_slave_select,/* Read Unique Device ID */ |
| 183 | + SMIF_Type *baseaddr, |
| 184 | + cy_stc_smif_context_t *smifContext, |
| 185 | + uint8_t tst_rxBuffer[], |
| 186 | + uint32_t rxSize); |
| 187 | + |
| 188 | +cy_en_sysint_status_t FramCmdHBN(cy_en_smif_slave_select_t fram_slave_select,/* Enter DPD HIBERNATE */ |
| 189 | + SMIF_Type *baseaddr, |
| 190 | + cy_stc_smif_context_t *smifContext); |
| 191 | + |
| 192 | +cy_en_sysint_status_t FramCmdDPD(cy_en_smif_slave_select_t fram_slave_select,/* Enter DPD Mode */ |
| 193 | + SMIF_Type *baseaddr, |
| 194 | + cy_stc_smif_context_t *smifContext); |
| 195 | + |
| 196 | +#endif //SPI_FRAM_APIS_H |
| 197 | + |
| 198 | +/* [] END OF FILE */ |
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