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| 1 | +<?xml version="1.0" encoding="UTF-8"?> |
| 2 | +<Configuration app="BACKEND" formatVersion="13" lastSavedWith="Configurator Backend" lastSavedWithVersion="3.10.0" toolsPackage="ModusToolbox 3.1.0" xmlns="http://cypress.com/xsd/cydesignfile_v4"> |
| 3 | + <Devices> |
| 4 | + <Device mpn="CYW20829B0LKML"> |
| 5 | + <BlockConfig> |
| 6 | + <Block location="ioss[0].port[0].pin[0]"> |
| 7 | + <Alias value="CYBSP_PDM_CLK"/> |
| 8 | + <Alias value="CYBSP_D6"/> |
| 9 | + </Block> |
| 10 | + <Block location="ioss[0].port[0].pin[1]"> |
| 11 | + <Alias value="CYBSP_PDM_DATA"/> |
| 12 | + <Alias value="CYBSP_D7"/> |
| 13 | + </Block> |
| 14 | + <Block location="ioss[0].port[0].pin[2]"> |
| 15 | + <Alias value="CYBSP_D18"/> |
| 16 | + <Alias value="CYBSP_LED_RGB_RED"/> |
| 17 | + </Block> |
| 18 | + <Block location="ioss[0].port[0].pin[3]"> |
| 19 | + <Alias value="CYBSP_D19"/> |
| 20 | + <Alias value="CYBSP_LED_RGB_GREEN"/> |
| 21 | + </Block> |
| 22 | + <Block location="ioss[0].port[0].pin[4]"> |
| 23 | + <Alias value="CYBSP_I2S_MCLK"/> |
| 24 | + <Alias value="CYBSP_LED_RGB_BLUE"/> |
| 25 | + </Block> |
| 26 | + <Block location="ioss[0].port[0].pin[5]"> |
| 27 | + <Alias value="CYBSP_USER_BTN"/> |
| 28 | + <Alias value="CYBSP_USER_BTN1"/> |
| 29 | + <Alias value="CYBSP_I2S_SCK"/> |
| 30 | + </Block> |
| 31 | + <Block location="ioss[0].port[1].pin[0]"> |
| 32 | + <Alias value="CYBSP_USER_BTN2"/> |
| 33 | + <Alias value="CYBSP_D3"/> |
| 34 | + <Alias value="CYBSP_D10"/> |
| 35 | + <Alias value="CYBSP_I2S_WS"/> |
| 36 | + <Alias value="CYBSP_SPI_CS"/> |
| 37 | + </Block> |
| 38 | + <Block location="ioss[0].port[1].pin[1]"> |
| 39 | + <Alias value="CYBSP_USER_LED1"/> |
| 40 | + <Alias value="CYBSP_D13"/> |
| 41 | + <Alias value="CYBSP_I2S_DATA"/> |
| 42 | + <Alias value="CYBSP_SPI_CLK"/> |
| 43 | + </Block> |
| 44 | + <Block location="ioss[0].port[1].pin[2]"> |
| 45 | + <Alias value="CYBSP_SWDIO"/> |
| 46 | + <Alias value="CYBSP_D5"/> |
| 47 | + <Alias value="CYBSP_D11"/> |
| 48 | + <Alias value="CYBSP_SPI_MOSI"/> |
| 49 | + </Block> |
| 50 | + <Block location="ioss[0].port[1].pin[3]"> |
| 51 | + <Alias value="CYBSP_SWDCK"/> |
| 52 | + <Alias value="CYBSP_D4"/> |
| 53 | + <Alias value="CYBSP_SPI_MISO"/> |
| 54 | + <Alias value="CYBSP_D12"/> |
| 55 | + </Block> |
| 56 | + <Block location="ioss[0].port[1].pin[4]"> |
| 57 | + <Alias value="CYBSP_D2"/> |
| 58 | + <Alias value="CYBSP_LIN_EN"/> |
| 59 | + </Block> |
| 60 | + <Block location="ioss[0].port[1].pin[5]"> |
| 61 | + <Alias value="CYBSP_D8"/> |
| 62 | + <Alias value="CYBSP_LIN_RX"/> |
| 63 | + </Block> |
| 64 | + <Block location="ioss[0].port[1].pin[6]"> |
| 65 | + <Alias value="CYBSP_D9"/> |
| 66 | + <Alias value="CYBSP_LIN_TX"/> |
| 67 | + </Block> |
| 68 | + <Block location="ioss[0].port[2].pin[0]"> |
| 69 | + <Alias value="CYBSP_QSPI_SS"/> |
| 70 | + </Block> |
| 71 | + <Block location="ioss[0].port[2].pin[1]"> |
| 72 | + <Alias value="CYBSP_QSPI_D3"/> |
| 73 | + </Block> |
| 74 | + <Block location="ioss[0].port[2].pin[2]"> |
| 75 | + <Alias value="CYBSP_QSPI_D2"/> |
| 76 | + </Block> |
| 77 | + <Block location="ioss[0].port[2].pin[3]"> |
| 78 | + <Alias value="CYBSP_QSPI_D1"/> |
| 79 | + </Block> |
| 80 | + <Block location="ioss[0].port[2].pin[4]"> |
| 81 | + <Alias value="CYBSP_QSPI_D0"/> |
| 82 | + </Block> |
| 83 | + <Block location="ioss[0].port[2].pin[5]"> |
| 84 | + <Alias value="CYBSP_QSPI_SCK"/> |
| 85 | + </Block> |
| 86 | + <Block location="ioss[0].port[3].pin[0]"> |
| 87 | + <Alias value="CYBSP_BT_UART_CTS"/> |
| 88 | + <Alias value="CYBSP_DEBUG_UART_CTS"/> |
| 89 | + </Block> |
| 90 | + <Block location="ioss[0].port[3].pin[1]"> |
| 91 | + <Alias value="CYBSP_BT_UART_RTS"/> |
| 92 | + <Alias value="CYBSP_DEBUG_UART_RTS"/> |
| 93 | + </Block> |
| 94 | + <Block location="ioss[0].port[3].pin[2]"> |
| 95 | + <Alias value="CYBSP_BT_UART_RX"/> |
| 96 | + <Alias value="CYBSP_DEBUG_UART_RX"/> |
| 97 | + <Alias value="CYBSP_D0"/> |
| 98 | + </Block> |
| 99 | + <Block location="ioss[0].port[3].pin[3]"> |
| 100 | + <Alias value="CYBSP_BT_UART_TX"/> |
| 101 | + <Alias value="CYBSP_DEBUG_UART_TX"/> |
| 102 | + <Alias value="CYBSP_D1"/> |
| 103 | + </Block> |
| 104 | + <Block location="ioss[0].port[3].pin[4]"> |
| 105 | + <Alias value="CYBSP_THERMISTOR"/> |
| 106 | + <Alias value="CYBSP_A0"/> |
| 107 | + </Block> |
| 108 | + <Block location="ioss[0].port[3].pin[5]"> |
| 109 | + <Alias value="CYBSP_A1"/> |
| 110 | + </Block> |
| 111 | + <Block location="ioss[0].port[3].pin[6]"> |
| 112 | + <Alias value="CYBSP_A2"/> |
| 113 | + </Block> |
| 114 | + <Block location="ioss[0].port[3].pin[7]"> |
| 115 | + <Alias value="CYBSP_A3"/> |
| 116 | + </Block> |
| 117 | + <Block location="ioss[0].port[4].pin[0]"> |
| 118 | + <Alias value="CYBSP_I2C_SCL"/> |
| 119 | + </Block> |
| 120 | + <Block location="ioss[0].port[4].pin[1]"> |
| 121 | + <Alias value="CYBSP_I2C_SDA"/> |
| 122 | + </Block> |
| 123 | + <Block location="ioss[0].port[5].pin[0]"> |
| 124 | + <Alias value="CYBSP_XTAL1"/> |
| 125 | + <Alias value="CYBSP_CAN_RX"/> |
| 126 | + </Block> |
| 127 | + <Block location="ioss[0].port[5].pin[1]"> |
| 128 | + <Alias value="CYBSP_XTAL0"/> |
| 129 | + <Alias value="CYBSP_CAN_TX"/> |
| 130 | + </Block> |
| 131 | + <Block location="ioss[0].port[5].pin[2]"> |
| 132 | + <Alias value="CYBSP_USER_LED2"/> |
| 133 | + <Alias value="CYBSP_USER_LED"/> |
| 134 | + </Block> |
| 135 | + <Block location="srss[0].clock[0]"> |
| 136 | + <Personality template="sysclocks" version="3.0"/> |
| 137 | + </Block> |
| 138 | + <Block location="srss[0].clock[0].bakclk[0]"> |
| 139 | + <Personality template="bakclk" version="3.0"> |
| 140 | + <Param id="sourceClock" value="lfclk"/> |
| 141 | + </Personality> |
| 142 | + </Block> |
| 143 | + <Block location="srss[0].clock[0].fll[0]"> |
| 144 | + <Personality template="fll" version="4.0"> |
| 145 | + <Param id="configuration" value="auto"/> |
| 146 | + <Param id="desiredFrequency" value="96.000"/> |
| 147 | + <Param id="enableOutputDivider" value="false"/> |
| 148 | + </Personality> |
| 149 | + </Block> |
| 150 | + <Block location="srss[0].clock[0].hfclk[0]"> |
| 151 | + <Personality template="hfclk" version="3.0"> |
| 152 | + <Param id="sourceClockNumber" value="0"/> |
| 153 | + <Param id="divider" value="1"/> |
| 154 | + </Personality> |
| 155 | + </Block> |
| 156 | + <Block location="srss[0].clock[0].hfclk[1]"> |
| 157 | + <Personality template="hfclk" version="3.0"> |
| 158 | + <Param id="sourceClockNumber" value="0"/> |
| 159 | + <Param id="divider" value="1"/> |
| 160 | + </Personality> |
| 161 | + </Block> |
| 162 | + <Block location="srss[0].clock[0].hfclk[2]"> |
| 163 | + <Personality template="hfclk" version="3.0"> |
| 164 | + <Param id="sourceClockNumber" value="2"/> |
| 165 | + <Param id="divider" value="1"/> |
| 166 | + </Personality> |
| 167 | + </Block> |
| 168 | + <Block location="srss[0].clock[0].hfclk[3]"> |
| 169 | + <Personality template="hfclk" version="3.0"> |
| 170 | + <Param id="sourceClockNumber" value="1"/> |
| 171 | + <Param id="divider" value="2"/> |
| 172 | + </Personality> |
| 173 | + </Block> |
| 174 | + <Block location="srss[0].clock[0].iho[0]"> |
| 175 | + <Personality template="mxs40iho" version="1.0"/> |
| 176 | + </Block> |
| 177 | + <Block location="srss[0].clock[0].imo[0]"> |
| 178 | + <Personality template="imo" version="3.0"> |
| 179 | + <Param id="trim" value="1"/> |
| 180 | + </Personality> |
| 181 | + </Block> |
| 182 | + <Block location="srss[0].clock[0].lfclk[0]"> |
| 183 | + <Personality template="lfclk" version="3.0"> |
| 184 | + <Param id="sourceClock" value="pilo"/> |
| 185 | + </Personality> |
| 186 | + </Block> |
| 187 | + <Block location="srss[0].clock[0].mfo[0]"> |
| 188 | + <Personality template="mfo" version="3.0"> |
| 189 | + <Param id="dsen" value="false"/> |
| 190 | + </Personality> |
| 191 | + </Block> |
| 192 | + <Block location="srss[0].clock[0].pathmux[0]"> |
| 193 | + <Personality template="pathmux" version="3.0"> |
| 194 | + <Param id="sourceClock" value="iho"/> |
| 195 | + </Personality> |
| 196 | + </Block> |
| 197 | + <Block location="srss[0].clock[0].pathmux[1]"> |
| 198 | + <Personality template="pathmux" version="3.0"> |
| 199 | + <Param id="sourceClock" value="iho"/> |
| 200 | + </Personality> |
| 201 | + </Block> |
| 202 | + <Block location="srss[0].clock[0].pathmux[2]"> |
| 203 | + <Personality template="pathmux" version="3.0"> |
| 204 | + <Param id="sourceClock" value="iho"/> |
| 205 | + </Personality> |
| 206 | + </Block> |
| 207 | + <Block location="srss[0].clock[0].pathmux[3]"> |
| 208 | + <Personality template="pathmux" version="3.0"> |
| 209 | + <Param id="sourceClock" value="imo"/> |
| 210 | + </Personality> |
| 211 | + </Block> |
| 212 | + <Block location="srss[0].clock[0].pilo[0]"> |
| 213 | + <Personality template="pilo" version="3.0"/> |
| 214 | + </Block> |
| 215 | + <Block location="srss[0].clock[0].timerclk[0]"> |
| 216 | + <Personality template="timerclk" version="3.0"/> |
| 217 | + </Block> |
| 218 | + <Block location="srss[0].power[0]"> |
| 219 | + <Personality template="power_v2" version="1.0"> |
| 220 | + <Param id="actPwrMode" value="POWER_PROFILE_0"/> |
| 221 | + <Param id="enableLowPowerProfileMode" value="false"/> |
| 222 | + <Param id="minCurrRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/> |
| 223 | + <Param id="backupSrc" value="VDDD"/> |
| 224 | + <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/> |
| 225 | + <Param id="deepsleepLatency" value="0"/> |
| 226 | + <Param id="sdr0BypassModeMacro" value="true"/> |
| 227 | + <Param id="vddaMv" value="3300"/> |
| 228 | + <Param id="vdddMv" value="3300"/> |
| 229 | + <Param id="vddbuckMv" value="3300"/> |
| 230 | + <Param id="vddio0Mv" value="3300"/> |
| 231 | + <Param id="vddio1Mv" value="3300"/> |
| 232 | + </Personality> |
| 233 | + </Block> |
| 234 | + </BlockConfig> |
| 235 | + <Netlist/> |
| 236 | + </Device> |
| 237 | + </Devices> |
| 238 | + <ConfiguratorData/> |
| 239 | +</Configuration> |
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