How to use this code in inline/passthrough mode instead of loopback on VC 707?

[optiplex91]

Hey Alex,

Currently I am using your code on VC707, I need to input data from SFP port and send it out on ethernet Phy (RJ 45). I successfully integrated this configuration. I instantiated two PCS/PMA cores, eth_mac_1g_fifo, eth_axis_rx and eth_axis_tx each for SFP and Ethernet Phy.I have also removed udp_complete module because I only needed ethernet frame.

While configuring PCS/PMA core for SFP side I set "include shared logic in core" and for Ethernet side "include shared logic in example design" and connected all output clocks of SFP PCS/PMA core to input clocks of Ethernet PCS/PMA core. I can understand that clock for GMII data of SFP PCS/PMA is "userclk2_out". But I am failing to understand what clock is to be used for GMII data of Ethernet PCS/PMA?

If I use same SFP PCS/PMA "userclk2_out" for GMII data of Ethernet PCS/PMA, all ethernet communication between SFP to ethernet and vice versa is working fine but when I test with NETFPGA using 1G traffic I find ~1% packet drop. How can I reduce/eliminate this data loss?

Thanks