Understanding the IDELAY usage in the KC705 RGMII example

[jeremyherbert]

Hi,

I'm interested in using this code with an ECP5 device that is connected to an RGMII PHY. I am using the KC705 example as a guide, and am writing verilog for use with the open source ECP5 toolchain.

In this file: https://github.com/alexforencich/verilog-ethernet/blob/master/example/KC705/fpga_rgmii/rtl/fpga.v the RX lines are passed through IDELAYE2 units, and IDELAYCTRL is clocked at 200MHz (greater than the 125MHz of the core).

What is the purpose of these IDELAYE2 units? I think the part that confuses me the most is that they are driven by the 200MHz clock, which is not a multiple of 125. The delay taps don't actually appear to be used in the instantiation of the primitive.

Thanks,
Jeremy

[alexforencich]

The IDELAYE2 primitives are hardened mixed-signal components present in the IO banks of Xilinx 7-series FPGAs (for reference, hardened mixed-signal components also include things like PLLs, serializers, etc.). The IDELAY primitives are used to align the clock with the data. I'm not sure exactly how they're implemented internally, probably a delay line built from inverters with muxes to control the delay. I believe the 200 MHz clock is for some sort of calibration to compensate for PVT variations; it is not directly related to the operation of the delay lines. Adjusting the tap settings is sometimes necessary depending on the board layout, PHY chip configuration, etc. Some of the designs set all of the taps to zero (and hence you could probably remove the IDELAY instances), some designs need some offset for things to work correctly. I'm not sure if there is an equivalent on the ECP5 devices, so you'll either have to make sure the clock and data are aligned by adjusting the trace lengths in the board layout or by adjusting the relative timings in the PHY chip, assuming it provides the necessary configurability.

See https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf for more information about the IDELAY primitives.

See https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf for the actual delay specifications. Looks like 78 ps per tap with a 200 MHz reference clock.

[jeremyherbert]

Thank you for explaining, that makes sense. I guess I was just confused as to why there were delay units that had the delay set to zero.

The ECP5 parts do have a delay primitive, but I've removed the delays for now. I'm just trying to see if I can get the timing to pass at this stage (looks like the ARP cache is my biggest problem)