Does the Project Code Support Optical Module Hot-Swapping During Data Transmission?

[Unicorn619]

Hello! I am currently testing the stability of the project, especially the compatibility with hardware operations during device runtime. I noticed that in real-world scenarios, it is possible that optical modules might be removed or inserted while data is being transmitted. Therefore, I need to confirm whether the current project code supports hot-swapping of optical modules during data transmission.

[alexforencich]

Well, naturally if you pull the module, the link will go down and no data will be transferred until you reinsert the module and the link comes back up, and anything sent during that time will be lost. But, no user intervention is required to bring the link back up after an interruption, generally it only takes a few microseconds to reacquire a 10G link (CDR lock and block lock, DFE EQ might take significantly longer, but it should still be well under 1 second). There is also a watchdog module that monitors the PHY and resets the FPGA serializer if the data does not look reasonable after a certain period of time.

I will also note that this repository is deprecated; please see https://github.com/fpganinja/taxi for the current codebase. Note that it is under a different license (CERN OHL strongly reciprocal, instead of MIT). The capabilities of the MAC and PHY logic are the same though, and they will be receiving various upgrades in the near future.