diff --git a/CMakeLists.txt b/CMakeLists.txt index 950a67f3d4..8569e5ed51 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -574,24 +574,25 @@ if(CAPSTONE_RISCV_SUPPORT) add_definitions(-DCAPSTONE_HAS_RISCV) set(SOURCES_RISCV arch/RISCV/RISCVDisassembler.c - arch/RISCV/RISCVInstPrinter.c - arch/RISCV/RISCVMapping.c + arch/RISCV/RISCVHelpers.c arch/RISCV/RISCVModule.c + arch/RISCV/RISCVPrinter.c ) set(HEADERS_RISCV - arch/RISCV/RISCVBaseInfo.h + arch/RISCV/RISCVAst.gen.inc + arch/RISCV/RISCVDecode.gen.inc + arch/RISCV/RISCVDecodeCompressed.gen.inc + arch/RISCV/RISCVAst2Str.gen.inc + arch/RISCV/RISCVAst2StrTbls.gen.inc + arch/RISCV/RISCVInsn.gen.inc + arch/RISCV/RISCVInsnMappings.gen.inc + + arch/RISCV/RISCVHelpers.h arch/RISCV/RISCVDisassembler.h - arch/RISCV/RISCVInstPrinter.h - arch/RISCV/RISCVMapping.h + arch/RISCV/RISCVAst2StrHelpers.h + arch/RISCV/RISCVRVContextHelpers.h arch/RISCV/RISCVModule.h - arch/RISCV/RISCVGenAsmWriter.inc - arch/RISCV/RISCVGenDisassemblerTables.inc - arch/RISCV/RISCVGenInsnNameMaps.inc - arch/RISCV/RISCVGenInstrInfo.inc - arch/RISCV/RISCVGenRegisterInfo.inc - arch/RISCV/RISCVGenSubtargetInfo.inc - arch/RISCV/RISCVMappingInsn.inc - arch/RISCV/RISCVMappingInsnOp.inc + arch/RISCV/RISCVPrinter.h ) endif() diff --git a/arch/RISCV/RISCVAst.gen.inc b/arch/RISCV/RISCVAst.gen.inc new file mode 100644 index 0000000000..46c360c812 --- /dev/null +++ b/arch/RISCV/RISCVAst.gen.inc @@ -0,0 +1,2476 @@ +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ + +#ifndef __RISCVAST_GEN_INC__ +#define __RISCVAST_GEN_INC__ +#include +#include +#include + +enum { RISCV_false = 0, RISCV_true = 1 }; +struct ast { + enum { + RISCV_ILLEGAL, + RISCV_C_ILLEGAL, + RISCV_UTYPE, + RISCV_JAL, + RISCV_JALR, + RISCV_BTYPE, + RISCV_ITYPE, + RISCV_SHIFTIOP, + RISCV_RTYPE, + RISCV_LOAD, + RISCV_STORE, + RISCV_ADDIW, + RISCV_RTYPEW, + RISCV_SHIFTIWOP, + RISCV_FENCE, + RISCV_FENCE_TSO, + RISCV_ECALL, + RISCV_MRET, + RISCV_SRET, + RISCV_EBREAK, + RISCV_WFI, + RISCV_SFENCE_VMA, + RISCV_FENCEI, + RISCV_LOADRES, + RISCV_STORECON, + RISCV_AMO, + RISCV_C_NOP, + RISCV_C_ADDI4SPN, + RISCV_C_LW, + RISCV_C_LD, + RISCV_C_SW, + RISCV_C_SD, + RISCV_C_ADDI, + RISCV_C_JAL, + RISCV_C_ADDIW, + RISCV_C_LI, + RISCV_C_ADDI16SP, + RISCV_C_LUI, + RISCV_C_SRLI, + RISCV_C_SRAI, + RISCV_C_ANDI, + RISCV_C_SUB, + RISCV_C_XOR, + RISCV_C_OR, + RISCV_C_AND, + RISCV_C_SUBW, + RISCV_C_ADDW, + RISCV_C_J, + RISCV_C_BEQZ, + RISCV_C_BNEZ, + RISCV_C_SLLI, + RISCV_C_LWSP, + RISCV_C_LDSP, + RISCV_C_SWSP, + RISCV_C_SDSP, + RISCV_C_JR, + RISCV_C_JALR, + RISCV_C_MV, + RISCV_C_EBREAK, + RISCV_C_ADD, + RISCV_MUL, + RISCV_DIV, + RISCV_REM, + RISCV_MULW, + RISCV_DIVW, + RISCV_REMW, + RISCV_CSRReg, + RISCV_CSRImm, + RISCV_C_NOP_HINT, + RISCV_C_ADDI_HINT, + RISCV_C_LI_HINT, + RISCV_C_LUI_HINT, + RISCV_C_MV_HINT, + RISCV_C_ADD_HINT, + RISCV_C_SLLI_HINT, + RISCV_C_SRLI_HINT, + RISCV_C_SRAI_HINT, + RISCV_FENCE_RESERVED, + RISCV_FENCEI_RESERVED, + RISCV_LOAD_FP, + RISCV_STORE_FP, + RISCV_F_MADD_TYPE_S, + RISCV_F_BIN_RM_TYPE_S, + RISCV_F_UN_RM_FF_TYPE_S, + RISCV_F_UN_RM_FX_TYPE_S, + RISCV_F_UN_RM_XF_TYPE_S, + RISCV_F_BIN_TYPE_F_S, + RISCV_F_BIN_TYPE_X_S, + RISCV_F_UN_TYPE_F_S, + RISCV_F_UN_TYPE_X_S, + RISCV_C_FLWSP, + RISCV_C_FSWSP, + RISCV_C_FLW, + RISCV_C_FSW, + RISCV_F_MADD_TYPE_D, + RISCV_F_BIN_RM_TYPE_D, + RISCV_F_UN_RM_FF_TYPE_D, + RISCV_F_UN_RM_XF_TYPE_D, + RISCV_F_UN_RM_FX_TYPE_D, + RISCV_F_BIN_F_TYPE_D, + RISCV_F_BIN_X_TYPE_D, + RISCV_F_UN_X_TYPE_D, + RISCV_F_UN_F_TYPE_D, + RISCV_C_FLDSP, + RISCV_C_FSDSP, + RISCV_C_FLD, + RISCV_C_FSD, + RISCV_SINVAL_VMA, + RISCV_SFENCE_W_INVAL, + RISCV_SFENCE_INVAL_IR, + RISCV_SLLIUW, + RISCV_ZBA_RTYPEUW, + RISCV_ZBA_RTYPE, + RISCV_RORIW, + RISCV_RORI, + RISCV_ZBB_RTYPEW, + RISCV_ZBB_RTYPE, + RISCV_ZBB_EXTOP, + RISCV_REV8, + RISCV_ORCB, + RISCV_CPOP, + RISCV_CPOPW, + RISCV_CLZ, + RISCV_CLZW, + RISCV_CTZ, + RISCV_CTZW, + RISCV_CLMUL, + RISCV_CLMULH, + RISCV_CLMULR, + RISCV_ZBS_IOP, + RISCV_ZBS_RTYPE, + RISCV_C_LBU, + RISCV_C_LHU, + RISCV_C_LH, + RISCV_C_SB, + RISCV_C_SH, + RISCV_C_ZEXT_B, + RISCV_C_SEXT_B, + RISCV_C_ZEXT_H, + RISCV_C_SEXT_H, + RISCV_C_ZEXT_W, + RISCV_C_NOT, + RISCV_C_MUL, + RISCV_F_BIN_RM_TYPE_H, + RISCV_F_MADD_TYPE_H, + RISCV_F_BIN_F_TYPE_H, + RISCV_F_BIN_X_TYPE_H, + RISCV_F_UN_RM_FF_TYPE_H, + RISCV_F_UN_RM_FX_TYPE_H, + RISCV_F_UN_RM_XF_TYPE_H, + RISCV_F_UN_F_TYPE_H, + RISCV_F_UN_X_TYPE_H, + RISCV_FLI_H, + RISCV_FLI_S, + RISCV_FLI_D, + RISCV_FMINM_H, + RISCV_FMAXM_H, + RISCV_FMINM_S, + RISCV_FMAXM_S, + RISCV_FMINM_D, + RISCV_FMAXM_D, + RISCV_FROUND_H, + RISCV_FROUNDNX_H, + RISCV_FROUND_S, + RISCV_FROUNDNX_S, + RISCV_FROUND_D, + RISCV_FROUNDNX_D, + RISCV_FMVH_X_D, + RISCV_FMVP_D_X, + RISCV_FLEQ_H, + RISCV_FLTQ_H, + RISCV_FLEQ_S, + RISCV_FLTQ_S, + RISCV_FLEQ_D, + RISCV_FLTQ_D, + RISCV_FCVTMOD_W_D, + RISCV_SHA256SIG0, + RISCV_SHA256SIG1, + RISCV_SHA256SUM0, + RISCV_SHA256SUM1, + RISCV_AES32ESMI, + RISCV_AES32ESI, + RISCV_AES32DSMI, + RISCV_AES32DSI, + RISCV_SHA512SIG0L, + RISCV_SHA512SIG0H, + RISCV_SHA512SIG1L, + RISCV_SHA512SIG1H, + RISCV_SHA512SUM0R, + RISCV_SHA512SUM1R, + RISCV_AES64KS1I, + RISCV_AES64KS2, + RISCV_AES64IM, + RISCV_AES64ESM, + RISCV_AES64ES, + RISCV_AES64DSM, + RISCV_AES64DS, + RISCV_SHA512SIG0, + RISCV_SHA512SIG1, + RISCV_SHA512SUM0, + RISCV_SHA512SUM1, + RISCV_SM3P0, + RISCV_SM3P1, + RISCV_SM4ED, + RISCV_SM4KS, + RISCV_ZBKB_RTYPE, + RISCV_ZBKB_PACKW, + RISCV_ZIP, + RISCV_UNZIP, + RISCV_BREV8, + RISCV_XPERM8, + RISCV_XPERM4, + RISCV_ZICOND_RTYPE, + RISCV_VSETVLI, + RISCV_VSETVL, + RISCV_VSETIVLI, + RISCV_VVTYPE, + RISCV_NVSTYPE, + RISCV_NVTYPE, + RISCV_MASKTYPEV, + RISCV_MOVETYPEV, + RISCV_VXTYPE, + RISCV_NXSTYPE, + RISCV_NXTYPE, + RISCV_VXSG, + RISCV_MASKTYPEX, + RISCV_MOVETYPEX, + RISCV_VITYPE, + RISCV_NISTYPE, + RISCV_NITYPE, + RISCV_VISG, + RISCV_MASKTYPEI, + RISCV_MOVETYPEI, + RISCV_VMVRTYPE, + RISCV_MVVTYPE, + RISCV_MVVMATYPE, + RISCV_WVVTYPE, + RISCV_WVTYPE, + RISCV_WMVVTYPE, + RISCV_VEXT2TYPE, + RISCV_VEXT4TYPE, + RISCV_VEXT8TYPE, + RISCV_VMVXS, + RISCV_MVVCOMPRESS, + RISCV_MVXTYPE, + RISCV_MVXMATYPE, + RISCV_WVXTYPE, + RISCV_WXTYPE, + RISCV_WMVXTYPE, + RISCV_VMVSX, + RISCV_FVVTYPE, + RISCV_FVVMATYPE, + RISCV_FWVVTYPE, + RISCV_FWVVMATYPE, + RISCV_FWVTYPE, + RISCV_VFUNARY0, + RISCV_VFWUNARY0, + RISCV_VFNUNARY0, + RISCV_VFUNARY1, + RISCV_VFMVFS, + RISCV_FVFTYPE, + RISCV_FVFMATYPE, + RISCV_FWVFTYPE, + RISCV_FWVFMATYPE, + RISCV_FWFTYPE, + RISCV_VFMERGE, + RISCV_VFMV, + RISCV_VFMVSF, + RISCV_VLSEGTYPE, + RISCV_VLSEGFFTYPE, + RISCV_VSSEGTYPE, + RISCV_VLSSEGTYPE, + RISCV_VSSSEGTYPE, + RISCV_VLUXSEGTYPE, + RISCV_VLOXSEGTYPE, + RISCV_VSUXSEGTYPE, + RISCV_VSOXSEGTYPE, + RISCV_VLRETYPE, + RISCV_VSRETYPE, + RISCV_VMTYPE, + RISCV_MMTYPE, + RISCV_VCPOP_M, + RISCV_VFIRST_M, + RISCV_VMSBF_M, + RISCV_VMSIF_M, + RISCV_VMSOF_M, + RISCV_VIOTA_M, + RISCV_VID_V, + RISCV_VVMTYPE, + RISCV_VVMCTYPE, + RISCV_VVMSTYPE, + RISCV_VVCMPTYPE, + RISCV_VXMTYPE, + RISCV_VXMCTYPE, + RISCV_VXMSTYPE, + RISCV_VXCMPTYPE, + RISCV_VIMTYPE, + RISCV_VIMCTYPE, + RISCV_VIMSTYPE, + RISCV_VICMPTYPE, + RISCV_FVVMTYPE, + RISCV_FVFMTYPE, + RISCV_RIVVTYPE, + RISCV_RMVVTYPE, + RISCV_RFVVTYPE, + RISCV_ZICBOM, + RISCV_ZICBOZ, + RISCV_VANDN_VV, + RISCV_VANDN_VX, + RISCV_VBREV_V, + RISCV_VBREV8_V, + RISCV_VREV8_V, + RISCV_VCLZ_V, + RISCV_VCTZ_V, + RISCV_VCPOP_V, + RISCV_VROL_VV, + RISCV_VROL_VX, + RISCV_VROR_VV, + RISCV_VROR_VX, + RISCV_VROR_VI, + RISCV_VWSLL_VV, + RISCV_VWSLL_VX, + RISCV_VWSLL_VI, + RISCV_VCLMUL_VV, + RISCV_VCLMUL_VX, + RISCV_VCLMULH_VV, + RISCV_VCLMULH_VX, + RISCV_VSHA2MS_VV, + RISCV_ZVKSHA2TYPE, + RISCV_ZIMOP_MOP_R, + RISCV_ZIMOP_MOP_RR, + RISCV_ZCMOP, + RISCV_STOP_FETCHING, + RISCV_THREAD_START + } ast_node_type; + union { + uint32_t illegal; + uint16_t c_illegal; + struct { + uint32_t imm /* bits : 20 */; + uint8_t rd /* bits : 5 */; + enum uop { RISCV_LUI, RISCV_AUIPC } op; + } utype; + struct { + uint32_t imm /* bits : 21 */; + uint8_t rd /* bits : 5 */; + } riscv_jal; + struct { + uint16_t imm /* bits : 12 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_jalr; + struct { + uint16_t imm /* bits : 13 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum bop { + RISCV_BEQ, + RISCV_BNE, + RISCV_BLT, + RISCV_BGE, + RISCV_BLTU, + RISCV_BGEU + } op; + } btype; + struct { + uint16_t imm /* bits : 12 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum iop { + RISCV_ADDI, + RISCV_SLTI, + RISCV_SLTIU, + RISCV_XORI, + RISCV_ORI, + RISCV_ANDI + } op; + } itype; + struct { + uint8_t shamt /* bits : 6 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum sop { RISCV_SLLI, RISCV_SRLI, RISCV_SRAI } op; + } shiftiop; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum rop { + RISCV_ADD, + RISCV_SUB, + RISCV_SLL, + RISCV_SLT, + RISCV_SLTU, + RISCV_XOR, + RISCV_SRL, + RISCV_SRA, + RISCV_OR, + RISCV_AND + } op; + } rtype; + struct { + uint16_t imm /* bits : 12 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + uint8_t is_unsigned /* bits : 1 */; + enum word_width { + RISCV_BYTE, + RISCV_HALF, + RISCV_WORD, + RISCV_DOUBLE + } width; + uint8_t aq /* bits : 1 */; + uint8_t rl /* bits : 1 */; + } load; + struct { + uint16_t imm /* bits : 12 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum word_width width; + uint8_t aq /* bits : 1 */; + uint8_t rl /* bits : 1 */; + } store; + struct { + uint16_t imm /* bits : 12 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } addiw; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum ropw { + RISCV_ADDW, + RISCV_SUBW, + RISCV_SLLW, + RISCV_SRLW, + RISCV_SRAW + } op; + } rtypew; + struct { + uint8_t shamt /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum sopw { RISCV_SLLIW, RISCV_SRLIW, RISCV_SRAIW } op; + } shiftiwop; + struct { + uint8_t pred /* bits : 4 */; + uint8_t succ /* bits : 4 */; + } fence; + struct { + uint8_t pred /* bits : 4 */; + uint8_t succ /* bits : 4 */; + } fence_tso; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rs2 /* bits : 5 */; + } sfence_vma; + struct { + uint8_t aq /* bits : 1 */; + uint8_t rl /* bits : 1 */; + uint8_t rs1 /* bits : 5 */; + enum word_width width; + uint8_t rd /* bits : 5 */; + } loadres; + struct { + uint8_t aq /* bits : 1 */; + uint8_t rl /* bits : 1 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum word_width width; + uint8_t rd /* bits : 5 */; + } storecon; + struct { + enum amoop { + RISCV_AMOSWAP, + RISCV_AMOADD, + RISCV_AMOXOR, + RISCV_AMOAND, + RISCV_AMOOR, + RISCV_AMOMIN, + RISCV_AMOMAX, + RISCV_AMOMINU, + RISCV_AMOMAXU + } op; + uint8_t aq /* bits : 1 */; + uint8_t rl /* bits : 1 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum word_width width; + uint8_t rd /* bits : 5 */; + } amo; + struct { + uint8_t rdc /* bits : 3 */; + uint8_t nzimm; + } c_addi4spn; + struct { + uint8_t uimm /* bits : 5 */; + uint8_t rsc /* bits : 3 */; + uint8_t rdc /* bits : 3 */; + } c_lw; + struct { + uint8_t uimm /* bits : 5 */; + uint8_t rsc /* bits : 3 */; + uint8_t rdc /* bits : 3 */; + } c_ld; + struct { + uint8_t uimm /* bits : 5 */; + uint8_t rsc1 /* bits : 3 */; + uint8_t rsc2 /* bits : 3 */; + } c_sw; + struct { + uint8_t uimm /* bits : 5 */; + uint8_t rsc1 /* bits : 3 */; + uint8_t rsc2 /* bits : 3 */; + } c_sd; + struct { + uint8_t nzi /* bits : 6 */; + uint8_t rsd /* bits : 5 */; + } c_addi; + uint16_t c_jal /* bits : 11 */; + struct { + uint8_t imm /* bits : 6 */; + uint8_t rsd /* bits : 5 */; + } c_addiw; + struct { + uint8_t imm /* bits : 6 */; + uint8_t rd /* bits : 5 */; + } c_li; + uint8_t c_addi16sp /* bits : 6 */; + struct { + uint8_t imm /* bits : 6 */; + uint8_t rd /* bits : 5 */; + } c_lui; + struct { + uint8_t shamt /* bits : 6 */; + uint8_t rsd /* bits : 3 */; + } c_srli; + struct { + uint8_t shamt /* bits : 6 */; + uint8_t rsd /* bits : 3 */; + } c_srai; + struct { + uint8_t imm /* bits : 6 */; + uint8_t rsd /* bits : 3 */; + } c_andi; + struct { + uint8_t rsd /* bits : 3 */; + uint8_t rs2 /* bits : 3 */; + } c_sub; + struct { + uint8_t rsd /* bits : 3 */; + uint8_t rs2 /* bits : 3 */; + } c_xor; + struct { + uint8_t rsd /* bits : 3 */; + uint8_t rs2 /* bits : 3 */; + } c_or; + struct { + uint8_t rsd /* bits : 3 */; + uint8_t rs2 /* bits : 3 */; + } c_and; + struct { + uint8_t rsd /* bits : 3 */; + uint8_t rs2 /* bits : 3 */; + } c_subw; + struct { + uint8_t rsd /* bits : 3 */; + uint8_t rs2 /* bits : 3 */; + } c_addw; + uint16_t c_j /* bits : 11 */; + struct { + uint8_t imm; + uint8_t rs /* bits : 3 */; + } c_beqz; + struct { + uint8_t imm; + uint8_t rs /* bits : 3 */; + } c_bnez; + struct { + uint8_t shamt /* bits : 6 */; + uint8_t rsd /* bits : 5 */; + } c_slli; + struct { + uint8_t uimm /* bits : 6 */; + uint8_t rd /* bits : 5 */; + } c_lwsp; + struct { + uint8_t uimm /* bits : 6 */; + uint8_t rd /* bits : 5 */; + } c_ldsp; + struct { + uint8_t uimm /* bits : 6 */; + uint8_t rs2 /* bits : 5 */; + } c_swsp; + struct { + uint8_t uimm /* bits : 6 */; + uint8_t rs2 /* bits : 5 */; + } c_sdsp; + uint8_t c_jr /* bits : 5 */; + uint8_t c_jalr /* bits : 5 */; + struct { + uint8_t rd /* bits : 5 */; + uint8_t rs2 /* bits : 5 */; + } c_mv; + struct { + uint8_t rsd /* bits : 5 */; + uint8_t rs2 /* bits : 5 */; + } c_add; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + struct mul_op { + uint8_t high /* bits : 1 */; + uint8_t signed_rs1 /* bits : 1 */; + uint8_t signed_rs2 /* bits : 1 */; + } mul_op; + } mul; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + uint8_t s /* bits : 1 */; + } div; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + uint8_t s /* bits : 1 */; + } rem; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } mulw; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + uint8_t s /* bits : 1 */; + } divw; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + uint8_t s /* bits : 1 */; + } remw; + struct { + uint16_t csr /* bits : 12 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum csrop { RISCV_CSRRW, RISCV_CSRRS, RISCV_CSRRC } op; + } csrreg; + struct { + uint16_t csr /* bits : 12 */; + uint8_t imm /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum csrop op; + } csrimm; + uint8_t c_nop_hint /* bits : 6 */; + uint8_t c_addi_hint /* bits : 5 */; + uint8_t c_li_hint /* bits : 6 */; + uint8_t c_lui_hint /* bits : 6 */; + uint8_t c_mv_hint /* bits : 5 */; + uint8_t c_add_hint /* bits : 5 */; + struct { + uint8_t shamt /* bits : 6 */; + uint8_t rsd /* bits : 5 */; + } c_slli_hint; + uint8_t c_srli_hint /* bits : 3 */; + uint8_t c_srai_hint /* bits : 3 */; + struct { + uint8_t fm /* bits : 4 */; + uint8_t pred /* bits : 4 */; + uint8_t succ /* bits : 4 */; + uint8_t rs /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } fence_reserved; + struct { + uint16_t imm /* bits : 12 */; + uint8_t rs /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } fencei_reserved; + struct { + uint16_t imm /* bits : 12 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum word_width width; + } load_fp; + struct { + uint16_t imm /* bits : 12 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum word_width width; + } store_fp; + struct { + uint8_t rs3 /* bits : 5 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum rounding_mode { + RISCV_RM_RNE, + RISCV_RM_RTZ, + RISCV_RM_RDN, + RISCV_RM_RUP, + RISCV_RM_RMM, + RISCV_RM_DYN + } rm; + uint8_t rd /* bits : 5 */; + enum f_madd_op_S { + RISCV_FMADD_S, + RISCV_FMSUB_S, + RISCV_FNMSUB_S, + RISCV_FNMADD_S + } op; + } f_madd_type_s; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_bin_rm_op_S { + RISCV_FADD_S, + RISCV_FSUB_S, + RISCV_FMUL_S, + RISCV_FDIV_S + } op; + } f_bin_rm_type_s; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_ff_op_S { RISCV_FSQRT_S } fsqrt_s; + } f_un_rm_ff_type_s; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_fx_op_S { + RISCV_FCVT_W_S, + RISCV_FCVT_WU_S, + RISCV_FCVT_L_S, + RISCV_FCVT_LU_S + } fcvt_lu_s; + } f_un_rm_fx_type_s; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_xf_op_S { + RISCV_FCVT_S_W, + RISCV_FCVT_S_WU, + RISCV_FCVT_S_L, + RISCV_FCVT_S_LU + } fcvt_s_lu; + } f_un_rm_xf_type_s; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_bin_op_f_S { + RISCV_FSGNJ_S, + RISCV_FSGNJN_S, + RISCV_FSGNJX_S, + RISCV_FMIN_S, + RISCV_FMAX_S + } fmax_s; + } f_bin_type_f_s; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_bin_op_x_S { RISCV_FEQ_S, RISCV_FLT_S, RISCV_FLE_S } fle_s; + } f_bin_type_x_s; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_un_op_f_S { RISCV_FMV_W_X } fmv_w_x; + } f_un_type_f_s; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_un_op_x_S { RISCV_FCLASS_S, RISCV_FMV_X_W } fmv_x_w; + } f_un_type_x_s; + struct { + uint8_t imm /* bits : 6 */; + uint8_t rd /* bits : 5 */; + } c_flwsp; + struct { + uint8_t uimm /* bits : 6 */; + uint8_t rs2 /* bits : 5 */; + } c_fswsp; + struct { + uint8_t uimm /* bits : 5 */; + uint8_t rsc /* bits : 3 */; + uint8_t rdc /* bits : 3 */; + } c_flw; + struct { + uint8_t uimm /* bits : 5 */; + uint8_t rsc1 /* bits : 3 */; + uint8_t rsc2 /* bits : 3 */; + } c_fsw; + struct { + uint8_t rs3 /* bits : 5 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_madd_op_D { + RISCV_FMADD_D, + RISCV_FMSUB_D, + RISCV_FNMSUB_D, + RISCV_FNMADD_D + } op; + } f_madd_type_d; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_bin_rm_op_D { + RISCV_FADD_D, + RISCV_FSUB_D, + RISCV_FMUL_D, + RISCV_FDIV_D + } op; + } f_bin_rm_type_d; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_ff_op_D { + RISCV_FSQRT_D, + RISCV_FCVT_S_D, + RISCV_FCVT_D_S + } fcvt_d_s; + } f_un_rm_ff_type_d; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_xf_op_D { + RISCV_FCVT_D_W, + RISCV_FCVT_D_WU, + RISCV_FCVT_D_L, + RISCV_FCVT_D_LU + } fcvt_d_lu; + } f_un_rm_xf_type_d; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_fx_op_D { + RISCV_FCVT_W_D, + RISCV_FCVT_WU_D, + RISCV_FCVT_L_D, + RISCV_FCVT_LU_D + } fcvt_lu_d; + } f_un_rm_fx_type_d; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_bin_f_op_D { + RISCV_FSGNJ_D, + RISCV_FSGNJN_D, + RISCV_FSGNJX_D, + RISCV_FMIN_D, + RISCV_FMAX_D + } fmax_d; + } f_bin_f_type_d; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_bin_x_op_D { RISCV_FEQ_D, RISCV_FLT_D, RISCV_FLE_D } fle_d; + } f_bin_x_type_d; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_un_x_op_D { RISCV_FCLASS_D, RISCV_FMV_X_D } fmv_x_d; + } f_un_x_type_d; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_un_f_op_D { RISCV_FMV_D_X } fmv_d_x; + } f_un_f_type_d; + struct { + uint8_t uimm /* bits : 6 */; + uint8_t rd /* bits : 5 */; + } c_fldsp; + struct { + uint8_t uimm /* bits : 6 */; + uint8_t rs2 /* bits : 5 */; + } c_fsdsp; + struct { + uint8_t uimm /* bits : 5 */; + uint8_t rsc /* bits : 3 */; + uint8_t rdc /* bits : 3 */; + } c_fld; + struct { + uint8_t uimm /* bits : 5 */; + uint8_t rsc1 /* bits : 3 */; + uint8_t rsc2 /* bits : 3 */; + } c_fsd; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rs2 /* bits : 5 */; + } sinval_vma; + struct { + uint8_t shamt /* bits : 6 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_slliuw; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum bropw_zba { + RISCV_ADDUW, + RISCV_SH1ADDUW, + RISCV_SH2ADDUW, + RISCV_SH3ADDUW + } op; + } zba_rtypeuw; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum brop_zba { RISCV_SH1ADD, RISCV_SH2ADD, RISCV_SH3ADD } op; + } zba_rtype; + struct { + uint8_t shamt /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_roriw; + struct { + uint8_t shamt /* bits : 6 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_rori; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum bropw_zbb { RISCV_ROLW, RISCV_RORW } op; + } zbb_rtypew; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum brop_zbb { + RISCV_ANDN, + RISCV_ORN, + RISCV_XNOR, + RISCV_MAX, + RISCV_MAXU, + RISCV_MIN, + RISCV_MINU, + RISCV_ROL, + RISCV_ROR + } op; + } zbb_rtype; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum extop_zbb { RISCV_SEXTB, RISCV_SEXTH, RISCV_ZEXTH } op; + } zbb_extop; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_rev8; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_orcb; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_cpop; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_cpopw; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_clz; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_clzw; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_ctz; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_ctzw; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_clmul; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_clmulh; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_clmulr; + struct { + uint8_t shamt /* bits : 6 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum biop_zbs { RISCV_BCLRI, RISCV_BEXTI, RISCV_BINVI, RISCV_BSETI } op; + } zbs_iop; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum brop_zbs { RISCV_BCLR, RISCV_BEXT, RISCV_BINV, RISCV_BSET } op; + } zbs_rtype; + struct { + uint8_t uimm /* bits : 2 */; + uint8_t rdc /* bits : 3 */; + uint8_t rs1c /* bits : 3 */; + } c_lbu; + struct { + uint8_t uimm /* bits : 2 */; + uint8_t rdc /* bits : 3 */; + uint8_t rs1c /* bits : 3 */; + } c_lhu; + struct { + uint8_t uimm /* bits : 2 */; + uint8_t rdc /* bits : 3 */; + uint8_t rs1c /* bits : 3 */; + } c_lh; + struct { + uint8_t uimm /* bits : 2 */; + uint8_t rs1c /* bits : 3 */; + uint8_t rs2c /* bits : 3 */; + } c_sb; + struct { + uint8_t uimm /* bits : 2 */; + uint8_t rs1c /* bits : 3 */; + uint8_t rs2c /* bits : 3 */; + } c_sh; + uint8_t c_zext_b /* bits : 3 */; + uint8_t c_sext_b /* bits : 3 */; + uint8_t c_zext_h /* bits : 3 */; + uint8_t c_sext_h /* bits : 3 */; + uint8_t c_zext_w /* bits : 3 */; + uint8_t c_not /* bits : 3 */; + struct { + uint8_t rsdc /* bits : 3 */; + uint8_t rs2c /* bits : 3 */; + } c_mul; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_bin_rm_op_H { + RISCV_FADD_H, + RISCV_FSUB_H, + RISCV_FMUL_H, + RISCV_FDIV_H + } op; + } f_bin_rm_type_h; + struct { + uint8_t rs3 /* bits : 5 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_madd_op_H { + RISCV_FMADD_H, + RISCV_FMSUB_H, + RISCV_FNMSUB_H, + RISCV_FNMADD_H + } op; + } f_madd_type_h; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_bin_f_op_H { + RISCV_FSGNJ_H, + RISCV_FSGNJN_H, + RISCV_FSGNJX_H, + RISCV_FMIN_H, + RISCV_FMAX_H + } fmax_h; + } f_bin_f_type_h; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_bin_x_op_H { RISCV_FEQ_H, RISCV_FLT_H, RISCV_FLE_H } fle_h; + } f_bin_x_type_h; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_ff_op_H { + RISCV_FSQRT_H, + RISCV_FCVT_H_S, + RISCV_FCVT_H_D, + RISCV_FCVT_S_H, + RISCV_FCVT_D_H + } fcvt_d_h; + } f_un_rm_ff_type_h; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_fx_op_H { + RISCV_FCVT_W_H, + RISCV_FCVT_WU_H, + RISCV_FCVT_L_H, + RISCV_FCVT_LU_H + } fcvt_lu_h; + } f_un_rm_fx_type_h; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + enum f_un_rm_xf_op_H { + RISCV_FCVT_H_W, + RISCV_FCVT_H_WU, + RISCV_FCVT_H_L, + RISCV_FCVT_H_LU + } fcvt_h_lu; + } f_un_rm_xf_type_h; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_un_f_op_H { RISCV_FMV_H_X } fmv_h_x; + } f_un_f_type_h; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum f_un_x_op_H { RISCV_FCLASS_H, RISCV_FMV_X_H } fmv_x_h; + } f_un_x_type_h; + struct { + uint8_t constantidx /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fli_h; + struct { + uint8_t constantidx /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fli_s; + struct { + uint8_t constantidx /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fli_d; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fminm_h; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fmaxm_h; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fminm_s; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fmaxm_s; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fminm_d; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fmaxm_d; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + } riscv_fround_h; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + } riscv_froundnx_h; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + } riscv_fround_s; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + } riscv_froundnx_s; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + } riscv_fround_d; + struct { + uint8_t rs1 /* bits : 5 */; + enum rounding_mode rm; + uint8_t rd /* bits : 5 */; + } riscv_froundnx_d; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fmvh_x_d; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fmvp_d_x; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fleq_h; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fltq_h; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fleq_s; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fltq_s; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fleq_d; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fltq_d; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_fcvtmod_w_d; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha256sig0; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha256sig1; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha256sum0; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha256sum1; + struct { + uint8_t bs /* bits : 2 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes32esmi; + struct { + uint8_t bs /* bits : 2 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes32esi; + struct { + uint8_t bs /* bits : 2 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes32dsmi; + struct { + uint8_t bs /* bits : 2 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes32dsi; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sig0l; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sig0h; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sig1l; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sig1h; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sum0r; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sum1r; + struct { + uint8_t rnum /* bits : 4 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes64ks1i; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes64ks2; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes64im; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes64esm; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes64es; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes64dsm; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } aes64ds; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sig0; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sig1; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sum0; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sha512sum1; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sm3p0; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sm3p1; + struct { + uint8_t bs /* bits : 2 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sm4ed; + struct { + uint8_t bs /* bits : 2 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } sm4ks; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum brop_zbkb { RISCV_PACK, RISCV_PACKH } op; + } zbkb_rtype; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } zbkb_packw; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_zip; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_unzip; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_brev8; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_xperm8; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } riscv_xperm4; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + enum zicondop { RISCV_CZERO_EQZ, RISCV_CZERO_NEZ } riscv_czero_nez; + } zicond_rtype; + struct { + uint8_t ma /* bits : 1 */; + uint8_t ta /* bits : 1 */; + uint8_t sew /* bits : 3 */; + uint8_t lmul /* bits : 3 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } vsetvli; + struct { + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } vsetvl; + struct { + uint8_t ma /* bits : 1 */; + uint8_t ta /* bits : 1 */; + uint8_t sew /* bits : 3 */; + uint8_t lmul /* bits : 3 */; + uint8_t uimm /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } vsetivli; + struct { + enum vvfunct6 { + RISCV_VV_VADD, + RISCV_VV_VSUB, + RISCV_VV_VMINU, + RISCV_VV_VMIN, + RISCV_VV_VMAXU, + RISCV_VV_VMAX, + RISCV_VV_VAND, + RISCV_VV_VOR, + RISCV_VV_VXOR, + RISCV_VV_VRGATHER, + RISCV_VV_VRGATHEREI16, + RISCV_VV_VSADDU, + RISCV_VV_VSADD, + RISCV_VV_VSSUBU, + RISCV_VV_VSSUB, + RISCV_VV_VSLL, + RISCV_VV_VSMUL, + RISCV_VV_VSRL, + RISCV_VV_VSRA, + RISCV_VV_VSSRL, + RISCV_VV_VSSRA + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vvtype; + struct { + enum nvsfunct6 { RISCV_NVS_VNSRL, RISCV_NVS_VNSRA } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } nvstype; + struct { + enum nvfunct6 { RISCV_NV_VNCLIPU, RISCV_NV_VNCLIP } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } nvtype; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } masktypev; + struct { + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } movetypev; + struct { + enum vxfunct6 { + RISCV_VX_VADD, + RISCV_VX_VSUB, + RISCV_VX_VRSUB, + RISCV_VX_VMINU, + RISCV_VX_VMIN, + RISCV_VX_VMAXU, + RISCV_VX_VMAX, + RISCV_VX_VAND, + RISCV_VX_VOR, + RISCV_VX_VXOR, + RISCV_VX_VSADDU, + RISCV_VX_VSADD, + RISCV_VX_VSSUBU, + RISCV_VX_VSSUB, + RISCV_VX_VSLL, + RISCV_VX_VSMUL, + RISCV_VX_VSRL, + RISCV_VX_VSRA, + RISCV_VX_VSSRL, + RISCV_VX_VSSRA + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vxtype; + struct { + enum nxsfunct6 { RISCV_NXS_VNSRL, RISCV_NXS_VNSRA } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } nxstype; + struct { + enum nxfunct6 { RISCV_NX_VNCLIPU, RISCV_NX_VNCLIP } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } nxtype; + struct { + enum vxsgfunct6 { + RISCV_VX_VSLIDEUP, + RISCV_VX_VSLIDEDOWN, + RISCV_VX_VRGATHER + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vxsg; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } masktypex; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } movetypex; + struct { + enum vifunct6 { + RISCV_VI_VADD, + RISCV_VI_VRSUB, + RISCV_VI_VAND, + RISCV_VI_VOR, + RISCV_VI_VXOR, + RISCV_VI_VSADDU, + RISCV_VI_VSADD, + RISCV_VI_VSLL, + RISCV_VI_VSRL, + RISCV_VI_VSRA, + RISCV_VI_VSSRL, + RISCV_VI_VSSRA + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vitype; + struct { + enum nisfunct6 { RISCV_NIS_VNSRL, RISCV_NIS_VNSRA } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } nistype; + struct { + enum nifunct6 { RISCV_NI_VNCLIPU, RISCV_NI_VNCLIP } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } nitype; + struct { + enum visgfunct6 { + RISCV_VI_VSLIDEUP, + RISCV_VI_VSLIDEDOWN, + RISCV_VI_VRGATHER + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } visg; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } masktypei; + struct { + uint8_t vd /* bits : 5 */; + uint8_t simm /* bits : 5 */; + } movetypei; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vmvrtype; + struct { + enum mvvfunct6 { + RISCV_MVV_VAADDU, + RISCV_MVV_VAADD, + RISCV_MVV_VASUBU, + RISCV_MVV_VASUB, + RISCV_MVV_VMUL, + RISCV_MVV_VMULH, + RISCV_MVV_VMULHU, + RISCV_MVV_VMULHSU, + RISCV_MVV_VDIVU, + RISCV_MVV_VDIV, + RISCV_MVV_VREMU, + RISCV_MVV_VREM + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } mvvtype; + struct { + enum mvvmafunct6 { + RISCV_MVV_VMACC, + RISCV_MVV_VNMSAC, + RISCV_MVV_VMADD, + RISCV_MVV_VNMSUB + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } mvvmatype; + struct { + enum wvvfunct6 { + RISCV_WVV_VADD, + RISCV_WVV_VSUB, + RISCV_WVV_VADDU, + RISCV_WVV_VSUBU, + RISCV_WVV_VWMUL, + RISCV_WVV_VWMULU, + RISCV_WVV_VWMULSU + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } wvvtype; + struct { + enum wvfunct6 { + RISCV_WV_VADD, + RISCV_WV_VSUB, + RISCV_WV_VADDU, + RISCV_WV_VSUBU + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } wvtype; + struct { + enum wmvvfunct6 { + RISCV_WMVV_VWMACCU, + RISCV_WMVV_VWMACC, + RISCV_WMVV_VWMACCSU + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } wmvvtype; + struct { + enum vext2funct6 { RISCV_VEXT2_ZVF2, RISCV_VEXT2_SVF2 } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vext2type; + struct { + enum vext4funct6 { RISCV_VEXT4_ZVF4, RISCV_VEXT4_SVF4 } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vext4type; + struct { + enum vext8funct6 { RISCV_VEXT8_ZVF8, RISCV_VEXT8_SVF8 } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vext8type; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } vmvxs; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } mvvcompress; + struct { + enum mvxfunct6 { + RISCV_MVX_VAADDU, + RISCV_MVX_VAADD, + RISCV_MVX_VASUBU, + RISCV_MVX_VASUB, + RISCV_MVX_VSLIDE1UP, + RISCV_MVX_VSLIDE1DOWN, + RISCV_MVX_VMUL, + RISCV_MVX_VMULH, + RISCV_MVX_VMULHU, + RISCV_MVX_VMULHSU, + RISCV_MVX_VDIVU, + RISCV_MVX_VDIV, + RISCV_MVX_VREMU, + RISCV_MVX_VREM + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } mvxtype; + struct { + enum mvxmafunct6 { + RISCV_MVX_VMACC, + RISCV_MVX_VNMSAC, + RISCV_MVX_VMADD, + RISCV_MVX_VNMSUB + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } mvxmatype; + struct { + enum wvxfunct6 { + RISCV_WVX_VADD, + RISCV_WVX_VSUB, + RISCV_WVX_VADDU, + RISCV_WVX_VSUBU, + RISCV_WVX_VWMUL, + RISCV_WVX_VWMULU, + RISCV_WVX_VWMULSU + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } wvxtype; + struct { + enum wxfunct6 { + RISCV_WX_VADD, + RISCV_WX_VSUB, + RISCV_WX_VADDU, + RISCV_WX_VSUBU + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } wxtype; + struct { + enum wmvxfunct6 { + RISCV_WMVX_VWMACCU, + RISCV_WMVX_VWMACC, + RISCV_WMVX_VWMACCUS, + RISCV_WMVX_VWMACCSU + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } wmvxtype; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vmvsx; + struct { + enum fvvfunct6 { + RISCV_FVV_VADD, + RISCV_FVV_VSUB, + RISCV_FVV_VMIN, + RISCV_FVV_VMAX, + RISCV_FVV_VSGNJ, + RISCV_FVV_VSGNJN, + RISCV_FVV_VSGNJX, + RISCV_FVV_VDIV, + RISCV_FVV_VMUL + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fvvtype; + struct { + enum fvvmafunct6 { + RISCV_FVV_VMADD, + RISCV_FVV_VNMADD, + RISCV_FVV_VMSUB, + RISCV_FVV_VNMSUB, + RISCV_FVV_VMACC, + RISCV_FVV_VNMACC, + RISCV_FVV_VMSAC, + RISCV_FVV_VNMSAC + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fvvmatype; + struct { + enum fwvvfunct6 { + RISCV_FWVV_VADD, + RISCV_FWVV_VSUB, + RISCV_FWVV_VMUL + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fwvvtype; + struct { + enum fwvvmafunct6 { + RISCV_FWVV_VMACC, + RISCV_FWVV_VNMACC, + RISCV_FWVV_VMSAC, + RISCV_FWVV_VNMSAC + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fwvvmatype; + struct { + enum fwvfunct6 { RISCV_FWV_VADD, RISCV_FWV_VSUB } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fwvtype; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + enum vfunary0 { + RISCV_FV_CVT_XU_F, + RISCV_FV_CVT_X_F, + RISCV_FV_CVT_F_XU, + RISCV_FV_CVT_F_X, + RISCV_FV_CVT_RTZ_XU_F, + RISCV_FV_CVT_RTZ_X_F + } vfunary0; + uint8_t vd /* bits : 5 */; + } vfunary0; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + enum vfwunary0 { + RISCV_FWV_CVT_XU_F, + RISCV_FWV_CVT_X_F, + RISCV_FWV_CVT_F_XU, + RISCV_FWV_CVT_F_X, + RISCV_FWV_CVT_F_F, + RISCV_FWV_CVT_RTZ_XU_F, + RISCV_FWV_CVT_RTZ_X_F + } vfwunary0; + uint8_t vd /* bits : 5 */; + } vfwunary0; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + enum vfnunary0 { + RISCV_FNV_CVT_XU_F, + RISCV_FNV_CVT_X_F, + RISCV_FNV_CVT_F_XU, + RISCV_FNV_CVT_F_X, + RISCV_FNV_CVT_F_F, + RISCV_FNV_CVT_ROD_F_F, + RISCV_FNV_CVT_RTZ_XU_F, + RISCV_FNV_CVT_RTZ_X_F + } vfnunary0; + uint8_t vd /* bits : 5 */; + } vfnunary0; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + enum vfunary1 { + RISCV_FVV_VSQRT, + RISCV_FVV_VRSQRT7, + RISCV_FVV_VREC7, + RISCV_FVV_VCLASS + } vfunary1; + uint8_t vd /* bits : 5 */; + } vfunary1; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } vfmvfs; + struct { + enum fvffunct6 { + RISCV_VF_VADD, + RISCV_VF_VSUB, + RISCV_VF_VMIN, + RISCV_VF_VMAX, + RISCV_VF_VSGNJ, + RISCV_VF_VSGNJN, + RISCV_VF_VSGNJX, + RISCV_VF_VDIV, + RISCV_VF_VRDIV, + RISCV_VF_VMUL, + RISCV_VF_VRSUB, + RISCV_VF_VSLIDE1UP, + RISCV_VF_VSLIDE1DOWN + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fvftype; + struct { + enum fvfmafunct6 { + RISCV_VF_VMADD, + RISCV_VF_VNMADD, + RISCV_VF_VMSUB, + RISCV_VF_VNMSUB, + RISCV_VF_VMACC, + RISCV_VF_VNMACC, + RISCV_VF_VMSAC, + RISCV_VF_VNMSAC + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fvfmatype; + struct { + enum fwvffunct6 { + RISCV_FWVF_VADD, + RISCV_FWVF_VSUB, + RISCV_FWVF_VMUL + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fwvftype; + struct { + enum fwvfmafunct6 { + RISCV_FWVF_VMACC, + RISCV_FWVF_VNMACC, + RISCV_FWVF_VMSAC, + RISCV_FWVF_VNMSAC + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fwvfmatype; + struct { + enum fwffunct6 { RISCV_FWF_VADD, RISCV_FWF_VSUB } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fwftype; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vfmerge; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vfmv; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vfmvsf; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth { RISCV_VLE8, RISCV_VLE16, RISCV_VLE32, RISCV_VLE64 } width; + uint8_t vd /* bits : 5 */; + } vlsegtype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vd /* bits : 5 */; + } vlsegfftype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vs3 /* bits : 5 */; + } vssegtype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vd /* bits : 5 */; + } vlssegtype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vs3 /* bits : 5 */; + } vsssegtype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vd /* bits : 5 */; + } vluxsegtype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vd /* bits : 5 */; + } vloxsegtype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vs3 /* bits : 5 */; + } vsuxsegtype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vs3 /* bits : 5 */; + } vsoxsegtype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t rs1 /* bits : 5 */; + enum vlewidth width; + uint8_t vd /* bits : 5 */; + } vlretype; + struct { + uint8_t nf /* bits : 3 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vs3 /* bits : 5 */; + } vsretype; + struct { + uint8_t rs1 /* bits : 5 */; + uint8_t vd_or_vs3 /* bits : 5 */; + enum vmlsop { RISCV_VLM, RISCV_VSM } op; + } vmtype; + struct { + enum mmfunct6 { + RISCV_MM_VMAND, + RISCV_MM_VMNAND, + RISCV_MM_VMANDN, + RISCV_MM_VMXOR, + RISCV_MM_VMOR, + RISCV_MM_VMNOR, + RISCV_MM_VMORN, + RISCV_MM_VMXNOR + } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } mmtype; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } vcpop_m; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } vfirst_m; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vmsbf_m; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vmsif_m; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vmsof_m; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } viota_m; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vd /* bits : 5 */; + } vid_v; + struct { + enum vvmfunct6 { RISCV_VVM_VMADC, RISCV_VVM_VMSBC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vvmtype; + struct { + enum vvmcfunct6 { RISCV_VVMC_VMADC, RISCV_VVMC_VMSBC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vvmctype; + struct { + enum vvmsfunct6 { RISCV_VVMS_VADC, RISCV_VVMS_VSBC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vvmstype; + struct { + enum vvcmpfunct6 { + RISCV_VVCMP_VMSEQ, + RISCV_VVCMP_VMSNE, + RISCV_VVCMP_VMSLTU, + RISCV_VVCMP_VMSLT, + RISCV_VVCMP_VMSLEU, + RISCV_VVCMP_VMSLE + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vvcmptype; + struct { + enum vxmfunct6 { RISCV_VXM_VMADC, RISCV_VXM_VMSBC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vxmtype; + struct { + enum vxmcfunct6 { RISCV_VXMC_VMADC, RISCV_VXMC_VMSBC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vxmctype; + struct { + enum vxmsfunct6 { RISCV_VXMS_VADC, RISCV_VXMS_VSBC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vxmstype; + struct { + enum vxcmpfunct6 { + RISCV_VXCMP_VMSEQ, + RISCV_VXCMP_VMSNE, + RISCV_VXCMP_VMSLTU, + RISCV_VXCMP_VMSLT, + RISCV_VXCMP_VMSLEU, + RISCV_VXCMP_VMSLE, + RISCV_VXCMP_VMSGTU, + RISCV_VXCMP_VMSGT + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vxcmptype; + struct { + enum vimfunct6 { RISCV_VIM_VMADC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vimtype; + struct { + enum vimcfunct6 { RISCV_VIMC_VMADC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vimctype; + struct { + enum vimsfunct6 { RISCV_VIMS_VADC } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vimstype; + struct { + enum vicmpfunct6 { + RISCV_VICMP_VMSEQ, + RISCV_VICMP_VMSNE, + RISCV_VICMP_VMSLEU, + RISCV_VICMP_VMSLE, + RISCV_VICMP_VMSGTU, + RISCV_VICMP_VMSGT + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t simm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vicmptype; + struct { + enum fvvmfunct6 { + RISCV_FVVM_VMFEQ, + RISCV_FVVM_VMFLE, + RISCV_FVVM_VMFLT, + RISCV_FVVM_VMFNE + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fvvmtype; + struct { + enum fvfmfunct6 { + RISCV_VFM_VMFEQ, + RISCV_VFM_VMFLE, + RISCV_VFM_VMFLT, + RISCV_VFM_VMFNE, + RISCV_VFM_VMFGT, + RISCV_VFM_VMFGE + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } fvfmtype; + struct { + enum rivvfunct6 { RISCV_IVV_VWREDSUMU, RISCV_IVV_VWREDSUM } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } rivvtype; + struct { + enum rmvvfunct6 { + RISCV_MVV_VREDSUM, + RISCV_MVV_VREDAND, + RISCV_MVV_VREDOR, + RISCV_MVV_VREDXOR, + RISCV_MVV_VREDMINU, + RISCV_MVV_VREDMIN, + RISCV_MVV_VREDMAXU, + RISCV_MVV_VREDMAX + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } rmvvtype; + struct { + enum rfvvfunct6 { + RISCV_FVV_VFREDOSUM, + RISCV_FVV_VFREDUSUM, + RISCV_FVV_VFREDMAX, + RISCV_FVV_VFREDMIN, + RISCV_FVV_VFWREDOSUM, + RISCV_FVV_VFWREDUSUM + } funct6; + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } rfvvtype; + struct { + enum cbop_zicbom { + RISCV_CBO_CLEAN, + RISCV_CBO_FLUSH, + RISCV_CBO_INVAL + } cbo_inval; + uint8_t rs1 /* bits : 5 */; + } riscv_zicbom; + uint8_t riscv_zicboz /* bits : 5 */; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vandn_vv; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vandn_vx; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vbrev_v; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vbrev8_v; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vrev8_v; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vclz_v; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vctz_v; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vcpop_v; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vrol_vv; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vrol_vx; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vror_vv; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vror_vx; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t uimm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vror_vi; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vwsll_vv; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vwsll_vx; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t uimm /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vwsll_vi; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vclmul_vv; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vclmul_vx; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vclmulh_vv; + struct { + uint8_t vm /* bits : 1 */; + uint8_t vs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vclmulh_vx; + struct { + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } vsha2ms_vv; + struct { + enum zvkfunct6 { RISCV_ZVK_VSHA2CH, RISCV_ZVK_VSHA2CL } funct6; + uint8_t vs2 /* bits : 5 */; + uint8_t vs1 /* bits : 5 */; + uint8_t vd /* bits : 5 */; + } zvksha2type; + struct { + uint8_t mop /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } zimop_mop_r; + struct { + uint8_t mop /* bits : 3 */; + uint8_t rs2 /* bits : 5 */; + uint8_t rs1 /* bits : 5 */; + uint8_t rd /* bits : 5 */; + } zimop_mop_rr; + uint8_t zcmop /* bits : 3 */; + } ast_node; +}; +#endif diff --git a/arch/RISCV/RISCVAst2Str.gen.inc b/arch/RISCV/RISCVAst2Str.gen.inc new file mode 100644 index 0000000000..e91273a44f --- /dev/null +++ b/arch/RISCV/RISCVAst2Str.gen.inc @@ -0,0 +1,3010 @@ +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ + +#ifndef __RISCVAST2STR_GEN_INC__ +#define __RISCVAST2STR_GEN_INC__ +#include +#include +#include + +#include "../../SStream.h" +#include "RISCVAst.gen.inc" +#include "RISCVAst2StrHelpers.h" +#include "RISCVAst2StrTbls.gen.inc" + +static void ast2str(struct ast *tree, SStream *ss, RVContext *ctx) { + switch (tree->ast_node_type) { + case RISCV_UTYPE: + utype_mnemonic(tree->ast_node.utype.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.utype.rd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_20(tree->ast_node.utype.imm, ss, ctx); + break; + case RISCV_JAL: + SStream_concat(ss, "jal"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_jal.rd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_21(tree->ast_node.riscv_jal.imm, ss, ctx); + break; + case RISCV_JALR: + SStream_concat(ss, "jalr"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_jalr.rd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_12(tree->ast_node.riscv_jalr.imm, ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.riscv_jalr.rs1, ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_BTYPE: + btype_mnemonic(tree->ast_node.btype.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.btype.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.btype.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_signed_13(tree->ast_node.btype.imm, ss, ctx); + break; + case RISCV_ITYPE: + itype_mnemonic(tree->ast_node.itype.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.itype.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.itype.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_signed_12(tree->ast_node.itype.imm, ss, ctx); + break; + case RISCV_SHIFTIOP: + shiftiop_mnemonic(tree->ast_node.shiftiop.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.shiftiop.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.shiftiop.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.shiftiop.shamt, ss, ctx); + break; + case RISCV_RTYPE: + rtype_mnemonic(tree->ast_node.rtype.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.rtype.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.rtype.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.rtype.rs2, ss, ctx); + break; + case RISCV_LOAD: + SStream_concat(ss, "l"); + size_mnemonic(tree->ast_node.load.width, ss); + if (tree->ast_node.load.is_unsigned) { + SStream_concat(ss, "u"); + } else { + SStream_concat(ss, ""); + } + if (tree->ast_node.load.aq) { + SStream_concat(ss, ".aq"); + } else { + SStream_concat(ss, ""); + } + if (tree->ast_node.load.rl) { + SStream_concat(ss, ".rl"); + } else { + SStream_concat(ss, ""); + } + spc(ss, ctx); + reg_name(tree->ast_node.load.rd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_12(tree->ast_node.load.imm, ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.load.rs1, ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_STORE: + SStream_concat(ss, "s"); + size_mnemonic(tree->ast_node.store.width, ss); + if (tree->ast_node.store.aq) { + SStream_concat(ss, ".aq"); + } else { + SStream_concat(ss, ""); + } + if (tree->ast_node.store.rl) { + SStream_concat(ss, ".rl"); + } else { + SStream_concat(ss, ""); + } + spc(ss, ctx); + reg_name(tree->ast_node.store.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_signed_12(tree->ast_node.store.imm, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + reg_name(tree->ast_node.store.rs1, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_ADDIW: + SStream_concat(ss, "addiw"); + spc(ss, ctx); + reg_name(tree->ast_node.addiw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.addiw.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_signed_12(tree->ast_node.addiw.imm, ss, ctx); + break; + case RISCV_RTYPEW: + rtypew_mnemonic(tree->ast_node.rtypew.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.rtypew.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.rtypew.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.rtypew.rs2, ss, ctx); + break; + case RISCV_SHIFTIWOP: + shiftiwop_mnemonic(tree->ast_node.shiftiwop.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.shiftiwop.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.shiftiwop.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.shiftiwop.shamt, ss, ctx); + break; + case RISCV_FENCE: + SStream_concat(ss, "fence"); + spc(ss, ctx); + fence_bits(tree->ast_node.fence.pred, ss, ctx); + sep(ss, ctx); + fence_bits(tree->ast_node.fence.succ, ss, ctx); + break; + case RISCV_FENCE_TSO: + SStream_concat(ss, "fence.tso"); + spc(ss, ctx); + fence_bits(tree->ast_node.fence_tso.pred, ss, ctx); + sep(ss, ctx); + fence_bits(tree->ast_node.fence_tso.succ, ss, ctx); + break; + case RISCV_ECALL: + SStream_concat(ss, "ecall"); + break; + case RISCV_MRET: + SStream_concat(ss, "mret"); + break; + case RISCV_SRET: + SStream_concat(ss, "sret"); + break; + case RISCV_EBREAK: + SStream_concat(ss, "ebreak"); + break; + case RISCV_WFI: + SStream_concat(ss, "wfi"); + break; + case RISCV_SFENCE_VMA: + SStream_concat(ss, "sfence.vma"); + spc(ss, ctx); + reg_name(tree->ast_node.sfence_vma.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sfence_vma.rs2, ss, ctx); + break; + case RISCV_FENCEI: + SStream_concat(ss, "fence.i"); + break; + case RISCV_LOADRES: + SStream_concat(ss, "lr."); + size_mnemonic(tree->ast_node.loadres.width, ss); + if (tree->ast_node.loadres.aq) { + SStream_concat(ss, ".aq"); + } else { + SStream_concat(ss, ""); + } + if (tree->ast_node.loadres.rl) { + SStream_concat(ss, ".rl"); + } else { + SStream_concat(ss, ""); + } + spc(ss, ctx); + reg_name(tree->ast_node.loadres.rd, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.loadres.rs1, ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_STORECON: + SStream_concat(ss, "sc."); + size_mnemonic(tree->ast_node.storecon.width, ss); + if (tree->ast_node.storecon.aq) { + SStream_concat(ss, ".aq"); + } else { + SStream_concat(ss, ""); + } + if (tree->ast_node.storecon.rl) { + SStream_concat(ss, ".rl"); + } else { + SStream_concat(ss, ""); + } + spc(ss, ctx); + reg_name(tree->ast_node.storecon.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.storecon.rs2, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.storecon.rs1, ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_AMO: + amo_mnemonic(tree->ast_node.amo.op, ss); + SStream_concat(ss, "."); + size_mnemonic(tree->ast_node.amo.width, ss); + if (tree->ast_node.amo.aq) { + SStream_concat(ss, ".aq"); + } else { + SStream_concat(ss, ""); + } + if (tree->ast_node.amo.rl) { + SStream_concat(ss, ".rl"); + } else { + SStream_concat(ss, ""); + } + spc(ss, ctx); + reg_name(tree->ast_node.amo.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.amo.rs2, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.amo.rs1, ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_C_NOP: + SStream_concat(ss, "c.nop"); + break; + case RISCV_C_ADDI4SPN: + SStream_concat(ss, "c.addi4spn"); + spc(ss, ctx); + creg_name(tree->ast_node.c_addi4spn.rdc, ss, ctx); + sep(ss, ctx); + hex_bits_10(tree->ast_node.c_addi4spn.nzimm << 2 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_LW: + SStream_concat(ss, "c.lw"); + spc(ss, ctx); + creg_name(tree->ast_node.c_lw.rdc, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_lw.rsc, ss, ctx); + sep(ss, ctx); + hex_bits_7(tree->ast_node.c_lw.uimm << 2 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_LD: + SStream_concat(ss, "c.ld"); + spc(ss, ctx); + creg_name(tree->ast_node.c_ld.rdc, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_ld.rsc, ss, ctx); + sep(ss, ctx); + hex_bits_8(tree->ast_node.c_ld.uimm << 3 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_SW: + SStream_concat(ss, "c.sw"); + spc(ss, ctx); + creg_name(tree->ast_node.c_sw.rsc1, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_sw.rsc2, ss, ctx); + sep(ss, ctx); + hex_bits_7(tree->ast_node.c_sw.uimm << 2 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_SD: + SStream_concat(ss, "c.sd"); + spc(ss, ctx); + creg_name(tree->ast_node.c_sd.rsc1, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_sd.rsc2, ss, ctx); + sep(ss, ctx); + hex_bits_8(tree->ast_node.c_sd.uimm << 3 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_ADDI: + SStream_concat(ss, "c.addi"); + spc(ss, ctx); + reg_name(tree->ast_node.c_addi.rsd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_6(tree->ast_node.c_addi.nzi, ss, ctx); + break; + case RISCV_C_JAL: + SStream_concat(ss, "c.jal"); + spc(ss, ctx); + hex_bits_signed_12(tree->ast_node.c_jal << 1 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_ADDIW: + SStream_concat(ss, "c.addiw"); + spc(ss, ctx); + reg_name(tree->ast_node.c_addiw.rsd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_6(tree->ast_node.c_addiw.imm, ss, ctx); + break; + case RISCV_C_LI: + SStream_concat(ss, "c.li"); + spc(ss, ctx); + reg_name(tree->ast_node.c_li.rd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_6(tree->ast_node.c_li.imm, ss, ctx); + break; + case RISCV_C_ADDI16SP: + SStream_concat(ss, "c.addi16sp"); + spc(ss, ctx); + hex_bits_signed_6(tree->ast_node.c_addi16sp, ss, ctx); + break; + case RISCV_C_LUI: + SStream_concat(ss, "c.lui"); + spc(ss, ctx); + reg_name(tree->ast_node.c_lui.rd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_6(tree->ast_node.c_lui.imm, ss, ctx); + break; + case RISCV_C_SRLI: + SStream_concat(ss, "c.srli"); + spc(ss, ctx); + creg_name(tree->ast_node.c_srli.rsd, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_srli.shamt, ss, ctx); + break; + case RISCV_C_SRAI: + SStream_concat(ss, "c.srai"); + spc(ss, ctx); + creg_name(tree->ast_node.c_srai.rsd, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_srai.shamt, ss, ctx); + break; + case RISCV_C_ANDI: + SStream_concat(ss, "c.andi"); + spc(ss, ctx); + creg_name(tree->ast_node.c_andi.rsd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_6(tree->ast_node.c_andi.imm, ss, ctx); + break; + case RISCV_C_SUB: + SStream_concat(ss, "c.sub"); + spc(ss, ctx); + creg_name(tree->ast_node.c_sub.rsd, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_sub.rs2, ss, ctx); + break; + case RISCV_C_XOR: + SStream_concat(ss, "c.xor"); + spc(ss, ctx); + creg_name(tree->ast_node.c_xor.rsd, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_xor.rs2, ss, ctx); + break; + case RISCV_C_OR: + SStream_concat(ss, "c.or"); + spc(ss, ctx); + creg_name(tree->ast_node.c_or.rsd, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_or.rs2, ss, ctx); + break; + case RISCV_C_AND: + SStream_concat(ss, "c.and"); + spc(ss, ctx); + creg_name(tree->ast_node.c_and.rsd, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_and.rs2, ss, ctx); + break; + case RISCV_C_SUBW: + SStream_concat(ss, "c.subw"); + spc(ss, ctx); + creg_name(tree->ast_node.c_subw.rsd, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_subw.rs2, ss, ctx); + break; + case RISCV_C_ADDW: + SStream_concat(ss, "c.addw"); + spc(ss, ctx); + creg_name(tree->ast_node.c_addw.rsd, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_addw.rs2, ss, ctx); + break; + case RISCV_C_J: + SStream_concat(ss, "c.j"); + spc(ss, ctx); + hex_bits_signed_12(tree->ast_node.c_j << 1 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_BEQZ: + SStream_concat(ss, "c.beqz"); + spc(ss, ctx); + creg_name(tree->ast_node.c_beqz.rs, ss, ctx); + sep(ss, ctx); + hex_bits_signed_8(tree->ast_node.c_beqz.imm, ss, ctx); + break; + case RISCV_C_BNEZ: + SStream_concat(ss, "c.bnez"); + spc(ss, ctx); + creg_name(tree->ast_node.c_bnez.rs, ss, ctx); + sep(ss, ctx); + hex_bits_signed_8(tree->ast_node.c_bnez.imm, ss, ctx); + break; + case RISCV_C_SLLI: + SStream_concat(ss, "c.slli"); + spc(ss, ctx); + reg_name(tree->ast_node.c_slli.rsd, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_slli.shamt, ss, ctx); + break; + case RISCV_C_LWSP: + SStream_concat(ss, "c.lwsp"); + spc(ss, ctx); + reg_name(tree->ast_node.c_lwsp.rd, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_lwsp.uimm, ss, ctx); + break; + case RISCV_C_LDSP: + SStream_concat(ss, "c.ldsp"); + spc(ss, ctx); + reg_name(tree->ast_node.c_ldsp.rd, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_ldsp.uimm, ss, ctx); + break; + case RISCV_C_SWSP: + SStream_concat(ss, "c.swsp"); + spc(ss, ctx); + reg_name(tree->ast_node.c_swsp.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_swsp.uimm, ss, ctx); + break; + case RISCV_C_SDSP: + SStream_concat(ss, "c.sdsp"); + spc(ss, ctx); + reg_name(tree->ast_node.c_sdsp.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_sdsp.uimm, ss, ctx); + break; + case RISCV_C_JR: + SStream_concat(ss, "c.jr"); + spc(ss, ctx); + reg_name(tree->ast_node.c_jr, ss, ctx); + break; + case RISCV_C_JALR: + SStream_concat(ss, "c.jalr"); + spc(ss, ctx); + reg_name(tree->ast_node.c_jalr, ss, ctx); + break; + case RISCV_C_MV: + SStream_concat(ss, "c.mv"); + spc(ss, ctx); + reg_name(tree->ast_node.c_mv.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.c_mv.rs2, ss, ctx); + break; + case RISCV_C_EBREAK: + SStream_concat(ss, "c.ebreak"); + break; + case RISCV_C_ADD: + SStream_concat(ss, "c.add"); + spc(ss, ctx); + reg_name(tree->ast_node.c_add.rsd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.c_add.rs2, ss, ctx); + break; + case RISCV_MUL: + if ((tree->ast_node.mul.mul_op.high == 1) && + (tree->ast_node.mul.mul_op.signed_rs1 == 1) && + (tree->ast_node.mul.mul_op.signed_rs2 == 1)) { + SStream_concat(ss, "mulh"); + } else if ((tree->ast_node.mul.mul_op.high == 1) && + (tree->ast_node.mul.mul_op.signed_rs1 == 0) && + (tree->ast_node.mul.mul_op.signed_rs2 == 0)) { + SStream_concat(ss, "mulhu"); + } else if ((tree->ast_node.mul.mul_op.high == 1) && + (tree->ast_node.mul.mul_op.signed_rs1 == 1) && + (tree->ast_node.mul.mul_op.signed_rs2 == 0)) { + SStream_concat(ss, "mulhsu"); + } else if ((tree->ast_node.mul.mul_op.high == 0) && + (tree->ast_node.mul.mul_op.signed_rs1 == 1) && + (tree->ast_node.mul.mul_op.signed_rs2 == 1)) { + SStream_concat(ss, "mul"); + } else + ; + spc(ss, ctx); + reg_name(tree->ast_node.mul.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.mul.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.mul.rs2, ss, ctx); + break; + case RISCV_DIV: + SStream_concat(ss, "div"); + if (tree->ast_node.div.s) { + SStream_concat(ss, ""); + } else { + SStream_concat(ss, "u"); + } + spc(ss, ctx); + reg_name(tree->ast_node.div.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.div.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.div.rs2, ss, ctx); + break; + case RISCV_REM: + SStream_concat(ss, "rem"); + if (tree->ast_node.rem.s) { + SStream_concat(ss, ""); + } else { + SStream_concat(ss, "u"); + } + spc(ss, ctx); + reg_name(tree->ast_node.rem.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.rem.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.rem.rs2, ss, ctx); + break; + case RISCV_MULW: + SStream_concat(ss, "mulw"); + spc(ss, ctx); + reg_name(tree->ast_node.mulw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.mulw.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.mulw.rs2, ss, ctx); + break; + case RISCV_DIVW: + SStream_concat(ss, "div"); + if (tree->ast_node.divw.s) { + SStream_concat(ss, ""); + } else { + SStream_concat(ss, "u"); + } + SStream_concat(ss, "w"); + spc(ss, ctx); + reg_name(tree->ast_node.divw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.divw.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.divw.rs2, ss, ctx); + break; + case RISCV_REMW: + SStream_concat(ss, "rem"); + if (tree->ast_node.remw.s) { + SStream_concat(ss, ""); + } else { + SStream_concat(ss, "u"); + } + SStream_concat(ss, "w"); + spc(ss, ctx); + reg_name(tree->ast_node.remw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.remw.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.remw.rs2, ss, ctx); + break; + case RISCV_CSRImm: + csr_mnemonic(tree->ast_node.csrimm.op, ss); + SStream_concat(ss, "i"); + spc(ss, ctx); + reg_name(tree->ast_node.csrimm.rd, ss, ctx); + sep(ss, ctx); + csr_name_map(tree->ast_node.csrimm.csr, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.csrimm.imm, ss, ctx); + break; + case RISCV_CSRReg: + csr_mnemonic(tree->ast_node.csrreg.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.csrreg.rd, ss, ctx); + sep(ss, ctx); + csr_name_map(tree->ast_node.csrreg.csr, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.csrreg.rs1, ss, ctx); + break; + case RISCV_C_NOP_HINT: + SStream_concat(ss, "c.nop.hint."); + hex_bits_6(tree->ast_node.c_nop_hint, ss, ctx); + break; + case RISCV_C_ADDI_HINT: + SStream_concat(ss, "c.addi.hint."); + reg_name(tree->ast_node.c_addi_hint, ss, ctx); + break; + case RISCV_C_LI_HINT: + SStream_concat(ss, "c.li.hint."); + hex_bits_6(tree->ast_node.c_li_hint, ss, ctx); + break; + case RISCV_C_LUI_HINT: + SStream_concat(ss, "c.lui.hint."); + hex_bits_6(tree->ast_node.c_lui_hint, ss, ctx); + break; + case RISCV_C_MV_HINT: + SStream_concat(ss, "c.mv.hint."); + reg_name(tree->ast_node.c_mv_hint, ss, ctx); + break; + case RISCV_C_ADD_HINT: + SStream_concat(ss, "c.add.hint."); + reg_name(tree->ast_node.c_add_hint, ss, ctx); + break; + case RISCV_C_SLLI_HINT: + SStream_concat(ss, "c.slli.hint."); + reg_name(tree->ast_node.c_slli_hint.rsd, ss, ctx); + SStream_concat(ss, "."); + hex_bits_6(tree->ast_node.c_slli_hint.shamt, ss, ctx); + break; + case RISCV_C_SRLI_HINT: + SStream_concat(ss, "c.srli.hint."); + creg_name(tree->ast_node.c_srli_hint, ss, ctx); + break; + case RISCV_C_SRAI_HINT: + SStream_concat(ss, "c.srai.hint."); + creg_name(tree->ast_node.c_srai_hint, ss, ctx); + break; + case RISCV_FENCE_RESERVED: + SStream_concat(ss, "fence.reserved."); + fence_bits(tree->ast_node.fence_reserved.pred, ss, ctx); + SStream_concat(ss, "."); + fence_bits(tree->ast_node.fence_reserved.succ, ss, ctx); + SStream_concat(ss, "."); + reg_name(tree->ast_node.fence_reserved.rs, ss, ctx); + SStream_concat(ss, "."); + reg_name(tree->ast_node.fence_reserved.rd, ss, ctx); + SStream_concat(ss, "."); + hex_bits_4(tree->ast_node.fence_reserved.fm, ss, ctx); + break; + case RISCV_FENCEI_RESERVED: + SStream_concat(ss, "fence.i.reserved."); + reg_name(tree->ast_node.fencei_reserved.rd, ss, ctx); + SStream_concat(ss, "."); + reg_name(tree->ast_node.fencei_reserved.rs, ss, ctx); + SStream_concat(ss, "."); + hex_bits_12(tree->ast_node.fencei_reserved.imm, ss, ctx); + break; + case RISCV_LOAD_FP: + SStream_concat(ss, "fl"); + size_mnemonic(tree->ast_node.load_fp.width, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.load_fp.rd, ss, ctx); + sep(ss, ctx); + hex_bits_signed_12(tree->ast_node.load_fp.imm, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + reg_name(tree->ast_node.load_fp.rs1, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_STORE_FP: + SStream_concat(ss, "fs"); + size_mnemonic(tree->ast_node.store_fp.width, ss); + spc(ss, ctx); + freg_name(tree->ast_node.store_fp.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_signed_12(tree->ast_node.store_fp.imm, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + reg_name(tree->ast_node.store_fp.rs1, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_F_MADD_TYPE_S: + f_madd_type_mnemonic_S(tree->ast_node.f_madd_type_s.op, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_s.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_s.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_s.rs2, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_s.rs3, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_madd_type_s.rm, ss); + break; + case RISCV_F_BIN_RM_TYPE_S: + f_bin_rm_type_mnemonic_S(tree->ast_node.f_bin_rm_type_s.op, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_s.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_s.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_s.rs2, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_bin_rm_type_s.rm, ss); + break; + case RISCV_F_UN_RM_FF_TYPE_S: + if (tree->ast_node.f_un_rm_ff_type_s.fsqrt_s == RISCV_FSQRT_S) { + SStream_concat(ss, "fsqrt.s"); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_ff_type_s.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_ff_type_s.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_ff_type_s.rm, ss); + } + break; + case RISCV_F_UN_RM_FX_TYPE_S: + f_un_rm_fx_type_mnemonic_S(tree->ast_node.f_un_rm_fx_type_s.fcvt_lu_s, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_un_rm_fx_type_s.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_fx_type_s.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_fx_type_s.rm, ss); + break; + case RISCV_F_UN_RM_XF_TYPE_S: + f_un_rm_xf_type_mnemonic_S(tree->ast_node.f_un_rm_xf_type_s.fcvt_s_lu, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_xf_type_s.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.f_un_rm_xf_type_s.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_xf_type_s.rm, ss); + break; + case RISCV_F_BIN_TYPE_F_S: + f_bin_type_mnemonic_f_S(tree->ast_node.f_bin_type_f_s.fmax_s, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_type_f_s.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_type_f_s.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_type_f_s.rs2, ss, ctx); + break; + case RISCV_F_BIN_TYPE_X_S: + f_bin_type_mnemonic_x_S(tree->ast_node.f_bin_type_x_s.fle_s, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_bin_type_x_s.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_type_x_s.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_type_x_s.rs2, ss, ctx); + break; + case RISCV_F_UN_TYPE_X_S: + f_un_type_mnemonic_x_S(tree->ast_node.f_un_type_x_s.fmv_x_w, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_un_type_x_s.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.f_un_type_x_s.rs1, ss, ctx); + break; + case RISCV_F_UN_TYPE_F_S: + f_un_type_mnemonic_f_S(tree->ast_node.f_un_type_f_s.fmv_w_x, ss); + spc(ss, ctx); + freg_name(tree->ast_node.f_un_type_f_s.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.f_un_type_f_s.rs1, ss, ctx); + break; + case RISCV_C_FLWSP: + SStream_concat(ss, "c.flwsp"); + spc(ss, ctx); + freg_name(tree->ast_node.c_flwsp.rd, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_flwsp.imm, ss, ctx); + break; + case RISCV_C_FSWSP: + SStream_concat(ss, "c.fswsp"); + spc(ss, ctx); + freg_name(tree->ast_node.c_fswsp.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_fswsp.uimm, ss, ctx); + break; + case RISCV_C_FLW: + SStream_concat(ss, "c.flw"); + spc(ss, ctx); + creg_name(tree->ast_node.c_flw.rdc, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_flw.rsc, ss, ctx); + sep(ss, ctx); + hex_bits_7(tree->ast_node.c_flw.uimm << 2 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_FSW: + SStream_concat(ss, "c.fsw"); + spc(ss, ctx); + creg_name(tree->ast_node.c_fsw.rsc1, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_fsw.rsc2, ss, ctx); + sep(ss, ctx); + hex_bits_7(tree->ast_node.c_fsw.uimm << 2 | 0x0 << 0, ss, ctx); + break; + case RISCV_F_MADD_TYPE_D: + f_madd_type_mnemonic_D(tree->ast_node.f_madd_type_d.op, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_d.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_d.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_d.rs2, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_d.rs3, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_madd_type_d.rm, ss); + break; + case RISCV_F_BIN_RM_TYPE_D: + f_bin_rm_type_mnemonic_D(tree->ast_node.f_bin_rm_type_d.op, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_d.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_d.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_d.rs2, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_bin_rm_type_d.rm, ss); + break; + case RISCV_F_UN_RM_FF_TYPE_D: + f_un_rm_ff_type_mnemonic_D(tree->ast_node.f_un_rm_ff_type_d.fcvt_d_s, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_ff_type_d.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_ff_type_d.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_ff_type_d.rm, ss); + break; + case RISCV_F_UN_RM_FX_TYPE_D: + f_un_rm_fx_type_mnemonic_D(tree->ast_node.f_un_rm_fx_type_d.fcvt_lu_d, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_un_rm_fx_type_d.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_fx_type_d.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_fx_type_d.rm, ss); + break; + case RISCV_F_UN_RM_XF_TYPE_D: + f_un_rm_xf_type_mnemonic_D(tree->ast_node.f_un_rm_xf_type_d.fcvt_d_lu, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_xf_type_d.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.f_un_rm_xf_type_d.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_xf_type_d.rm, ss); + break; + case RISCV_F_BIN_F_TYPE_D: + f_bin_f_type_mnemonic_D(tree->ast_node.f_bin_f_type_d.fmax_d, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_f_type_d.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_f_type_d.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_f_type_d.rs2, ss, ctx); + break; + case RISCV_F_BIN_X_TYPE_D: + f_bin_x_type_mnemonic_D(tree->ast_node.f_bin_x_type_d.fle_d, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_bin_x_type_d.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_x_type_d.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_x_type_d.rs2, ss, ctx); + break; + case RISCV_F_UN_X_TYPE_D: + f_un_x_type_mnemonic_D(tree->ast_node.f_un_x_type_d.fmv_x_d, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_un_x_type_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.f_un_x_type_d.rs1, ss, ctx); + break; + case RISCV_F_UN_F_TYPE_D: + f_un_f_type_mnemonic_D(tree->ast_node.f_un_f_type_d.fmv_d_x, ss); + spc(ss, ctx); + freg_name(tree->ast_node.f_un_f_type_d.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.f_un_f_type_d.rs1, ss, ctx); + break; + case RISCV_C_FLDSP: + SStream_concat(ss, "c.fldsp"); + spc(ss, ctx); + freg_name(tree->ast_node.c_fldsp.rd, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_fldsp.uimm, ss, ctx); + break; + case RISCV_C_FSDSP: + SStream_concat(ss, "c.fsdsp"); + spc(ss, ctx); + freg_name(tree->ast_node.c_fsdsp.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.c_fsdsp.uimm, ss, ctx); + break; + case RISCV_C_FLD: + SStream_concat(ss, "c.fld"); + spc(ss, ctx); + creg_name(tree->ast_node.c_fld.rdc, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_fld.rsc, ss, ctx); + sep(ss, ctx); + hex_bits_8(tree->ast_node.c_fld.uimm << 3 | 0x0 << 0, ss, ctx); + break; + case RISCV_C_FSD: + SStream_concat(ss, "c.fsd"); + spc(ss, ctx); + creg_name(tree->ast_node.c_fsd.rsc1, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_fsd.rsc2, ss, ctx); + sep(ss, ctx); + hex_bits_8(tree->ast_node.c_fsd.uimm << 3 | 0x0 << 0, ss, ctx); + break; + case RISCV_SINVAL_VMA: + SStream_concat(ss, "sinval.vma"); + spc(ss, ctx); + reg_name(tree->ast_node.sinval_vma.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sinval_vma.rs2, ss, ctx); + break; + case RISCV_SFENCE_W_INVAL: + SStream_concat(ss, "sfence.w.inval"); + break; + case RISCV_SFENCE_INVAL_IR: + SStream_concat(ss, "sfence.inval.ir"); + break; + case RISCV_SLLIUW: + SStream_concat(ss, "slli.uw"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_slliuw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_slliuw.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.riscv_slliuw.shamt, ss, ctx); + break; + case RISCV_ZBA_RTYPEUW: + zba_rtypeuw_mnemonic(tree->ast_node.zba_rtypeuw.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zba_rtypeuw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zba_rtypeuw.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zba_rtypeuw.rs2, ss, ctx); + break; + case RISCV_ZBA_RTYPE: + zba_rtype_mnemonic(tree->ast_node.zba_rtype.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zba_rtype.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zba_rtype.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zba_rtype.rs2, ss, ctx); + break; + case RISCV_RORIW: + SStream_concat(ss, "roriw"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_roriw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_roriw.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.riscv_roriw.shamt, ss, ctx); + break; + case RISCV_RORI: + SStream_concat(ss, "rori"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_rori.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_rori.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.riscv_rori.shamt, ss, ctx); + break; + case RISCV_ZBB_RTYPEW: + zbb_rtypew_mnemonic(tree->ast_node.zbb_rtypew.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zbb_rtypew.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbb_rtypew.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbb_rtypew.rs2, ss, ctx); + break; + case RISCV_ZBB_RTYPE: + zbb_rtype_mnemonic(tree->ast_node.zbb_rtype.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zbb_rtype.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbb_rtype.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbb_rtype.rs2, ss, ctx); + break; + case RISCV_ZBB_EXTOP: + zbb_extop_mnemonic(tree->ast_node.zbb_extop.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zbb_extop.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbb_extop.rs1, ss, ctx); + break; + case RISCV_REV8: + SStream_concat(ss, "rev8"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_rev8.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_rev8.rs1, ss, ctx); + break; + case RISCV_ORCB: + SStream_concat(ss, "orc.b"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_orcb.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_orcb.rs1, ss, ctx); + break; + case RISCV_CPOP: + SStream_concat(ss, "cpop"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_cpop.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_cpop.rs1, ss, ctx); + break; + case RISCV_CPOPW: + SStream_concat(ss, "cpopw"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_cpopw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_cpopw.rs1, ss, ctx); + break; + case RISCV_CLZ: + SStream_concat(ss, "clz"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_clz.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_clz.rs1, ss, ctx); + break; + case RISCV_CLZW: + SStream_concat(ss, "clzw"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_clzw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_clzw.rs1, ss, ctx); + break; + case RISCV_CTZ: + SStream_concat(ss, "ctz"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_ctz.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_ctz.rs1, ss, ctx); + break; + case RISCV_CTZW: + SStream_concat(ss, "ctzw"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_ctzw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_ctzw.rs1, ss, ctx); + break; + case RISCV_CLMUL: + SStream_concat(ss, "clmul"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_clmul.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_clmul.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_clmul.rs2, ss, ctx); + break; + case RISCV_CLMULH: + SStream_concat(ss, "clmulh"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_clmulh.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_clmulh.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_clmulh.rs2, ss, ctx); + break; + case RISCV_CLMULR: + SStream_concat(ss, "clmulr"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_clmulr.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_clmulr.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_clmulr.rs2, ss, ctx); + break; + case RISCV_ZBS_IOP: + zbs_iop_mnemonic(tree->ast_node.zbs_iop.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zbs_iop.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbs_iop.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_6(tree->ast_node.zbs_iop.shamt, ss, ctx); + break; + case RISCV_ZBS_RTYPE: + zbs_rtype_mnemonic(tree->ast_node.zbs_rtype.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zbs_rtype.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbs_rtype.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbs_rtype.rs2, ss, ctx); + break; + case RISCV_C_LBU: + SStream_concat(ss, "c.lbu"); + spc(ss, ctx); + creg_name(tree->ast_node.c_lbu.rdc, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.c_lbu.uimm, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + creg_name(tree->ast_node.c_lbu.rs1c, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_C_LHU: + SStream_concat(ss, "c.lhu"); + spc(ss, ctx); + creg_name(tree->ast_node.c_lhu.rdc, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.c_lhu.uimm, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + creg_name(tree->ast_node.c_lhu.rs1c, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_C_LH: + SStream_concat(ss, "c.lh"); + spc(ss, ctx); + creg_name(tree->ast_node.c_lh.rdc, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.c_lh.uimm, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + creg_name(tree->ast_node.c_lh.rs1c, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_C_SB: + SStream_concat(ss, "c.sb"); + spc(ss, ctx); + creg_name(tree->ast_node.c_sb.rs2c, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.c_sb.uimm, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + creg_name(tree->ast_node.c_sb.rs1c, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_C_SH: + SStream_concat(ss, "c.sh"); + spc(ss, ctx); + creg_name(tree->ast_node.c_sh.rs1c, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.c_sh.uimm, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + creg_name(tree->ast_node.c_sh.rs2c, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_C_ZEXT_B: + SStream_concat(ss, "c.zext.b"); + spc(ss, ctx); + creg_name(tree->ast_node.c_zext_b, ss, ctx); + break; + case RISCV_C_SEXT_B: + SStream_concat(ss, "c.sext.b"); + spc(ss, ctx); + creg_name(tree->ast_node.c_sext_b, ss, ctx); + break; + case RISCV_C_ZEXT_H: + SStream_concat(ss, "c.zext.h"); + spc(ss, ctx); + creg_name(tree->ast_node.c_zext_h, ss, ctx); + break; + case RISCV_C_SEXT_H: + SStream_concat(ss, "c.sext.h"); + spc(ss, ctx); + creg_name(tree->ast_node.c_sext_h, ss, ctx); + break; + case RISCV_C_ZEXT_W: + SStream_concat(ss, "c.zext.w"); + spc(ss, ctx); + creg_name(tree->ast_node.c_zext_w, ss, ctx); + break; + case RISCV_C_NOT: + SStream_concat(ss, "c.not"); + spc(ss, ctx); + creg_name(tree->ast_node.c_not, ss, ctx); + break; + case RISCV_C_MUL: + SStream_concat(ss, "c.mul"); + spc(ss, ctx); + creg_name(tree->ast_node.c_mul.rsdc, ss, ctx); + sep(ss, ctx); + creg_name(tree->ast_node.c_mul.rs2c, ss, ctx); + break; + case RISCV_F_BIN_RM_TYPE_H: + f_bin_rm_type_mnemonic_H(tree->ast_node.f_bin_rm_type_h.op, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_h.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_h.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_rm_type_h.rs2, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_bin_rm_type_h.rm, ss); + break; + case RISCV_F_MADD_TYPE_H: + f_madd_type_mnemonic_H(tree->ast_node.f_madd_type_h.op, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_h.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_h.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_h.rs2, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_madd_type_h.rs3, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_madd_type_h.rm, ss); + break; + case RISCV_F_BIN_F_TYPE_H: + f_bin_f_type_mnemonic_H(tree->ast_node.f_bin_f_type_h.fmax_h, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_f_type_h.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_f_type_h.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_f_type_h.rs2, ss, ctx); + break; + case RISCV_F_BIN_X_TYPE_H: + f_bin_x_type_mnemonic_H(tree->ast_node.f_bin_x_type_h.fle_h, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_bin_x_type_h.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_x_type_h.rs1, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_bin_x_type_h.rs2, ss, ctx); + break; + case RISCV_F_UN_RM_FF_TYPE_H: + f_un_rm_ff_type_mnemonic_H(tree->ast_node.f_un_rm_ff_type_h.fcvt_d_h, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_ff_type_h.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_ff_type_h.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_ff_type_h.rm, ss); + break; + case RISCV_F_UN_RM_FX_TYPE_H: + f_un_rm_fx_type_mnemonic_H(tree->ast_node.f_un_rm_fx_type_h.fcvt_lu_h, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_un_rm_fx_type_h.rd, ss, ctx); + sep(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_fx_type_h.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_fx_type_h.rm, ss); + break; + case RISCV_F_UN_RM_XF_TYPE_H: + f_un_rm_xf_type_mnemonic_H(tree->ast_node.f_un_rm_xf_type_h.fcvt_h_lu, ss); + spc(ss, ctx); + freg_or_reg_name(tree->ast_node.f_un_rm_xf_type_h.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.f_un_rm_xf_type_h.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.f_un_rm_xf_type_h.rm, ss); + break; + case RISCV_F_UN_F_TYPE_H: + f_un_f_type_mnemonic_H(tree->ast_node.f_un_f_type_h.fmv_h_x, ss); + spc(ss, ctx); + freg_name(tree->ast_node.f_un_f_type_h.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.f_un_f_type_h.rs1, ss, ctx); + break; + case RISCV_F_UN_X_TYPE_H: + f_un_x_type_mnemonic_H(tree->ast_node.f_un_x_type_h.fmv_x_h, ss); + spc(ss, ctx); + reg_name(tree->ast_node.f_un_x_type_h.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.f_un_x_type_h.rs1, ss, ctx); + break; + case RISCV_FLI_H: + SStream_concat(ss, "fli.h"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fli_h.rd, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.riscv_fli_h.constantidx, ss, ctx); + break; + case RISCV_FLI_S: + SStream_concat(ss, "fli.s"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fli_s.rd, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.riscv_fli_s.constantidx, ss, ctx); + break; + case RISCV_FLI_D: + SStream_concat(ss, "fli.d"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fli_d.rd, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.riscv_fli_d.constantidx, ss, ctx); + break; + case RISCV_FMINM_H: + SStream_concat(ss, "fminm.h"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_h.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_h.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_h.rs2, ss, ctx); + break; + case RISCV_FMAXM_H: + SStream_concat(ss, "fmaxm.h"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_h.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_h.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_h.rs2, ss, ctx); + break; + case RISCV_FMINM_S: + SStream_concat(ss, "fminm.s"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_s.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_s.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_s.rs2, ss, ctx); + break; + case RISCV_FMAXM_S: + SStream_concat(ss, "fmaxm.s"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_s.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_s.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_s.rs2, ss, ctx); + break; + case RISCV_FMINM_D: + SStream_concat(ss, "fminm.d"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_d.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fminm_d.rs2, ss, ctx); + break; + case RISCV_FMAXM_D: + SStream_concat(ss, "fmaxm.d"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_d.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fmaxm_d.rs2, ss, ctx); + break; + case RISCV_FROUND_H: + SStream_concat(ss, "fround.h"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fround_h.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fround_h.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.riscv_fround_h.rm, ss); + break; + case RISCV_FROUNDNX_H: + SStream_concat(ss, "froundnx.h"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_froundnx_h.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_froundnx_h.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.riscv_froundnx_h.rm, ss); + break; + case RISCV_FROUND_S: + SStream_concat(ss, "fround.s"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fround_s.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fround_s.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.riscv_fround_s.rm, ss); + break; + case RISCV_FROUNDNX_S: + SStream_concat(ss, "froundnx.s"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_froundnx_s.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_froundnx_s.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.riscv_froundnx_s.rm, ss); + break; + case RISCV_FROUND_D: + SStream_concat(ss, "fround.d"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fround_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fround_d.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.riscv_fround_d.rm, ss); + break; + case RISCV_FROUNDNX_D: + SStream_concat(ss, "froundnx.d"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_froundnx_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_froundnx_d.rs1, ss, ctx); + sep(ss, ctx); + frm_mnemonic(tree->ast_node.riscv_froundnx_d.rm, ss); + break; + case RISCV_FMVH_X_D: + SStream_concat(ss, "fmvh.x.d"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_fmvh_x_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fmvh_x_d.rs1, ss, ctx); + break; + case RISCV_FMVP_D_X: + SStream_concat(ss, "fmvp.d.x"); + spc(ss, ctx); + freg_name(tree->ast_node.riscv_fmvp_d_x.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_fmvp_d_x.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_fmvp_d_x.rs2, ss, ctx); + break; + case RISCV_FLEQ_H: + SStream_concat(ss, "fleq.h"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_fleq_h.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fleq_h.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fleq_h.rs2, ss, ctx); + break; + case RISCV_FLTQ_H: + SStream_concat(ss, "fltq.h"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_fltq_h.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fltq_h.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fltq_h.rs2, ss, ctx); + break; + case RISCV_FLEQ_S: + SStream_concat(ss, "fleq.s"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_fleq_s.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fleq_s.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fleq_s.rs2, ss, ctx); + break; + case RISCV_FLTQ_S: + SStream_concat(ss, "fltq.s"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_fltq_s.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fltq_s.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fltq_s.rs2, ss, ctx); + break; + case RISCV_FLEQ_D: + SStream_concat(ss, "fleq.d"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_fleq_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fleq_d.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fleq_d.rs2, ss, ctx); + break; + case RISCV_FLTQ_D: + SStream_concat(ss, "fltq.d"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_fltq_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fltq_d.rs1, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fltq_d.rs2, ss, ctx); + break; + case RISCV_FCVTMOD_W_D: + SStream_concat(ss, "fcvtmod.w.d"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_fcvtmod_w_d.rd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.riscv_fcvtmod_w_d.rs1, ss, ctx); + break; + case RISCV_SHA256SIG0: + SStream_concat(ss, "sha256sig0"); + spc(ss, ctx); + reg_name(tree->ast_node.sha256sig0.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha256sig0.rs1, ss, ctx); + break; + case RISCV_SHA256SIG1: + SStream_concat(ss, "sha256sig1"); + spc(ss, ctx); + reg_name(tree->ast_node.sha256sig1.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha256sig1.rs1, ss, ctx); + break; + case RISCV_SHA256SUM0: + SStream_concat(ss, "sha256sum0"); + spc(ss, ctx); + reg_name(tree->ast_node.sha256sum0.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha256sum0.rs1, ss, ctx); + break; + case RISCV_SHA256SUM1: + SStream_concat(ss, "sha256sum1"); + spc(ss, ctx); + reg_name(tree->ast_node.sha256sum1.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha256sum1.rs1, ss, ctx); + break; + case RISCV_AES32ESMI: + SStream_concat(ss, "aes32esmi"); + spc(ss, ctx); + reg_name(tree->ast_node.aes32esmi.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes32esmi.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes32esmi.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.aes32esmi.bs, ss, ctx); + break; + case RISCV_AES32ESI: + SStream_concat(ss, "aes32esi"); + spc(ss, ctx); + reg_name(tree->ast_node.aes32esi.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes32esi.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes32esi.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.aes32esi.bs, ss, ctx); + break; + case RISCV_AES32DSMI: + SStream_concat(ss, "aes32dsmi"); + spc(ss, ctx); + reg_name(tree->ast_node.aes32dsmi.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes32dsmi.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes32dsmi.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.aes32dsmi.bs, ss, ctx); + break; + case RISCV_AES32DSI: + SStream_concat(ss, "aes32dsi"); + spc(ss, ctx); + reg_name(tree->ast_node.aes32dsi.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes32dsi.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes32dsi.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.aes32dsi.bs, ss, ctx); + break; + case RISCV_SHA512SIG0L: + SStream_concat(ss, "sha512sig0l"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sig0l.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig0l.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig0l.rs2, ss, ctx); + break; + case RISCV_SHA512SIG0H: + SStream_concat(ss, "sha512sig0h"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sig0h.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig0h.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig0h.rs2, ss, ctx); + break; + case RISCV_SHA512SIG1L: + SStream_concat(ss, "sha512sig1l"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sig1l.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig1l.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig1l.rs2, ss, ctx); + break; + case RISCV_SHA512SIG1H: + SStream_concat(ss, "sha512sig1h"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sig1h.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig1h.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig1h.rs2, ss, ctx); + break; + case RISCV_SHA512SUM0R: + SStream_concat(ss, "sha512sum0r"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sum0r.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sum0r.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sum0r.rs2, ss, ctx); + break; + case RISCV_SHA512SUM1R: + SStream_concat(ss, "sha512sum1r"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sum1r.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sum1r.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sum1r.rs2, ss, ctx); + break; + case RISCV_AES64KS1I: + SStream_concat(ss, "aes64ks1i"); + spc(ss, ctx); + reg_name(tree->ast_node.aes64ks1i.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64ks1i.rs1, ss, ctx); + sep(ss, ctx); + hex_bits_4(tree->ast_node.aes64ks1i.rnum, ss, ctx); + break; + case RISCV_AES64KS2: + SStream_concat(ss, "aes64ks2"); + spc(ss, ctx); + reg_name(tree->ast_node.aes64ks2.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64ks2.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64ks2.rs2, ss, ctx); + break; + case RISCV_AES64IM: + SStream_concat(ss, "aes64im"); + spc(ss, ctx); + reg_name(tree->ast_node.aes64im.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64im.rs1, ss, ctx); + break; + case RISCV_AES64ESM: + SStream_concat(ss, "aes64esm"); + spc(ss, ctx); + reg_name(tree->ast_node.aes64esm.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64esm.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64esm.rs2, ss, ctx); + break; + case RISCV_AES64ES: + SStream_concat(ss, "aes64es"); + spc(ss, ctx); + reg_name(tree->ast_node.aes64es.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64es.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64es.rs2, ss, ctx); + break; + case RISCV_AES64DSM: + SStream_concat(ss, "aes64dsm"); + spc(ss, ctx); + reg_name(tree->ast_node.aes64dsm.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64dsm.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64dsm.rs2, ss, ctx); + break; + case RISCV_AES64DS: + SStream_concat(ss, "aes64ds"); + spc(ss, ctx); + reg_name(tree->ast_node.aes64ds.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64ds.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.aes64ds.rs2, ss, ctx); + break; + case RISCV_SHA512SIG0: + SStream_concat(ss, "sha512sig0"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sig0.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig0.rs1, ss, ctx); + break; + case RISCV_SHA512SIG1: + SStream_concat(ss, "sha512sig1"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sig1.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sig1.rs1, ss, ctx); + break; + case RISCV_SHA512SUM0: + SStream_concat(ss, "sha512sum0"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sum0.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sum0.rs1, ss, ctx); + break; + case RISCV_SHA512SUM1: + SStream_concat(ss, "sha512sum1"); + spc(ss, ctx); + reg_name(tree->ast_node.sha512sum1.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sha512sum1.rs1, ss, ctx); + break; + case RISCV_SM3P0: + SStream_concat(ss, "sm3p0"); + spc(ss, ctx); + reg_name(tree->ast_node.sm3p0.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sm3p0.rs1, ss, ctx); + break; + case RISCV_SM3P1: + SStream_concat(ss, "sm3p1"); + spc(ss, ctx); + reg_name(tree->ast_node.sm3p1.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sm3p1.rs1, ss, ctx); + break; + case RISCV_SM4ED: + SStream_concat(ss, "sm4ed"); + spc(ss, ctx); + reg_name(tree->ast_node.sm4ed.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sm4ed.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sm4ed.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.sm4ed.bs, ss, ctx); + break; + case RISCV_SM4KS: + SStream_concat(ss, "sm4ks"); + spc(ss, ctx); + reg_name(tree->ast_node.sm4ks.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sm4ks.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.sm4ks.rs2, ss, ctx); + sep(ss, ctx); + hex_bits_2(tree->ast_node.sm4ks.bs, ss, ctx); + break; + case RISCV_ZBKB_RTYPE: + zbkb_rtype_mnemonic(tree->ast_node.zbkb_rtype.op, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zbkb_rtype.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbkb_rtype.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbkb_rtype.rs2, ss, ctx); + break; + case RISCV_ZBKB_PACKW: + SStream_concat(ss, "packw"); + spc(ss, ctx); + reg_name(tree->ast_node.zbkb_packw.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbkb_packw.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zbkb_packw.rs2, ss, ctx); + break; + case RISCV_ZIP: + SStream_concat(ss, "zip"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_zip.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_zip.rs1, ss, ctx); + break; + case RISCV_UNZIP: + SStream_concat(ss, "unzip"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_unzip.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_unzip.rs1, ss, ctx); + break; + case RISCV_BREV8: + SStream_concat(ss, "brev8"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_brev8.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_brev8.rs1, ss, ctx); + break; + case RISCV_XPERM8: + SStream_concat(ss, "xperm8"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_xperm8.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_xperm8.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_xperm8.rs2, ss, ctx); + break; + case RISCV_XPERM4: + SStream_concat(ss, "xperm4"); + spc(ss, ctx); + reg_name(tree->ast_node.riscv_xperm4.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_xperm4.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.riscv_xperm4.rs2, ss, ctx); + break; + case RISCV_ZICOND_RTYPE: + zicond_mnemonic(tree->ast_node.zicond_rtype.riscv_czero_nez, ss); + spc(ss, ctx); + reg_name(tree->ast_node.zicond_rtype.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zicond_rtype.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zicond_rtype.rs2, ss, ctx); + break; + case RISCV_VSETVLI: + SStream_concat(ss, "vsetvli"); + spc(ss, ctx); + reg_name(tree->ast_node.vsetvli.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vsetvli.rs1, ss, ctx); + sep(ss, ctx); + sew_flag(tree->ast_node.vsetvli.sew, ss); + maybe_lmul_flag(tree->ast_node.vsetvli.lmul, ss, ctx); + ta_flag(tree->ast_node.vsetvli.ta, ss, ctx); + ma_flag(tree->ast_node.vsetvli.ma, ss, ctx); + break; + case RISCV_VSETVL: + SStream_concat(ss, "vsetvl"); + spc(ss, ctx); + reg_name(tree->ast_node.vsetvl.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vsetvl.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vsetvl.rs2, ss, ctx); + break; + case RISCV_VSETIVLI: + SStream_concat(ss, "vsetivli"); + spc(ss, ctx); + reg_name(tree->ast_node.vsetivli.rd, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.vsetivli.uimm, ss, ctx); + sep(ss, ctx); + sew_flag(tree->ast_node.vsetivli.sew, ss); + maybe_lmul_flag(tree->ast_node.vsetivli.lmul, ss, ctx); + ta_flag(tree->ast_node.vsetivli.ta, ss, ctx); + ma_flag(tree->ast_node.vsetivli.ma, ss, ctx); + break; + case RISCV_VVTYPE: + vvtype_mnemonic(tree->ast_node.vvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.vvtype.vm, ss, ctx); + break; + case RISCV_NVSTYPE: + nvstype_mnemonic(tree->ast_node.nvstype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.nvstype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.nvstype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.nvstype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.nvstype.vm, ss, ctx); + break; + case RISCV_NVTYPE: + nvtype_mnemonic(tree->ast_node.nvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.nvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.nvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.nvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.nvtype.vm, ss, ctx); + break; + case RISCV_MASKTYPEV: + SStream_concat(ss, "vmerge.vvm"); + spc(ss, ctx); + vreg_name(tree->ast_node.masktypev.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.masktypev.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.masktypev.vs1, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_MOVETYPEV: + SStream_concat(ss, "vmv.v.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.movetypev.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.movetypev.vs1, ss, ctx); + break; + case RISCV_VXTYPE: + vxtype_mnemonic(tree->ast_node.vxtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vxtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vxtype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vxtype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.vxtype.vm, ss, ctx); + break; + case RISCV_NXSTYPE: + nxstype_mnemonic(tree->ast_node.nxstype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.nxstype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.nxstype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.nxstype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.nxstype.vm, ss, ctx); + break; + case RISCV_NXTYPE: + nxtype_mnemonic(tree->ast_node.nxtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.nxtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.nxtype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.nxtype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.nxtype.vm, ss, ctx); + break; + case RISCV_VXSG: + vxsg_mnemonic(tree->ast_node.vxsg.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vxsg.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vxsg.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vxsg.rs1, ss, ctx); + maybe_vmask(tree->ast_node.vxsg.vm, ss, ctx); + break; + case RISCV_MASKTYPEX: + SStream_concat(ss, "vmerge.vxm"); + spc(ss, ctx); + vreg_name(tree->ast_node.masktypex.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.masktypex.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.masktypex.rs1, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_MOVETYPEX: + SStream_concat(ss, "vmv.v.x"); + spc(ss, ctx); + vreg_name(tree->ast_node.movetypex.vd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.movetypex.rs1, ss, ctx); + break; + case RISCV_VITYPE: + vitype_mnemonic(tree->ast_node.vitype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vitype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vitype.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.vitype.simm, ss, ctx); + maybe_vmask(tree->ast_node.vitype.vm, ss, ctx); + break; + case RISCV_NISTYPE: + nistype_mnemonic(tree->ast_node.nistype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.nistype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.nistype.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.nistype.simm, ss, ctx); + maybe_vmask(tree->ast_node.nistype.vm, ss, ctx); + break; + case RISCV_NITYPE: + nitype_mnemonic(tree->ast_node.nitype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.nitype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.nitype.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.nitype.simm, ss, ctx); + maybe_vmask(tree->ast_node.nitype.vm, ss, ctx); + break; + case RISCV_VISG: + visg_mnemonic(tree->ast_node.visg.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.visg.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.visg.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.visg.simm, ss, ctx); + maybe_vmask(tree->ast_node.visg.vm, ss, ctx); + break; + case RISCV_MASKTYPEI: + SStream_concat(ss, "vmerge.vim"); + spc(ss, ctx); + vreg_name(tree->ast_node.masktypei.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.masktypei.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.masktypei.simm, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_MOVETYPEI: + SStream_concat(ss, "vmv.v.i"); + spc(ss, ctx); + vreg_name(tree->ast_node.movetypei.vd, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.movetypei.simm, ss, ctx); + break; + case RISCV_VMVRTYPE: + SStream_concat(ss, "vmv"); + simm_string(tree->ast_node.vmvrtype.simm, ss); + SStream_concat(ss, "r.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vmvrtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vmvrtype.vs2, ss, ctx); + break; + case RISCV_MVVTYPE: + mvvtype_mnemonic(tree->ast_node.mvvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.mvvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mvvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mvvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.mvvtype.vm, ss, ctx); + break; + case RISCV_MVVMATYPE: + mvvmatype_mnemonic(tree->ast_node.mvvmatype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.mvvmatype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mvvmatype.vs1, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mvvmatype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.mvvmatype.vm, ss, ctx); + break; + case RISCV_WVVTYPE: + wvvtype_mnemonic(tree->ast_node.wvvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.wvvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wvvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wvvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.wvvtype.vm, ss, ctx); + break; + case RISCV_WVTYPE: + wvtype_mnemonic(tree->ast_node.wvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.wvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.wvtype.vm, ss, ctx); + break; + case RISCV_WMVVTYPE: + wmvvtype_mnemonic(tree->ast_node.wmvvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.wmvvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wmvvtype.vs1, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wmvvtype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.wmvvtype.vm, ss, ctx); + break; + case RISCV_VEXT2TYPE: + vext2type_mnemonic(tree->ast_node.vext2type.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vext2type.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vext2type.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vext2type.vm, ss, ctx); + break; + case RISCV_VEXT4TYPE: + vext4type_mnemonic(tree->ast_node.vext4type.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vext4type.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vext4type.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vext4type.vm, ss, ctx); + break; + case RISCV_VEXT8TYPE: + vext8type_mnemonic(tree->ast_node.vext8type.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vext8type.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vext8type.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vext8type.vm, ss, ctx); + break; + case RISCV_VMVXS: + SStream_concat(ss, "vmv.x.s"); + spc(ss, ctx); + reg_name(tree->ast_node.vmvxs.rd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vmvxs.vs2, ss, ctx); + break; + case RISCV_MVVCOMPRESS: + SStream_concat(ss, "vcompress.vm"); + spc(ss, ctx); + vreg_name(tree->ast_node.mvvcompress.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mvvcompress.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mvvcompress.vs1, ss, ctx); + break; + case RISCV_MVXTYPE: + mvxtype_mnemonic(tree->ast_node.mvxtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.mvxtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mvxtype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.mvxtype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.mvxtype.vm, ss, ctx); + break; + case RISCV_MVXMATYPE: + mvxmatype_mnemonic(tree->ast_node.mvxmatype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.mvxmatype.vd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.mvxmatype.rs1, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mvxmatype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.mvxmatype.vm, ss, ctx); + break; + case RISCV_WVXTYPE: + wvxtype_mnemonic(tree->ast_node.wvxtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.wvxtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wvxtype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.wvxtype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.wvxtype.vm, ss, ctx); + break; + case RISCV_WXTYPE: + wxtype_mnemonic(tree->ast_node.wxtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.wxtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wxtype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.wxtype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.wxtype.vm, ss, ctx); + break; + case RISCV_WMVXTYPE: + wmvxtype_mnemonic(tree->ast_node.wmvxtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.wmvxtype.vd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.wmvxtype.rs1, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.wmvxtype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.wmvxtype.vm, ss, ctx); + break; + case RISCV_VMVSX: + SStream_concat(ss, "vmv.s.x"); + spc(ss, ctx); + vreg_name(tree->ast_node.vmvsx.vd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vmvsx.rs1, ss, ctx); + break; + case RISCV_FVVTYPE: + fvvtype_mnemonic(tree->ast_node.fvvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fvvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.fvvtype.vm, ss, ctx); + break; + case RISCV_FVVMATYPE: + fvvmatype_mnemonic(tree->ast_node.fvvmatype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fvvmatype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvvmatype.vs1, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvvmatype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.fvvmatype.vm, ss, ctx); + break; + case RISCV_FWVVTYPE: + fwvvtype_mnemonic(tree->ast_node.fwvvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fwvvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwvvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwvvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.fwvvtype.vm, ss, ctx); + break; + case RISCV_FWVVMATYPE: + fwvvmatype_mnemonic(tree->ast_node.fwvvmatype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fwvvmatype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwvvmatype.vs1, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwvvmatype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.fwvvmatype.vm, ss, ctx); + break; + case RISCV_FWVTYPE: + fwvtype_mnemonic(tree->ast_node.fwvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fwvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.fwvtype.vm, ss, ctx); + break; + case RISCV_VFUNARY0: + vfunary0_mnemonic(tree->ast_node.vfunary0.vfunary0, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vfunary0.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vfunary0.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vfunary0.vm, ss, ctx); + break; + case RISCV_VFWUNARY0: + vfwunary0_mnemonic(tree->ast_node.vfwunary0.vfwunary0, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vfwunary0.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vfwunary0.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vfwunary0.vm, ss, ctx); + break; + case RISCV_VFNUNARY0: + vfnunary0_mnemonic(tree->ast_node.vfnunary0.vfnunary0, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vfnunary0.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vfnunary0.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vfnunary0.vm, ss, ctx); + break; + case RISCV_VFUNARY1: + vfunary1_mnemonic(tree->ast_node.vfunary1.vfunary1, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vfunary1.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vfunary1.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vfunary1.vm, ss, ctx); + break; + case RISCV_VFMVFS: + SStream_concat(ss, "vfmv.f.s"); + spc(ss, ctx); + freg_name(tree->ast_node.vfmvfs.rd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vfmvfs.vs2, ss, ctx); + break; + case RISCV_FVFTYPE: + fvftype_mnemonic(tree->ast_node.fvftype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fvftype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvftype.vs2, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.fvftype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.fvftype.vm, ss, ctx); + break; + case RISCV_FVFMATYPE: + fvfmatype_mnemonic(tree->ast_node.fvfmatype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fvfmatype.vd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.fvfmatype.rs1, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvfmatype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.fvfmatype.vm, ss, ctx); + break; + case RISCV_FWVFTYPE: + fwvftype_mnemonic(tree->ast_node.fwvftype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fwvftype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwvftype.vs2, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.fwvftype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.fwvftype.vm, ss, ctx); + break; + case RISCV_FWVFMATYPE: + fwvfmatype_mnemonic(tree->ast_node.fwvfmatype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fwvfmatype.vd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.fwvfmatype.rs1, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwvfmatype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.fwvfmatype.vm, ss, ctx); + break; + case RISCV_FWFTYPE: + fwftype_mnemonic(tree->ast_node.fwftype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fwftype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fwftype.vs2, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.fwftype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.fwftype.vm, ss, ctx); + break; + case RISCV_VFMERGE: + SStream_concat(ss, "vfmerge.vfm"); + spc(ss, ctx); + vreg_name(tree->ast_node.vfmerge.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vfmerge.vs2, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.vfmerge.rs1, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_VFMV: + SStream_concat(ss, "vfmv.v.f"); + spc(ss, ctx); + vreg_name(tree->ast_node.vfmv.vd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.vfmv.rs1, ss, ctx); + break; + case RISCV_VFMVSF: + SStream_concat(ss, "vfmv.s.f"); + spc(ss, ctx); + vreg_name(tree->ast_node.vfmvsf.vd, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.vfmvsf.rs1, ss, ctx); + break; + case RISCV_VLSEGTYPE: + SStream_concat(ss, "vl"); + nfields_string(tree->ast_node.vlsegtype.nf, ss); + SStream_concat(ss, "e"); + vlewidth_bitsnumberstr(tree->ast_node.vlsegtype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vlsegtype.vd, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vlsegtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + maybe_vmask(tree->ast_node.vlsegtype.vm, ss, ctx); + break; + case RISCV_VLSEGFFTYPE: + SStream_concat(ss, "vl"); + nfields_string(tree->ast_node.vlsegfftype.nf, ss); + SStream_concat(ss, "e"); + vlewidth_bitsnumberstr(tree->ast_node.vlsegfftype.width, ss); + SStream_concat(ss, "ff.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vlsegfftype.vd, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vlsegfftype.rs1, ss, ctx); + SStream_concat(ss, ")"); + maybe_vmask(tree->ast_node.vlsegfftype.vm, ss, ctx); + break; + case RISCV_VSSEGTYPE: + SStream_concat(ss, "vs"); + nfields_string(tree->ast_node.vssegtype.nf, ss); + SStream_concat(ss, "e"); + vlewidth_bitsnumberstr(tree->ast_node.vssegtype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vssegtype.vs3, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vssegtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + maybe_vmask(tree->ast_node.vssegtype.vm, ss, ctx); + break; + case RISCV_VLSSEGTYPE: + SStream_concat(ss, "vls"); + nfields_string(tree->ast_node.vlssegtype.nf, ss); + SStream_concat(ss, "e"); + vlewidth_bitsnumberstr(tree->ast_node.vlssegtype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vlssegtype.vd, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vlssegtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + sep(ss, ctx); + reg_name(tree->ast_node.vlssegtype.rs2, ss, ctx); + maybe_vmask(tree->ast_node.vlssegtype.vm, ss, ctx); + break; + case RISCV_VSSSEGTYPE: + SStream_concat(ss, "vss"); + nfields_string(tree->ast_node.vsssegtype.nf, ss); + SStream_concat(ss, "e"); + vlewidth_bitsnumberstr(tree->ast_node.vsssegtype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vsssegtype.vs3, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vsssegtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + sep(ss, ctx); + reg_name(tree->ast_node.vsssegtype.rs2, ss, ctx); + maybe_vmask(tree->ast_node.vsssegtype.vm, ss, ctx); + break; + case RISCV_VLUXSEGTYPE: + SStream_concat(ss, "vlux"); + nfields_string(tree->ast_node.vluxsegtype.nf, ss); + SStream_concat(ss, "ei"); + vlewidth_bitsnumberstr(tree->ast_node.vluxsegtype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vluxsegtype.vd, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vluxsegtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + sep(ss, ctx); + vreg_name(tree->ast_node.vluxsegtype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vluxsegtype.vm, ss, ctx); + break; + case RISCV_VLOXSEGTYPE: + SStream_concat(ss, "vlox"); + nfields_string(tree->ast_node.vloxsegtype.nf, ss); + SStream_concat(ss, "ei"); + vlewidth_bitsnumberstr(tree->ast_node.vloxsegtype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vloxsegtype.vd, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vloxsegtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + sep(ss, ctx); + vreg_name(tree->ast_node.vloxsegtype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vloxsegtype.vm, ss, ctx); + break; + case RISCV_VSUXSEGTYPE: + SStream_concat(ss, "vsux"); + nfields_string(tree->ast_node.vsuxsegtype.nf, ss); + SStream_concat(ss, "ei"); + vlewidth_bitsnumberstr(tree->ast_node.vsuxsegtype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vsuxsegtype.vs3, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vsuxsegtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + sep(ss, ctx); + vreg_name(tree->ast_node.vsuxsegtype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vsuxsegtype.vm, ss, ctx); + break; + case RISCV_VSOXSEGTYPE: + SStream_concat(ss, "vsox"); + nfields_string(tree->ast_node.vsoxsegtype.nf, ss); + SStream_concat(ss, "ei"); + vlewidth_bitsnumberstr(tree->ast_node.vsoxsegtype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vsoxsegtype.vs3, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vsoxsegtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + sep(ss, ctx); + vreg_name(tree->ast_node.vsoxsegtype.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vsoxsegtype.vm, ss, ctx); + break; + case RISCV_VLRETYPE: + SStream_concat(ss, "vl"); + nfields_string(tree->ast_node.vlretype.nf, ss); + SStream_concat(ss, "re"); + vlewidth_bitsnumberstr(tree->ast_node.vlretype.width, ss); + SStream_concat(ss, ".v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vlretype.vd, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vlretype.rs1, ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_VSRETYPE: + SStream_concat(ss, "vs"); + nfields_string(tree->ast_node.vsretype.nf, ss); + SStream_concat(ss, "r.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vsretype.vs3, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vsretype.rs1, ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_VMTYPE: + vmtype_mnemonic(tree->ast_node.vmtype.op, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vmtype.vd_or_vs3, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "("); + reg_name(tree->ast_node.vmtype.rs1, ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_MMTYPE: + mmtype_mnemonic(tree->ast_node.mmtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.mmtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mmtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.mmtype.vs1, ss, ctx); + break; + case RISCV_VCPOP_M: + SStream_concat(ss, "vpopc.m"); + spc(ss, ctx); + reg_name(tree->ast_node.vcpop_m.rd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vcpop_m.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vcpop_m.vm, ss, ctx); + break; + case RISCV_VFIRST_M: + SStream_concat(ss, "vfirst.m"); + spc(ss, ctx); + reg_name(tree->ast_node.vfirst_m.rd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vfirst_m.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vfirst_m.vm, ss, ctx); + break; + case RISCV_VMSBF_M: + SStream_concat(ss, "vmsbf.m"); + spc(ss, ctx); + vreg_name(tree->ast_node.vmsbf_m.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vmsbf_m.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vmsbf_m.vm, ss, ctx); + break; + case RISCV_VMSIF_M: + SStream_concat(ss, "vmsif.m"); + spc(ss, ctx); + vreg_name(tree->ast_node.vmsif_m.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vmsif_m.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vmsif_m.vm, ss, ctx); + break; + case RISCV_VMSOF_M: + SStream_concat(ss, "vmsof.m"); + spc(ss, ctx); + vreg_name(tree->ast_node.vmsof_m.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vmsof_m.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vmsof_m.vm, ss, ctx); + break; + case RISCV_VIOTA_M: + SStream_concat(ss, "viota.m"); + spc(ss, ctx); + vreg_name(tree->ast_node.viota_m.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.viota_m.vs2, ss, ctx); + maybe_vmask(tree->ast_node.viota_m.vm, ss, ctx); + break; + case RISCV_VID_V: + SStream_concat(ss, "vid.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vid_v.vd, ss, ctx); + maybe_vmask(tree->ast_node.vid_v.vm, ss, ctx); + break; + case RISCV_VVMTYPE: + vvmtype_mnemonic(tree->ast_node.vvmtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vvmtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvmtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvmtype.vs1, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_VVMCTYPE: + vvmctype_mnemonic(tree->ast_node.vvmctype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vvmctype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvmctype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvmctype.vs1, ss, ctx); + break; + case RISCV_VVMSTYPE: + vvmstype_mnemonic(tree->ast_node.vvmstype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vvmstype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvmstype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvmstype.vs1, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_VVCMPTYPE: + vvcmptype_mnemonic(tree->ast_node.vvcmptype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vvcmptype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvcmptype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vvcmptype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.vvcmptype.vm, ss, ctx); + break; + case RISCV_VXMTYPE: + vxmtype_mnemonic(tree->ast_node.vxmtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vxmtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vxmtype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vxmtype.rs1, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_VXMCTYPE: + vxmctype_mnemonic(tree->ast_node.vxmctype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vxmctype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vxmctype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vxmctype.rs1, ss, ctx); + break; + case RISCV_VXMSTYPE: + vxmstype_mnemonic(tree->ast_node.vxmstype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vxmstype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vxmstype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vxmstype.rs1, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_VXCMPTYPE: + vxcmptype_mnemonic(tree->ast_node.vxcmptype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vxcmptype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vxcmptype.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vxcmptype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.vxcmptype.vm, ss, ctx); + break; + case RISCV_VIMTYPE: + vimtype_mnemonic(tree->ast_node.vimtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vimtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vimtype.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.vimtype.simm, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_VIMCTYPE: + vimctype_mnemonic(tree->ast_node.vimctype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vimctype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vimctype.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.vimctype.simm, ss, ctx); + break; + case RISCV_VIMSTYPE: + vimstype_mnemonic(tree->ast_node.vimstype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vimstype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vimstype.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.vimstype.simm, ss, ctx); + sep(ss, ctx); + SStream_concat(ss, "v0"); + break; + case RISCV_VICMPTYPE: + vicmptype_mnemonic(tree->ast_node.vicmptype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.vicmptype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vicmptype.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.vicmptype.simm, ss, ctx); + maybe_vmask(tree->ast_node.vicmptype.vm, ss, ctx); + break; + case RISCV_FVVMTYPE: + fvvmtype_mnemonic(tree->ast_node.fvvmtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fvvmtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvvmtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvvmtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.fvvmtype.vm, ss, ctx); + break; + case RISCV_FVFMTYPE: + fvfmtype_mnemonic(tree->ast_node.fvfmtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.fvfmtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.fvfmtype.vs2, ss, ctx); + sep(ss, ctx); + freg_name(tree->ast_node.fvfmtype.rs1, ss, ctx); + maybe_vmask(tree->ast_node.fvfmtype.vm, ss, ctx); + break; + case RISCV_RIVVTYPE: + rivvtype_mnemonic(tree->ast_node.rivvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.rivvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.rivvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.rivvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.rivvtype.vm, ss, ctx); + break; + case RISCV_RMVVTYPE: + rmvvtype_mnemonic(tree->ast_node.rmvvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.rmvvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.rmvvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.rmvvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.rmvvtype.vm, ss, ctx); + break; + case RISCV_RFVVTYPE: + rfvvtype_mnemonic(tree->ast_node.rfvvtype.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.rfvvtype.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.rfvvtype.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.rfvvtype.vs1, ss, ctx); + maybe_vmask(tree->ast_node.rfvvtype.vm, ss, ctx); + break; + case RISCV_ZICBOM: + cbop_mnemonic(tree->ast_node.riscv_zicbom.cbo_inval, ss); + spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + reg_name(tree->ast_node.riscv_zicbom.rs1, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_ZICBOZ: + SStream_concat(ss, "cbo.zero"); + spc(ss, ctx); + SStream_concat(ss, "("); + opt_spc(ss, ctx); + reg_name(tree->ast_node.riscv_zicboz, ss, ctx); + opt_spc(ss, ctx); + SStream_concat(ss, ")"); + break; + case RISCV_VANDN_VV: + SStream_concat(ss, "vandn.vv"); + spc(ss, ctx); + vreg_name(tree->ast_node.vandn_vv.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vandn_vv.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vandn_vv.vs1, ss, ctx); + maybe_vmask(tree->ast_node.vandn_vv.vm, ss, ctx); + break; + case RISCV_VANDN_VX: + SStream_concat(ss, "vandn.vx"); + spc(ss, ctx); + vreg_name(tree->ast_node.vandn_vx.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vandn_vx.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vandn_vx.rs1, ss, ctx); + maybe_vmask(tree->ast_node.vandn_vx.vm, ss, ctx); + break; + case RISCV_VBREV_V: + SStream_concat(ss, "vbrev.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vbrev_v.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vbrev_v.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vbrev_v.vm, ss, ctx); + break; + case RISCV_VBREV8_V: + SStream_concat(ss, "vbrev8.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vbrev8_v.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vbrev8_v.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vbrev8_v.vm, ss, ctx); + break; + case RISCV_VREV8_V: + SStream_concat(ss, "vrev8.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vrev8_v.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vrev8_v.vs2, ss, ctx); + maybe_vmask(tree->ast_node.vrev8_v.vm, ss, ctx); + break; + case RISCV_VCLZ_V: + SStream_concat(ss, "vclz.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vclz_v.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vclz_v.vs2, ss, ctx); + sep(ss, ctx); + maybe_vmask(tree->ast_node.vclz_v.vm, ss, ctx); + break; + case RISCV_VCTZ_V: + SStream_concat(ss, "vctz.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vctz_v.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vctz_v.vs2, ss, ctx); + sep(ss, ctx); + maybe_vmask(tree->ast_node.vctz_v.vm, ss, ctx); + break; + case RISCV_VCPOP_V: + SStream_concat(ss, "vcpop.v"); + spc(ss, ctx); + vreg_name(tree->ast_node.vcpop_v.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vcpop_v.vs2, ss, ctx); + sep(ss, ctx); + maybe_vmask(tree->ast_node.vcpop_v.vm, ss, ctx); + break; + case RISCV_VROL_VV: + SStream_concat(ss, "vrol.vv"); + spc(ss, ctx); + vreg_name(tree->ast_node.vrol_vv.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vrol_vv.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vrol_vv.vs1, ss, ctx); + maybe_vmask(tree->ast_node.vrol_vv.vm, ss, ctx); + break; + case RISCV_VROL_VX: + SStream_concat(ss, "vrol.vx"); + spc(ss, ctx); + vreg_name(tree->ast_node.vrol_vx.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vrol_vx.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vrol_vx.rs1, ss, ctx); + maybe_vmask(tree->ast_node.vrol_vx.vm, ss, ctx); + break; + case RISCV_VROR_VV: + SStream_concat(ss, "vror.vv"); + spc(ss, ctx); + vreg_name(tree->ast_node.vror_vv.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vror_vv.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vror_vv.vs1, ss, ctx); + maybe_vmask(tree->ast_node.vror_vv.vm, ss, ctx); + break; + case RISCV_VROR_VX: + SStream_concat(ss, "vror.vx"); + spc(ss, ctx); + vreg_name(tree->ast_node.vror_vx.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vror_vx.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vror_vx.rs1, ss, ctx); + maybe_vmask(tree->ast_node.vror_vx.vm, ss, ctx); + break; + case RISCV_VROR_VI: + SStream_concat(ss, "vror.vi"); + spc(ss, ctx); + vreg_name(tree->ast_node.vror_vi.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vror_vi.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.vror_vi.uimm, ss, ctx); + maybe_vmask(tree->ast_node.vror_vi.vm, ss, ctx); + break; + case RISCV_VWSLL_VV: + SStream_concat(ss, "vwsll.vv"); + spc(ss, ctx); + vreg_name(tree->ast_node.vwsll_vv.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vwsll_vv.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vwsll_vv.vs1, ss, ctx); + sep(ss, ctx); + maybe_vmask(tree->ast_node.vwsll_vv.vm, ss, ctx); + break; + case RISCV_VWSLL_VX: + SStream_concat(ss, "vwsll.vx"); + spc(ss, ctx); + vreg_name(tree->ast_node.vwsll_vx.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vwsll_vx.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vwsll_vx.rs1, ss, ctx); + sep(ss, ctx); + maybe_vmask(tree->ast_node.vwsll_vx.vm, ss, ctx); + break; + case RISCV_VWSLL_VI: + SStream_concat(ss, "vwsll.vi"); + spc(ss, ctx); + vreg_name(tree->ast_node.vwsll_vi.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vwsll_vi.vs2, ss, ctx); + sep(ss, ctx); + hex_bits_5(tree->ast_node.vwsll_vi.uimm, ss, ctx); + sep(ss, ctx); + maybe_vmask(tree->ast_node.vwsll_vi.vm, ss, ctx); + break; + case RISCV_VCLMUL_VV: + SStream_concat(ss, "vclmul.vv"); + spc(ss, ctx); + vreg_name(tree->ast_node.vclmul_vv.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vclmul_vv.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vclmul_vv.vs1, ss, ctx); + maybe_vmask(tree->ast_node.vclmul_vv.vm, ss, ctx); + break; + case RISCV_VCLMUL_VX: + SStream_concat(ss, "vclmul.vx"); + spc(ss, ctx); + vreg_name(tree->ast_node.vclmul_vx.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vclmul_vx.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vclmul_vx.rs1, ss, ctx); + maybe_vmask(tree->ast_node.vclmul_vx.vm, ss, ctx); + break; + case RISCV_VCLMULH_VV: + SStream_concat(ss, "vclmulh.vv"); + spc(ss, ctx); + vreg_name(tree->ast_node.vclmulh_vv.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vclmulh_vv.vs2, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vclmulh_vv.vs1, ss, ctx); + maybe_vmask(tree->ast_node.vclmulh_vv.vm, ss, ctx); + break; + case RISCV_VCLMULH_VX: + SStream_concat(ss, "vclmulh.vx"); + spc(ss, ctx); + vreg_name(tree->ast_node.vclmulh_vx.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vclmulh_vx.vs2, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.vclmulh_vx.rs1, ss, ctx); + maybe_vmask(tree->ast_node.vclmulh_vx.vm, ss, ctx); + break; + case RISCV_VSHA2MS_VV: + SStream_concat(ss, "vsha2ms.vv"); + spc(ss, ctx); + vreg_name(tree->ast_node.vsha2ms_vv.vd, ss, ctx); + sep(ss, ctx); + vreg_name(tree->ast_node.vsha2ms_vv.vs2, ss, ctx); + vreg_name(tree->ast_node.vsha2ms_vv.vs1, ss, ctx); + break; + case RISCV_ZVKSHA2TYPE: + vsha2c_mnemonic(tree->ast_node.zvksha2type.funct6, ss); + spc(ss, ctx); + vreg_name(tree->ast_node.zvksha2type.vd, ss, ctx); + spc(ss, ctx); + vreg_name(tree->ast_node.zvksha2type.vs2, ss, ctx); + spc(ss, ctx); + vreg_name(tree->ast_node.zvksha2type.vs1, ss, ctx); + break; + case RISCV_ZIMOP_MOP_R: + SStream_concat(ss, "mop.r."); + dec_bits_5(tree->ast_node.zimop_mop_r.mop, ss, ctx); + spc(ss, ctx); + reg_name(tree->ast_node.zimop_mop_r.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zimop_mop_r.rs1, ss, ctx); + break; + case RISCV_ZIMOP_MOP_RR: + SStream_concat(ss, "mop.rr."); + dec_bits_3(tree->ast_node.zimop_mop_rr.mop, ss, ctx); + spc(ss, ctx); + reg_name(tree->ast_node.zimop_mop_rr.rd, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zimop_mop_rr.rs1, ss, ctx); + sep(ss, ctx); + reg_name(tree->ast_node.zimop_mop_rr.rs2, ss, ctx); + break; + case RISCV_ZCMOP: + SStream_concat(ss, "c.mop."); + dec_bits_4(tree->ast_node.zcmop << 1 | 0x1 << 0, ss, ctx); + break; + case RISCV_STOP_FETCHING: + SStream_concat(ss, "stop_fetching"); + break; + case RISCV_THREAD_START: + SStream_concat(ss, "thread_start"); + break; + case RISCV_ILLEGAL: + SStream_concat(ss, "illegal"); + spc(ss, ctx); + hex_bits_32(tree->ast_node.illegal, ss, ctx); + break; + case RISCV_C_ILLEGAL: + SStream_concat(ss, "c.illegal"); + spc(ss, ctx); + hex_bits_16(tree->ast_node.c_illegal, ss, ctx); + break; + } +} +#endif diff --git a/arch/RISCV/RISCVAst2StrHelpers.h b/arch/RISCV/RISCVAst2StrHelpers.h new file mode 100644 index 0000000000..d2aac9df98 --- /dev/null +++ b/arch/RISCV/RISCVAst2StrHelpers.h @@ -0,0 +1,1428 @@ +#ifndef __AST2STR_HELPERS_H__ +#define __AST2STR_HELPERS_H__ + +#include +#include + +#include "../../SStream.h" +#include "../../cs_priv.h" +#include "RISCVDecodeHelpers.h" +#include "RISCVRVContextHelpers.h" + +#define spc(ss, c) SStream_concat1(ss, ' ') + +#define opt_spc spc + +#define sep(ss, c) SStream_concat(ss, " , ") + +static inline void hex_bits(uint64_t bitvec, uint8_t bvlen_bits, SStream *ss, + RVContext *ctx) { + char str[25] = {0}; + uint8_t str_len = bvlen_bits / 4; + // is not divisible by 4? + if ((bvlen_bits & 0x3) != 0) { + str_len++; + } + str_len += 2; // for the '0x' in the beginning + + CS_ASSERT(str_len < 24); + + for (uint8_t i = 0; i < bvlen_bits; i += 4) { + char digit = (bitvec & 0xF) + 48; + if (digit > '9') { + digit += ('a' - ':'); + } + + str[--str_len] = digit; + bitvec = bitvec >> 4; + } + str[0] = '0'; + str[1] = 'x'; + SStream_concat(ss, "%s", str); +} + +#define DEF_HEX_BITS(n) \ + static inline void hex_bits_##n(uint64_t bitvec, SStream *ss, \ + RVContext *ctx) { \ + hex_bits(bitvec, n, ss, ctx); \ + } + +DEF_HEX_BITS(1) +DEF_HEX_BITS(2) +DEF_HEX_BITS(3) +DEF_HEX_BITS(4) +DEF_HEX_BITS(5) +DEF_HEX_BITS(6) +DEF_HEX_BITS(7) +DEF_HEX_BITS(8) +DEF_HEX_BITS(9) +DEF_HEX_BITS(10) +DEF_HEX_BITS(11) +DEF_HEX_BITS(12) +DEF_HEX_BITS(13) +DEF_HEX_BITS(14) +DEF_HEX_BITS(15) +DEF_HEX_BITS(16) +DEF_HEX_BITS(17) +DEF_HEX_BITS(18) +DEF_HEX_BITS(19) +DEF_HEX_BITS(20) +DEF_HEX_BITS(21) +DEF_HEX_BITS(22) +DEF_HEX_BITS(23) +DEF_HEX_BITS(24) +DEF_HEX_BITS(25) +DEF_HEX_BITS(26) +DEF_HEX_BITS(27) +DEF_HEX_BITS(28) +DEF_HEX_BITS(29) +DEF_HEX_BITS(30) +DEF_HEX_BITS(31) +DEF_HEX_BITS(32) + +static inline void hex_bits_signed(uint64_t bitvec, uint8_t bvlen_bits, + SStream *ss, RVContext *ctx) { + // is not negative ? + if ((bitvec & (1 << (bvlen_bits - 1))) == 0) { + hex_bits(bitvec, bvlen_bits, ss, ctx); + } else { + SStream_concat1(ss, '-'); + hex_bits(bitvec, bvlen_bits, ss, ctx); + } +} + +#define DEF_HEX_BITS_SIGNED(n) \ + static inline void hex_bits_signed_##n(uint64_t bitvec, SStream *ss, \ + RVContext *ctx) { \ + hex_bits_signed(bitvec, n, ss, ctx); \ + } + +DEF_HEX_BITS_SIGNED(1); +DEF_HEX_BITS_SIGNED(2); +DEF_HEX_BITS_SIGNED(3); +DEF_HEX_BITS_SIGNED(4); +DEF_HEX_BITS_SIGNED(5); +DEF_HEX_BITS_SIGNED(6); +DEF_HEX_BITS_SIGNED(7); +DEF_HEX_BITS_SIGNED(8); +DEF_HEX_BITS_SIGNED(9); +DEF_HEX_BITS_SIGNED(10); +DEF_HEX_BITS_SIGNED(11); +DEF_HEX_BITS_SIGNED(12); +DEF_HEX_BITS_SIGNED(13); +DEF_HEX_BITS_SIGNED(14); +DEF_HEX_BITS_SIGNED(15); +DEF_HEX_BITS_SIGNED(16); +DEF_HEX_BITS_SIGNED(17); +DEF_HEX_BITS_SIGNED(18); +DEF_HEX_BITS_SIGNED(19); +DEF_HEX_BITS_SIGNED(20); +DEF_HEX_BITS_SIGNED(21); +DEF_HEX_BITS_SIGNED(22); +DEF_HEX_BITS_SIGNED(23); +DEF_HEX_BITS_SIGNED(24); +DEF_HEX_BITS_SIGNED(25); +DEF_HEX_BITS_SIGNED(26); +DEF_HEX_BITS_SIGNED(27); +DEF_HEX_BITS_SIGNED(28); +DEF_HEX_BITS_SIGNED(29); +DEF_HEX_BITS_SIGNED(30); +DEF_HEX_BITS_SIGNED(31); +DEF_HEX_BITS_SIGNED(32); + +const static char *reg_names[] = { + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", "a0", + "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", + "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"}; +static inline void reg_name(uint8_t r, SStream *ss, RVContext *ctx) { + CS_ASSERT(r < 32); + SStream_concat(ss, reg_names[r]); +} + +const static char *creg_names[] = {"s0", "s1", "a0", "a1", + "a2", "a3", "a4", "a5"}; +static inline void creg_name(uint8_t r, SStream *ss, RVContext *ctx) { + CS_ASSERT(r < 8); + SStream_concat(ss, creg_names[r]); +} + +const static char *freg_names[] = { + "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", + "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", + "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", + "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"}; +static inline void freg_name(uint8_t r, SStream *ss, RVContext *ctx) { + CS_ASSERT(r < 32); + SStream_concat(ss, freg_names[r]); +} + +const static char *vreg_names[] = { + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", + "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", + "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"}; +static inline void vreg_name(uint8_t r, SStream *ss, RVContext *ctx) { + CS_ASSERT(r < 32); + SStream_concat(ss, vreg_names[r]); +} + +static inline void freg_or_reg_name(uint8_t r, SStream *ss, RVContext *ctx) { + if (HART_SUPPORTS(Ext_Zfinx)) { + reg_name(r, ss, ctx); + } else { + freg_name(r, ss, ctx); + } +} + +static inline void maybe_vmask(uint8_t vm, SStream *ss, RVContext *ctx) { + if (vm) { + return; + } + SStream_concat(ss, " , v0.t"); +} + +static inline void ta_flag(uint8_t ta, SStream *ss, RVContext *ctx) { + if (ta) { + SStream_concat(ss, "ta"); + } else { + SStream_concat(ss, "tu"); + } +} + +static inline void ma_flag(uint8_t ma, SStream *ss, RVContext *ctx) { + if (ma) { + SStream_concat(ss, "ma"); + } else { + SStream_concat(ss, "mu"); + } +} + +static inline void maybe_lmul_flag(uint8_t lmul, SStream *ss, RVContext *ctx) { + switch (lmul) { + case 0x0: + return; + + case 0x5: + SStream_concat(ss, " , mf8"); + return; + + case 0x6: + SStream_concat(ss, " , mf4"); + return; + + case 0x7: + SStream_concat(ss, " , mf2"); + return; + + case 0x1: + SStream_concat(ss, " , m2"); + return; + + case 0x2: + SStream_concat(ss, " , m4"); + return; + + case 0x3: + SStream_concat(ss, " , m8"); + return; + } +} + +static inline void csr_name_map(uint32_t csr, SStream *ss, RVContext *ctx) { + switch (csr) { + case 0x3a0: + SStream_concat(ss, "pmpcfg0"); + return; + + case 0x3a1: + SStream_concat(ss, "pmpcfg1"); + return; + + case 0x3a2: + SStream_concat(ss, "pmpcfg2"); + return; + + case 0x3a3: + SStream_concat(ss, "pmpcfg3"); + return; + + case 0x3a4: + SStream_concat(ss, "pmpcfg4"); + return; + + case 0x3a5: + SStream_concat(ss, "pmpcfg5"); + return; + + case 0x3a6: + SStream_concat(ss, "pmpcfg6"); + return; + + case 0x3a7: + SStream_concat(ss, "pmpcfg7"); + return; + + case 0x3a8: + SStream_concat(ss, "pmpcfg8"); + return; + + case 0x3a9: + SStream_concat(ss, "pmpcfg9"); + return; + + case 0x3aa: + SStream_concat(ss, "pmpcfg10"); + return; + + case 0x3ab: + SStream_concat(ss, "pmpcfg11"); + return; + + case 0x3ac: + SStream_concat(ss, "pmpcfg12"); + return; + + case 0x3ad: + SStream_concat(ss, "pmpcfg13"); + return; + + case 0x3ae: + SStream_concat(ss, "pmpcfg14"); + return; + + case 0x3af: + SStream_concat(ss, "pmpcfg15"); + return; + + case 0x3b0: + SStream_concat(ss, "pmpaddr0"); + return; + + case 0x3b1: + SStream_concat(ss, "pmpaddr1"); + return; + + case 0x3b2: + SStream_concat(ss, "pmpaddr2"); + return; + + case 0x3b3: + SStream_concat(ss, "pmpaddr3"); + return; + + case 0x3b4: + SStream_concat(ss, "pmpaddr4"); + return; + + case 0x3b5: + SStream_concat(ss, "pmpaddr5"); + return; + + case 0x3b6: + SStream_concat(ss, "pmpaddr6"); + return; + + case 0x3b7: + SStream_concat(ss, "pmpaddr7"); + return; + + case 0x3b8: + SStream_concat(ss, "pmpaddr8"); + return; + + case 0x3b9: + SStream_concat(ss, "pmpaddr9"); + return; + + case 0x3ba: + SStream_concat(ss, "pmpaddr10"); + return; + + case 0x3bb: + SStream_concat(ss, "pmpaddr11"); + return; + + case 0x3bc: + SStream_concat(ss, "pmpaddr12"); + return; + + case 0x3bd: + SStream_concat(ss, "pmpaddr13"); + return; + + case 0x3be: + SStream_concat(ss, "pmpaddr14"); + return; + + case 0x3bf: + SStream_concat(ss, "pmpaddr15"); + return; + + case 0x3c0: + SStream_concat(ss, "pmpaddr16"); + return; + + case 0x3c1: + SStream_concat(ss, "pmpaddr17"); + return; + + case 0x3c2: + SStream_concat(ss, "pmpaddr18"); + return; + + case 0x3c3: + SStream_concat(ss, "pmpaddr19"); + return; + + case 0x3c4: + SStream_concat(ss, "pmpaddr20"); + return; + + case 0x3c5: + SStream_concat(ss, "pmpaddr21"); + return; + + case 0x3c6: + SStream_concat(ss, "pmpaddr22"); + return; + + case 0x3c7: + SStream_concat(ss, "pmpaddr23"); + return; + + case 0x3c8: + SStream_concat(ss, "pmpaddr24"); + return; + + case 0x3c9: + SStream_concat(ss, "pmpaddr25"); + return; + + case 0x3ca: + SStream_concat(ss, "pmpaddr26"); + return; + + case 0x3cb: + SStream_concat(ss, "pmpaddr27"); + return; + + case 0x3cc: + SStream_concat(ss, "pmpaddr28"); + return; + + case 0x3cd: + SStream_concat(ss, "pmpaddr29"); + return; + + case 0x3ce: + SStream_concat(ss, "pmpaddr30"); + return; + + case 0x3cf: + SStream_concat(ss, "pmpaddr31"); + return; + + case 0x3d0: + SStream_concat(ss, "pmpaddr32"); + return; + + case 0x3d1: + SStream_concat(ss, "pmpaddr33"); + return; + + case 0x3d2: + SStream_concat(ss, "pmpaddr34"); + return; + + case 0x3d3: + SStream_concat(ss, "pmpaddr35"); + return; + + case 0x3d4: + SStream_concat(ss, "pmpaddr36"); + return; + + case 0x3d5: + SStream_concat(ss, "pmpaddr37"); + return; + + case 0x3d6: + SStream_concat(ss, "pmpaddr38"); + return; + + case 0x3d7: + SStream_concat(ss, "pmpaddr39"); + return; + + case 0x3d8: + SStream_concat(ss, "pmpaddr40"); + return; + + case 0x3d9: + SStream_concat(ss, "pmpaddr41"); + return; + + case 0x3da: + SStream_concat(ss, "pmpaddr42"); + return; + + case 0x3db: + SStream_concat(ss, "pmpaddr43"); + return; + + case 0x3dc: + SStream_concat(ss, "pmpaddr44"); + return; + + case 0x3dd: + SStream_concat(ss, "pmpaddr45"); + return; + + case 0x3de: + SStream_concat(ss, "pmpaddr46"); + return; + + case 0x3df: + SStream_concat(ss, "pmpaddr47"); + return; + + case 0x3e0: + SStream_concat(ss, "pmpaddr48"); + return; + + case 0x3e1: + SStream_concat(ss, "pmpaddr49"); + return; + + case 0x3e2: + SStream_concat(ss, "pmpaddr50"); + return; + + case 0x3e3: + SStream_concat(ss, "pmpaddr51"); + return; + + case 0x3e4: + SStream_concat(ss, "pmpaddr52"); + return; + + case 0x3e5: + SStream_concat(ss, "pmpaddr53"); + return; + + case 0x3e6: + SStream_concat(ss, "pmpaddr54"); + return; + + case 0x3e7: + SStream_concat(ss, "pmpaddr55"); + return; + + case 0x3e8: + SStream_concat(ss, "pmpaddr56"); + return; + + case 0x3e9: + SStream_concat(ss, "pmpaddr57"); + return; + + case 0x3ea: + SStream_concat(ss, "pmpaddr58"); + return; + + case 0x3eb: + SStream_concat(ss, "pmpaddr59"); + return; + + case 0x3ec: + SStream_concat(ss, "pmpaddr60"); + return; + + case 0x3ed: + SStream_concat(ss, "pmpaddr61"); + return; + + case 0x3ee: + SStream_concat(ss, "pmpaddr62"); + return; + + case 0x3ef: + SStream_concat(ss, "pmpaddr63"); + return; + + case 0x180: + SStream_concat(ss, "satp"); + return; + + case 0x321: + SStream_concat(ss, "mcyclecfg"); + return; + + case 0x721: + SStream_concat(ss, "mcyclecfgh"); + return; + + case 0x322: + SStream_concat(ss, "minstretcfg"); + return; + + case 0x722: + SStream_concat(ss, "minstretcfgh"); + return; + + case 0x14d: + SStream_concat(ss, "stimecmp"); + return; + + case 0x15d: + SStream_concat(ss, "stimecmph"); + return; + + case 0x301: + SStream_concat(ss, "misa"); + return; + + case 0x300: + SStream_concat(ss, "mstatus"); + return; + + case 0x30a: + SStream_concat(ss, "menvcfg"); + return; + + case 0x31a: + SStream_concat(ss, "menvcfgh"); + return; + + case 0x10a: + SStream_concat(ss, "senvcfg"); + return; + + case 0x304: + SStream_concat(ss, "mie"); + return; + + case 0x344: + SStream_concat(ss, "mip"); + return; + + case 0x302: + SStream_concat(ss, "medeleg"); + return; + + case 0x312: + SStream_concat(ss, "medelegh"); + return; + + case 0x303: + SStream_concat(ss, "mideleg"); + return; + + case 0x342: + SStream_concat(ss, "mcause"); + return; + + case 0x343: + SStream_concat(ss, "mtval"); + return; + + case 0x340: + SStream_concat(ss, "mscratch"); + return; + + case 0x106: + SStream_concat(ss, "scounteren"); + return; + + case 0x306: + SStream_concat(ss, "mcounteren"); + return; + + case 0x320: + SStream_concat(ss, "mcountinhibit"); + return; + + case 0xf11: + SStream_concat(ss, "mvendorid"); + return; + + case 0xf12: + SStream_concat(ss, "marchid"); + return; + + case 0xf13: + SStream_concat(ss, "mimpid"); + return; + + case 0xf14: + SStream_concat(ss, "mhartid"); + return; + + case 0xf15: + SStream_concat(ss, "mconfigptr"); + return; + + case 0x100: + SStream_concat(ss, "sstatus"); + return; + + case 0x144: + SStream_concat(ss, "sip"); + return; + + case 0x104: + SStream_concat(ss, "sie"); + return; + + case 0x140: + SStream_concat(ss, "sscratch"); + return; + + case 0x142: + SStream_concat(ss, "scause"); + return; + + case 0x143: + SStream_concat(ss, "stval"); + return; + + case 0x7a0: + SStream_concat(ss, "tselect"); + return; + + case 0x7a1: + SStream_concat(ss, "tdata1"); + return; + + case 0x7a2: + SStream_concat(ss, "tdata2"); + return; + + case 0x7a3: + SStream_concat(ss, "tdata3"); + return; + + case 0x015: + SStream_concat(ss, "seed"); + return; + + case 0xb83: + SStream_concat(ss, "mhpmcounter3h"); + return; + + case 0xb84: + SStream_concat(ss, "mhpmcounter4h"); + return; + + case 0xb85: + SStream_concat(ss, "mhpmcounter5h"); + return; + + case 0xb86: + SStream_concat(ss, "mhpmcounter6h"); + return; + + case 0xb87: + SStream_concat(ss, "mhpmcounter7h"); + return; + + case 0xb88: + SStream_concat(ss, "mhpmcounter8h"); + return; + + case 0xb89: + SStream_concat(ss, "mhpmcounter9h"); + return; + + case 0xb8a: + SStream_concat(ss, "mhpmcounter10h"); + return; + + case 0xb8b: + SStream_concat(ss, "mhpmcounter11h"); + return; + + case 0xb8c: + SStream_concat(ss, "mhpmcounter12h"); + return; + + case 0xb8d: + SStream_concat(ss, "mhpmcounter13h"); + return; + + case 0xb8e: + SStream_concat(ss, "mhpmcounter14h"); + return; + + case 0xb8f: + SStream_concat(ss, "mhpmcounter15h"); + return; + + case 0xb90: + SStream_concat(ss, "mhpmcounter16h"); + return; + + case 0xb91: + SStream_concat(ss, "mhpmcounter17h"); + return; + + case 0xb92: + SStream_concat(ss, "mhpmcounter18h"); + return; + + case 0xb93: + SStream_concat(ss, "mhpmcounter19h"); + return; + + case 0xb94: + SStream_concat(ss, "mhpmcounter20h"); + return; + + case 0xb95: + SStream_concat(ss, "mhpmcounter21h"); + return; + + case 0xb96: + SStream_concat(ss, "mhpmcounter22h"); + return; + + case 0xb97: + SStream_concat(ss, "mhpmcounter23h"); + return; + + case 0xb98: + SStream_concat(ss, "mhpmcounter24h"); + return; + + case 0xb99: + SStream_concat(ss, "mhpmcounter25h"); + return; + + case 0xb9a: + SStream_concat(ss, "mhpmcounter26h"); + return; + + case 0xb9b: + SStream_concat(ss, "mhpmcounter27h"); + return; + + case 0xb9c: + SStream_concat(ss, "mhpmcounter28h"); + return; + + case 0xb9d: + SStream_concat(ss, "mhpmcounter29h"); + return; + + case 0xb9e: + SStream_concat(ss, "mhpmcounter30h"); + return; + + case 0xb9f: + SStream_concat(ss, "mhpmcounter31h"); + return; + + case 0xda0: + SStream_concat(ss, "scountovf"); + return; + + case 0x001: + SStream_concat(ss, "fflags"); + return; + + case 0x002: + SStream_concat(ss, "frm"); + return; + + case 0x003: + SStream_concat(ss, "fcsr"); + return; + + case 0xc00: + SStream_concat(ss, "cycle"); + return; + + case 0xc01: + SStream_concat(ss, "time"); + return; + + case 0xc02: + SStream_concat(ss, "instret"); + return; + + case 0xc80: + SStream_concat(ss, "cycleh"); + return; + + case 0xc81: + SStream_concat(ss, "timeh"); + return; + + case 0xc82: + SStream_concat(ss, "instreth"); + return; + + case 0xb00: + SStream_concat(ss, "mcycle"); + return; + + case 0xb02: + SStream_concat(ss, "minstret"); + return; + + case 0xb80: + SStream_concat(ss, "mcycleh"); + return; + + case 0xb82: + SStream_concat(ss, "minstreth"); + return; + + case 0xc03: + SStream_concat(ss, "hpmcounter3"); + return; + + case 0xc04: + SStream_concat(ss, "hpmcounter4"); + return; + + case 0xc05: + SStream_concat(ss, "hpmcounter5"); + return; + + case 0xc06: + SStream_concat(ss, "hpmcounter6"); + return; + + case 0xc07: + SStream_concat(ss, "hpmcounter7"); + return; + + case 0xc08: + SStream_concat(ss, "hpmcounter8"); + return; + + case 0xc09: + SStream_concat(ss, "hpmcounter9"); + return; + + case 0xc0a: + SStream_concat(ss, "hpmcounter10"); + return; + + case 0xc0b: + SStream_concat(ss, "hpmcounter11"); + return; + + case 0xc0c: + SStream_concat(ss, "hpmcounter12"); + return; + + case 0xc0d: + SStream_concat(ss, "hpmcounter13"); + return; + + case 0xc0e: + SStream_concat(ss, "hpmcounter14"); + return; + + case 0xc0f: + SStream_concat(ss, "hpmcounter15"); + return; + + case 0xc10: + SStream_concat(ss, "hpmcounter16"); + return; + + case 0xc11: + SStream_concat(ss, "hpmcounter17"); + return; + + case 0xc12: + SStream_concat(ss, "hpmcounter18"); + return; + + case 0xc13: + SStream_concat(ss, "hpmcounter19"); + return; + + case 0xc14: + SStream_concat(ss, "hpmcounter20"); + return; + + case 0xc15: + SStream_concat(ss, "hpmcounter21"); + return; + + case 0xc16: + SStream_concat(ss, "hpmcounter22"); + return; + + case 0xc17: + SStream_concat(ss, "hpmcounter23"); + return; + + case 0xc18: + SStream_concat(ss, "hpmcounter24"); + return; + + case 0xc19: + SStream_concat(ss, "hpmcounter25"); + return; + + case 0xc1a: + SStream_concat(ss, "hpmcounter26"); + return; + + case 0xc1b: + SStream_concat(ss, "hpmcounter27"); + return; + + case 0xc1c: + SStream_concat(ss, "hpmcounter28"); + return; + + case 0xc1d: + SStream_concat(ss, "hpmcounter29"); + return; + + case 0xc1e: + SStream_concat(ss, "hpmcounter30"); + return; + + case 0xc1f: + SStream_concat(ss, "hpmcounter31"); + return; + + case 0xc83: + SStream_concat(ss, "hpmcounter3h"); + return; + + case 0xc84: + SStream_concat(ss, "hpmcounter4h"); + return; + + case 0xc85: + SStream_concat(ss, "hpmcounter5h"); + return; + + case 0xc86: + SStream_concat(ss, "hpmcounter6h"); + return; + + case 0xc87: + SStream_concat(ss, "hpmcounter7h"); + return; + + case 0xc88: + SStream_concat(ss, "hpmcounter8h"); + return; + + case 0xc89: + SStream_concat(ss, "hpmcounter9h"); + return; + + case 0xc8a: + SStream_concat(ss, "hpmcounter10h"); + return; + + case 0xc8b: + SStream_concat(ss, "hpmcounter11h"); + return; + + case 0xc8c: + SStream_concat(ss, "hpmcounter12h"); + return; + + case 0xc8d: + SStream_concat(ss, "hpmcounter13h"); + return; + + case 0xc8e: + SStream_concat(ss, "hpmcounter14h"); + return; + + case 0xc8f: + SStream_concat(ss, "hpmcounter15h"); + return; + + case 0xc90: + SStream_concat(ss, "hpmcounter16h"); + return; + + case 0xc91: + SStream_concat(ss, "hpmcounter17h"); + return; + + case 0xc92: + SStream_concat(ss, "hpmcounter18h"); + return; + + case 0xc93: + SStream_concat(ss, "hpmcounter19h"); + return; + + case 0xc94: + SStream_concat(ss, "hpmcounter20h"); + return; + + case 0xc95: + SStream_concat(ss, "hpmcounter21h"); + return; + + case 0xc96: + SStream_concat(ss, "hpmcounter22h"); + return; + + case 0xc97: + SStream_concat(ss, "hpmcounter23h"); + return; + + case 0xc98: + SStream_concat(ss, "hpmcounter24h"); + return; + + case 0xc99: + SStream_concat(ss, "hpmcounter25h"); + return; + + case 0xc9a: + SStream_concat(ss, "hpmcounter26h"); + return; + + case 0xc9b: + SStream_concat(ss, "hpmcounter27h"); + return; + + case 0xc9c: + SStream_concat(ss, "hpmcounter28h"); + return; + + case 0xc9d: + SStream_concat(ss, "hpmcounter29h"); + return; + + case 0xc9e: + SStream_concat(ss, "hpmcounter30h"); + return; + + case 0xc9f: + SStream_concat(ss, "hpmcounter31h"); + return; + + case 0x323: + SStream_concat(ss, "mhpmevent3"); + return; + + case 0x324: + SStream_concat(ss, "mhpmevent4"); + return; + + case 0x325: + SStream_concat(ss, "mhpmevent5"); + return; + + case 0x326: + SStream_concat(ss, "mhpmevent6"); + return; + + case 0x327: + SStream_concat(ss, "mhpmevent7"); + return; + + case 0x328: + SStream_concat(ss, "mhpmevent8"); + return; + + case 0x329: + SStream_concat(ss, "mhpmevent9"); + return; + + case 0x32a: + SStream_concat(ss, "mhpmevent10"); + return; + + case 0x32b: + SStream_concat(ss, "mhpmevent11"); + return; + + case 0x32c: + SStream_concat(ss, "mhpmevent12"); + return; + + case 0x32d: + SStream_concat(ss, "mhpmevent13"); + return; + + case 0x32e: + SStream_concat(ss, "mhpmevent14"); + return; + + case 0x32f: + SStream_concat(ss, "mhpmevent15"); + return; + + case 0x330: + SStream_concat(ss, "mhpmevent16"); + return; + + case 0x331: + SStream_concat(ss, "mhpmevent17"); + return; + + case 0x332: + SStream_concat(ss, "mhpmevent18"); + return; + + case 0x333: + SStream_concat(ss, "mhpmevent19"); + return; + + case 0x334: + SStream_concat(ss, "mhpmevent20"); + return; + + case 0x335: + SStream_concat(ss, "mhpmevent21"); + return; + + case 0x336: + SStream_concat(ss, "mhpmevent22"); + return; + + case 0x337: + SStream_concat(ss, "mhpmevent23"); + return; + + case 0x338: + SStream_concat(ss, "mhpmevent24"); + return; + + case 0x339: + SStream_concat(ss, "mhpmevent25"); + return; + + case 0x33a: + SStream_concat(ss, "mhpmevent26"); + return; + + case 0x33b: + SStream_concat(ss, "mhpmevent27"); + return; + + case 0x33c: + SStream_concat(ss, "mhpmevent28"); + return; + + case 0x33d: + SStream_concat(ss, "mhpmevent29"); + return; + + case 0x33e: + SStream_concat(ss, "mhpmevent30"); + return; + + case 0x33f: + SStream_concat(ss, "mhpmevent31"); + return; + + case 0xb03: + SStream_concat(ss, "mhpmcounter3"); + return; + + case 0xb04: + SStream_concat(ss, "mhpmcounter4"); + return; + + case 0xb05: + SStream_concat(ss, "mhpmcounter5"); + return; + + case 0xb06: + SStream_concat(ss, "mhpmcounter6"); + return; + + case 0xb07: + SStream_concat(ss, "mhpmcounter7"); + return; + + case 0xb08: + SStream_concat(ss, "mhpmcounter8"); + return; + + case 0xb09: + SStream_concat(ss, "mhpmcounter9"); + return; + + case 0xb0a: + SStream_concat(ss, "mhpmcounter10"); + return; + + case 0xb0b: + SStream_concat(ss, "mhpmcounter11"); + return; + + case 0xb0c: + SStream_concat(ss, "mhpmcounter12"); + return; + + case 0xb0d: + SStream_concat(ss, "mhpmcounter13"); + return; + + case 0xb0e: + SStream_concat(ss, "mhpmcounter14"); + return; + + case 0xb0f: + SStream_concat(ss, "mhpmcounter15"); + return; + + case 0xb10: + SStream_concat(ss, "mhpmcounter16"); + return; + + case 0xb11: + SStream_concat(ss, "mhpmcounter17"); + return; + + case 0xb12: + SStream_concat(ss, "mhpmcounter18"); + return; + + case 0xb13: + SStream_concat(ss, "mhpmcounter19"); + return; + + case 0xb14: + SStream_concat(ss, "mhpmcounter20"); + return; + + case 0xb15: + SStream_concat(ss, "mhpmcounter21"); + return; + + case 0xb16: + SStream_concat(ss, "mhpmcounter22"); + return; + + case 0xb17: + SStream_concat(ss, "mhpmcounter23"); + return; + + case 0xb18: + SStream_concat(ss, "mhpmcounter24"); + return; + + case 0xb19: + SStream_concat(ss, "mhpmcounter25"); + return; + + case 0xb1a: + SStream_concat(ss, "mhpmcounter26"); + return; + + case 0xb1b: + SStream_concat(ss, "mhpmcounter27"); + return; + + case 0xb1c: + SStream_concat(ss, "mhpmcounter28"); + return; + + case 0xb1d: + SStream_concat(ss, "mhpmcounter29"); + return; + + case 0xb1e: + SStream_concat(ss, "mhpmcounter30"); + return; + + case 0xb1f: + SStream_concat(ss, "mhpmcounter31"); + return; + + case 0x105: + SStream_concat(ss, "stvec"); + return; + + case 0x141: + SStream_concat(ss, "sepc"); + return; + + case 0x305: + SStream_concat(ss, "mtvec"); + return; + + case 0x341: + SStream_concat(ss, "mepc"); + return; + + case 0x008: + SStream_concat(ss, "vstart"); + return; + + case 0x009: + SStream_concat(ss, "vxsat"); + return; + + case 0x00a: + SStream_concat(ss, "vxrm"); + return; + + case 0x00f: + SStream_concat(ss, "vcsr"); + return; + + case 0xc20: + SStream_concat(ss, "vl"); + return; + + case 0xc21: + SStream_concat(ss, "vtype"); + return; + + case 0xc22: + SStream_concat(ss, "vlenb"); + return; + + default: + hex_bits_12(csr, ss, ctx); + return; + } +} + +static inline void fence_bits(uint8_t bits, SStream *ss, RVContext *ctx) { + if (bits & 0x8) { + SStream_concat1(ss, 'i'); + } + if (bits & 0x4) { + SStream_concat1(ss, 'o'); + } + if (bits & 0x2) { + SStream_concat1(ss, 'r'); + } + if (bits & 0x1) { + SStream_concat1(ss, 'w'); + } +} + +static inline void dec_bits(uint64_t val, SStream *ss, RVContext *ctx, + uint32_t n) { + for (int i = 0; i < n; i++) { + // most significant bit printed first + uint64_t bit = val & (1ULL << (n - 1 - i)); + SStream_concat1(ss, (bit == 0) ? '0' : '1'); + } +} + +#define DEF_DEC_BITS(n) \ + static inline void dec_bits_##n(uint64_t val, SStream *ss, RVContext *ctx) { \ + dec_bits(val, ss, ctx, n); \ + } +DEF_DEC_BITS(1) +DEF_DEC_BITS(2) +DEF_DEC_BITS(3) +DEF_DEC_BITS(4) +DEF_DEC_BITS(5) + +#endif \ No newline at end of file diff --git a/arch/RISCV/RISCVAst2StrTbls.gen.inc b/arch/RISCV/RISCVAst2StrTbls.gen.inc new file mode 100644 index 0000000000..678366c9db --- /dev/null +++ b/arch/RISCV/RISCVAst2StrTbls.gen.inc @@ -0,0 +1,2442 @@ +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ + +#ifndef __RISCVAST2STRTBLS_GEN_INC__ +#define __RISCVAST2STRTBLS_GEN_INC__ +#include +#include +#include + +#include "../../SStream.h" +#include "RISCVAst.gen.inc" + +void utype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_LUI: { + SStream_concat(ss, "lui"); + break; + } + case RISCV_AUIPC: { + SStream_concat(ss, "auipc"); + break; + } + } +} +void btype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_BGEU: { + SStream_concat(ss, "bgeu"); + break; + } + case RISCV_BLT: { + SStream_concat(ss, "blt"); + break; + } + case RISCV_BGE: { + SStream_concat(ss, "bge"); + break; + } + case RISCV_BLTU: { + SStream_concat(ss, "bltu"); + break; + } + case RISCV_BNE: { + SStream_concat(ss, "bne"); + break; + } + case RISCV_BEQ: { + SStream_concat(ss, "beq"); + break; + } + } +} +void itype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_ANDI: { + SStream_concat(ss, "andi"); + break; + } + case RISCV_ADDI: { + SStream_concat(ss, "addi"); + break; + } + case RISCV_XORI: { + SStream_concat(ss, "xori"); + break; + } + case RISCV_SLTI: { + SStream_concat(ss, "slti"); + break; + } + case RISCV_ORI: { + SStream_concat(ss, "ori"); + break; + } + case RISCV_SLTIU: { + SStream_concat(ss, "sltiu"); + break; + } + } +} +void shiftiop_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_SRAI: { + SStream_concat(ss, "srai"); + break; + } + case RISCV_SRLI: { + SStream_concat(ss, "srli"); + break; + } + case RISCV_SLLI: { + SStream_concat(ss, "slli"); + break; + } + } +} +void rtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_SLL: { + SStream_concat(ss, "sll"); + break; + } + case RISCV_SRL: { + SStream_concat(ss, "srl"); + break; + } + case RISCV_SLTU: { + SStream_concat(ss, "sltu"); + break; + } + case RISCV_ADD: { + SStream_concat(ss, "add"); + break; + } + case RISCV_XOR: { + SStream_concat(ss, "xor"); + break; + } + case RISCV_SLT: { + SStream_concat(ss, "slt"); + break; + } + case RISCV_AND: { + SStream_concat(ss, "and"); + break; + } + case RISCV_OR: { + SStream_concat(ss, "or"); + break; + } + case RISCV_SRA: { + SStream_concat(ss, "sra"); + break; + } + case RISCV_SUB: { + SStream_concat(ss, "sub"); + break; + } + } +} +void size_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_BYTE: { + SStream_concat(ss, "b"); + break; + } + case RISCV_WORD: { + SStream_concat(ss, "w"); + break; + } + case RISCV_DOUBLE: { + SStream_concat(ss, "d"); + break; + } + case RISCV_HALF: { + SStream_concat(ss, "h"); + break; + } + } +} +void rtypew_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_SRAW: { + SStream_concat(ss, "sraw"); + break; + } + case RISCV_SUBW: { + SStream_concat(ss, "subw"); + break; + } + case RISCV_SLLW: { + SStream_concat(ss, "sllw"); + break; + } + case RISCV_SRLW: { + SStream_concat(ss, "srlw"); + break; + } + case RISCV_ADDW: { + SStream_concat(ss, "addw"); + break; + } + } +} +void shiftiwop_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_SRLIW: { + SStream_concat(ss, "srliw"); + break; + } + case RISCV_SLLIW: { + SStream_concat(ss, "slliw"); + break; + } + case RISCV_SRAIW: { + SStream_concat(ss, "sraiw"); + break; + } + } +} +void amo_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_AMOMIN: { + SStream_concat(ss, "amomin"); + break; + } + case RISCV_AMOXOR: { + SStream_concat(ss, "amoxor"); + break; + } + case RISCV_AMOADD: { + SStream_concat(ss, "amoadd"); + break; + } + case RISCV_AMOOR: { + SStream_concat(ss, "amoor"); + break; + } + case RISCV_AMOSWAP: { + SStream_concat(ss, "amoswap"); + break; + } + case RISCV_AMOMAX: { + SStream_concat(ss, "amomax"); + break; + } + case RISCV_AMOMINU: { + SStream_concat(ss, "amominu"); + break; + } + case RISCV_AMOAND: { + SStream_concat(ss, "amoand"); + break; + } + case RISCV_AMOMAXU: { + SStream_concat(ss, "amomaxu"); + break; + } + } +} +void csr_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_CSRRS: { + SStream_concat(ss, "csrrs"); + break; + } + case RISCV_CSRRW: { + SStream_concat(ss, "csrrw"); + break; + } + case RISCV_CSRRC: { + SStream_concat(ss, "csrrc"); + break; + } + } +} +void f_madd_type_mnemonic_S(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FMADD_S: { + SStream_concat(ss, "fmadd.s"); + break; + } + case RISCV_FNMADD_S: { + SStream_concat(ss, "fnmadd.s"); + break; + } + case RISCV_FNMSUB_S: { + SStream_concat(ss, "fnmsub.s"); + break; + } + case RISCV_FMSUB_S: { + SStream_concat(ss, "fmsub.s"); + break; + } + } +} +void frm_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_RM_RNE: { + SStream_concat(ss, "rne"); + break; + } + case RISCV_RM_RTZ: { + SStream_concat(ss, "rtz"); + break; + } + case RISCV_RM_RDN: { + SStream_concat(ss, "rdn"); + break; + } + case RISCV_RM_RMM: { + SStream_concat(ss, "rmm"); + break; + } + case RISCV_RM_RUP: { + SStream_concat(ss, "rup"); + break; + } + case RISCV_RM_DYN: { + SStream_concat(ss, "dyn"); + break; + } + } +} +void f_bin_rm_type_mnemonic_S(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FDIV_S: { + SStream_concat(ss, "fdiv.s"); + break; + } + case RISCV_FADD_S: { + SStream_concat(ss, "fadd.s"); + break; + } + case RISCV_FMUL_S: { + SStream_concat(ss, "fmul.s"); + break; + } + case RISCV_FSUB_S: { + SStream_concat(ss, "fsub.s"); + break; + } + } +} +void f_un_rm_fx_type_mnemonic_S(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FCVT_LU_S: { + SStream_concat(ss, "fcvt.lu.s"); + break; + } + case RISCV_FCVT_WU_S: { + SStream_concat(ss, "fcvt.wu.s"); + break; + } + case RISCV_FCVT_W_S: { + SStream_concat(ss, "fcvt.w.s"); + break; + } + case RISCV_FCVT_L_S: { + SStream_concat(ss, "fcvt.l.s"); + break; + } + } +} +void f_un_rm_xf_type_mnemonic_S(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FCVT_S_L: { + SStream_concat(ss, "fcvt.s.l"); + break; + } + case RISCV_FCVT_S_WU: { + SStream_concat(ss, "fcvt.s.wu"); + break; + } + case RISCV_FCVT_S_W: { + SStream_concat(ss, "fcvt.s.w"); + break; + } + case RISCV_FCVT_S_LU: { + SStream_concat(ss, "fcvt.s.lu"); + break; + } + } +} +void f_bin_type_mnemonic_f_S(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FSGNJ_S: { + SStream_concat(ss, "fsgnj.s"); + break; + } + case RISCV_FSGNJN_S: { + SStream_concat(ss, "fsgnjn.s"); + break; + } + case RISCV_FSGNJX_S: { + SStream_concat(ss, "fsgnjx.s"); + break; + } + case RISCV_FMIN_S: { + SStream_concat(ss, "fmin.s"); + break; + } + case RISCV_FMAX_S: { + SStream_concat(ss, "fmax.s"); + break; + } + } +} +void f_bin_type_mnemonic_x_S(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FEQ_S: { + SStream_concat(ss, "feq.s"); + break; + } + case RISCV_FLT_S: { + SStream_concat(ss, "flt.s"); + break; + } + case RISCV_FLE_S: { + SStream_concat(ss, "fle.s"); + break; + } + } +} +void f_un_type_mnemonic_x_S(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FMV_X_W: { + SStream_concat(ss, "fmv.x.w"); + break; + } + case RISCV_FCLASS_S: { + SStream_concat(ss, "fclass.s"); + break; + } + } +} +void f_un_type_mnemonic_f_S(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FMV_W_X: { + SStream_concat(ss, "fmv.w.x"); + break; + } + } +} +void f_madd_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FMSUB_D: { + SStream_concat(ss, "fmsub.d"); + break; + } + case RISCV_FNMSUB_D: { + SStream_concat(ss, "fnmsub.d"); + break; + } + case RISCV_FNMADD_D: { + SStream_concat(ss, "fnmadd.d"); + break; + } + case RISCV_FMADD_D: { + SStream_concat(ss, "fmadd.d"); + break; + } + } +} +void f_bin_rm_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FMUL_D: { + SStream_concat(ss, "fmul.d"); + break; + } + case RISCV_FADD_D: { + SStream_concat(ss, "fadd.d"); + break; + } + case RISCV_FSUB_D: { + SStream_concat(ss, "fsub.d"); + break; + } + case RISCV_FDIV_D: { + SStream_concat(ss, "fdiv.d"); + break; + } + } +} +void f_un_rm_ff_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FSQRT_D: { + SStream_concat(ss, "fsqrt.d"); + break; + } + case RISCV_FCVT_S_D: { + SStream_concat(ss, "fcvt.s.d"); + break; + } + case RISCV_FCVT_D_S: { + SStream_concat(ss, "fcvt.d.s"); + break; + } + } +} +void f_un_rm_fx_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FCVT_L_D: { + SStream_concat(ss, "fcvt.l.d"); + break; + } + case RISCV_FCVT_WU_D: { + SStream_concat(ss, "fcvt.wu.d"); + break; + } + case RISCV_FCVT_W_D: { + SStream_concat(ss, "fcvt.w.d"); + break; + } + case RISCV_FCVT_LU_D: { + SStream_concat(ss, "fcvt.lu.d"); + break; + } + } +} +void f_un_rm_xf_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FCVT_D_LU: { + SStream_concat(ss, "fcvt.d.lu"); + break; + } + case RISCV_FCVT_D_WU: { + SStream_concat(ss, "fcvt.d.wu"); + break; + } + case RISCV_FCVT_D_W: { + SStream_concat(ss, "fcvt.d.w"); + break; + } + case RISCV_FCVT_D_L: { + SStream_concat(ss, "fcvt.d.l"); + break; + } + } +} +void f_bin_f_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FSGNJ_D: { + SStream_concat(ss, "fsgnj.d"); + break; + } + case RISCV_FMAX_D: { + SStream_concat(ss, "fmax.d"); + break; + } + case RISCV_FSGNJX_D: { + SStream_concat(ss, "fsgnjx.d"); + break; + } + case RISCV_FSGNJN_D: { + SStream_concat(ss, "fsgnjn.d"); + break; + } + case RISCV_FMIN_D: { + SStream_concat(ss, "fmin.d"); + break; + } + } +} +void f_bin_x_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FLE_D: { + SStream_concat(ss, "fle.d"); + break; + } + case RISCV_FEQ_D: { + SStream_concat(ss, "feq.d"); + break; + } + case RISCV_FLT_D: { + SStream_concat(ss, "flt.d"); + break; + } + } +} +void f_un_x_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FCLASS_D: { + SStream_concat(ss, "fclass.d"); + break; + } + case RISCV_FMV_X_D: { + SStream_concat(ss, "fmv.x.d"); + break; + } + } +} +void f_un_f_type_mnemonic_D(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FMV_D_X: { + SStream_concat(ss, "fmv.d.x"); + break; + } + } +} +void zba_rtypeuw_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_SH1ADDUW: { + SStream_concat(ss, "sh1add.uw"); + break; + } + case RISCV_SH2ADDUW: { + SStream_concat(ss, "sh2add.uw"); + break; + } + case RISCV_ADDUW: { + SStream_concat(ss, "add.uw"); + break; + } + case RISCV_SH3ADDUW: { + SStream_concat(ss, "sh3add.uw"); + break; + } + } +} +void zba_rtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_SH3ADD: { + SStream_concat(ss, "sh3add"); + break; + } + case RISCV_SH2ADD: { + SStream_concat(ss, "sh2add"); + break; + } + case RISCV_SH1ADD: { + SStream_concat(ss, "sh1add"); + break; + } + } +} +void zbb_rtypew_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_RORW: { + SStream_concat(ss, "rorw"); + break; + } + case RISCV_ROLW: { + SStream_concat(ss, "rolw"); + break; + } + } +} +void zbb_rtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_ROR: { + SStream_concat(ss, "ror"); + break; + } + case RISCV_MAXU: { + SStream_concat(ss, "maxu"); + break; + } + case RISCV_MIN: { + SStream_concat(ss, "min"); + break; + } + case RISCV_MAX: { + SStream_concat(ss, "max"); + break; + } + case RISCV_ANDN: { + SStream_concat(ss, "andn"); + break; + } + case RISCV_ORN: { + SStream_concat(ss, "orn"); + break; + } + case RISCV_XNOR: { + SStream_concat(ss, "xnor"); + break; + } + case RISCV_MINU: { + SStream_concat(ss, "minu"); + break; + } + case RISCV_ROL: { + SStream_concat(ss, "rol"); + break; + } + } +} +void zbb_extop_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_SEXTH: { + SStream_concat(ss, "sext.h"); + break; + } + case RISCV_ZEXTH: { + SStream_concat(ss, "zext.h"); + break; + } + case RISCV_SEXTB: { + SStream_concat(ss, "sext.b"); + break; + } + } +} +void zbs_iop_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_BCLRI: { + SStream_concat(ss, "bclri"); + break; + } + case RISCV_BINVI: { + SStream_concat(ss, "binvi"); + break; + } + case RISCV_BSETI: { + SStream_concat(ss, "bseti"); + break; + } + case RISCV_BEXTI: { + SStream_concat(ss, "bexti"); + break; + } + } +} +void zbs_rtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_BEXT: { + SStream_concat(ss, "bext"); + break; + } + case RISCV_BINV: { + SStream_concat(ss, "binv"); + break; + } + case RISCV_BSET: { + SStream_concat(ss, "bset"); + break; + } + case RISCV_BCLR: { + SStream_concat(ss, "bclr"); + break; + } + } +} +void f_bin_rm_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FDIV_H: { + SStream_concat(ss, "fdiv.h"); + break; + } + case RISCV_FADD_H: { + SStream_concat(ss, "fadd.h"); + break; + } + case RISCV_FMUL_H: { + SStream_concat(ss, "fmul.h"); + break; + } + case RISCV_FSUB_H: { + SStream_concat(ss, "fsub.h"); + break; + } + } +} +void f_madd_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FNMSUB_H: { + SStream_concat(ss, "fnmsub.h"); + break; + } + case RISCV_FMSUB_H: { + SStream_concat(ss, "fmsub.h"); + break; + } + case RISCV_FNMADD_H: { + SStream_concat(ss, "fnmadd.h"); + break; + } + case RISCV_FMADD_H: { + SStream_concat(ss, "fmadd.h"); + break; + } + } +} +void f_bin_f_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FSGNJ_H: { + SStream_concat(ss, "fsgnj.h"); + break; + } + case RISCV_FMIN_H: { + SStream_concat(ss, "fmin.h"); + break; + } + case RISCV_FSGNJX_H: { + SStream_concat(ss, "fsgnjx.h"); + break; + } + case RISCV_FMAX_H: { + SStream_concat(ss, "fmax.h"); + break; + } + case RISCV_FSGNJN_H: { + SStream_concat(ss, "fsgnjn.h"); + break; + } + } +} +void f_bin_x_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FLE_H: { + SStream_concat(ss, "fle.h"); + break; + } + case RISCV_FLT_H: { + SStream_concat(ss, "flt.h"); + break; + } + case RISCV_FEQ_H: { + SStream_concat(ss, "feq.h"); + break; + } + } +} +void f_un_rm_ff_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FSQRT_H: { + SStream_concat(ss, "fsqrt.h"); + break; + } + case RISCV_FCVT_H_S: { + SStream_concat(ss, "fcvt.h.s"); + break; + } + case RISCV_FCVT_S_H: { + SStream_concat(ss, "fcvt.s.h"); + break; + } + case RISCV_FCVT_D_H: { + SStream_concat(ss, "fcvt.d.h"); + break; + } + case RISCV_FCVT_H_D: { + SStream_concat(ss, "fcvt.h.d"); + break; + } + } +} +void f_un_rm_fx_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FCVT_L_H: { + SStream_concat(ss, "fcvt.l.h"); + break; + } + case RISCV_FCVT_LU_H: { + SStream_concat(ss, "fcvt.lu.h"); + break; + } + case RISCV_FCVT_W_H: { + SStream_concat(ss, "fcvt.w.h"); + break; + } + case RISCV_FCVT_WU_H: { + SStream_concat(ss, "fcvt.wu.h"); + break; + } + } +} +void f_un_rm_xf_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FCVT_H_L: { + SStream_concat(ss, "fcvt.h.l"); + break; + } + case RISCV_FCVT_H_W: { + SStream_concat(ss, "fcvt.h.w"); + break; + } + case RISCV_FCVT_H_LU: { + SStream_concat(ss, "fcvt.h.lu"); + break; + } + case RISCV_FCVT_H_WU: { + SStream_concat(ss, "fcvt.h.wu"); + break; + } + } +} +void f_un_f_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FMV_H_X: { + SStream_concat(ss, "fmv.h.x"); + break; + } + } +} +void f_un_x_type_mnemonic_H(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FCLASS_H: { + SStream_concat(ss, "fclass.h"); + break; + } + case RISCV_FMV_X_H: { + SStream_concat(ss, "fmv.x.h"); + break; + } + } +} +void zbkb_rtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_PACKH: { + SStream_concat(ss, "packh"); + break; + } + case RISCV_PACK: { + SStream_concat(ss, "pack"); + break; + } + } +} +void zicond_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_CZERO_EQZ: { + SStream_concat(ss, "czero.eqz"); + break; + } + case RISCV_CZERO_NEZ: { + SStream_concat(ss, "czero.nez"); + break; + } + } +} +void sew_flag(uint64_t member, SStream *ss) { + switch (member) { + case 0x1: { + SStream_concat(ss, "e16"); + break; + } + case 0x3: { + SStream_concat(ss, "e64"); + break; + } + case 0x2: { + SStream_concat(ss, "e32"); + break; + } + case 0x0: { + SStream_concat(ss, "e8"); + break; + } + } +} +void vvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VV_VSSRA: { + SStream_concat(ss, "vssra.vv"); + break; + } + case RISCV_VV_VXOR: { + SStream_concat(ss, "vxor.vv"); + break; + } + case RISCV_VV_VSMUL: { + SStream_concat(ss, "vsmul.vv"); + break; + } + case RISCV_VV_VAND: { + SStream_concat(ss, "vand.vv"); + break; + } + case RISCV_VV_VSSUB: { + SStream_concat(ss, "vssub.vv"); + break; + } + case RISCV_VV_VSUB: { + SStream_concat(ss, "vsub.vv"); + break; + } + case RISCV_VV_VSLL: { + SStream_concat(ss, "vsll.vv"); + break; + } + case RISCV_VV_VSSRL: { + SStream_concat(ss, "vssrl.vv"); + break; + } + case RISCV_VV_VSADD: { + SStream_concat(ss, "vsadd.vv"); + break; + } + case RISCV_VV_VSSUBU: { + SStream_concat(ss, "vssubu.vv"); + break; + } + case RISCV_VV_VMAX: { + SStream_concat(ss, "vmax.vv"); + break; + } + case RISCV_VV_VADD: { + SStream_concat(ss, "vadd.vv"); + break; + } + case RISCV_VV_VSRL: { + SStream_concat(ss, "vsrl.vv"); + break; + } + case RISCV_VV_VMAXU: { + SStream_concat(ss, "vmaxu.vv"); + break; + } + case RISCV_VV_VRGATHER: { + SStream_concat(ss, "vrgather.vv"); + break; + } + case RISCV_VV_VSRA: { + SStream_concat(ss, "vsra.vv"); + break; + } + case RISCV_VV_VRGATHEREI16: { + SStream_concat(ss, "vrgatherei16.vv"); + break; + } + case RISCV_VV_VMINU: { + SStream_concat(ss, "vminu.vv"); + break; + } + case RISCV_VV_VSADDU: { + SStream_concat(ss, "vsaddu.vv"); + break; + } + case RISCV_VV_VMIN: { + SStream_concat(ss, "vmin.vv"); + break; + } + case RISCV_VV_VOR: { + SStream_concat(ss, "vor.vv"); + break; + } + } +} +void nvstype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_NVS_VNSRL: { + SStream_concat(ss, "vnsrl.wv"); + break; + } + case RISCV_NVS_VNSRA: { + SStream_concat(ss, "vnsra.wv"); + break; + } + } +} +void nvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_NV_VNCLIP: { + SStream_concat(ss, "vnclip.wv"); + break; + } + case RISCV_NV_VNCLIPU: { + SStream_concat(ss, "vnclipu.wv"); + break; + } + } +} +void vxtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VX_VSRA: { + SStream_concat(ss, "vsra.vx"); + break; + } + case RISCV_VX_VOR: { + SStream_concat(ss, "vor.vx"); + break; + } + case RISCV_VX_VADD: { + SStream_concat(ss, "vadd.vx"); + break; + } + case RISCV_VX_VSADDU: { + SStream_concat(ss, "vsaddu.vx"); + break; + } + case RISCV_VX_VMAX: { + SStream_concat(ss, "vmax.vx"); + break; + } + case RISCV_VX_VSSRA: { + SStream_concat(ss, "vssra.vx"); + break; + } + case RISCV_VX_VXOR: { + SStream_concat(ss, "vxor.vx"); + break; + } + case RISCV_VX_VSSRL: { + SStream_concat(ss, "vssrl.vx"); + break; + } + case RISCV_VX_VRSUB: { + SStream_concat(ss, "vrsub.vx"); + break; + } + case RISCV_VX_VSUB: { + SStream_concat(ss, "vsub.vx"); + break; + } + case RISCV_VX_VSADD: { + SStream_concat(ss, "vsadd.vx"); + break; + } + case RISCV_VX_VSSUBU: { + SStream_concat(ss, "vssubu.vx"); + break; + } + case RISCV_VX_VMIN: { + SStream_concat(ss, "vmin.vx"); + break; + } + case RISCV_VX_VSLL: { + SStream_concat(ss, "vsll.vx"); + break; + } + case RISCV_VX_VSMUL: { + SStream_concat(ss, "vsmul.vx"); + break; + } + case RISCV_VX_VMINU: { + SStream_concat(ss, "vminu.vx"); + break; + } + case RISCV_VX_VMAXU: { + SStream_concat(ss, "vmaxu.vx"); + break; + } + case RISCV_VX_VAND: { + SStream_concat(ss, "vand.vx"); + break; + } + case RISCV_VX_VSSUB: { + SStream_concat(ss, "vssub.vx"); + break; + } + case RISCV_VX_VSRL: { + SStream_concat(ss, "vsrl.vx"); + break; + } + } +} +void nxstype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_NXS_VNSRA: { + SStream_concat(ss, "vnsra.wx"); + break; + } + case RISCV_NXS_VNSRL: { + SStream_concat(ss, "vnsrl.wx"); + break; + } + } +} +void nxtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_NX_VNCLIP: { + SStream_concat(ss, "vnclip.wx"); + break; + } + case RISCV_NX_VNCLIPU: { + SStream_concat(ss, "vnclipu.wx"); + break; + } + } +} +void vxsg_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VX_VSLIDEDOWN: { + SStream_concat(ss, "vslidedown.vx"); + break; + } + case RISCV_VX_VSLIDEUP: { + SStream_concat(ss, "vslideup.vx"); + break; + } + case RISCV_VX_VRGATHER: { + SStream_concat(ss, "vrgather.vx"); + break; + } + } +} +void vitype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VI_VSRL: { + SStream_concat(ss, "vsrl.vi"); + break; + } + case RISCV_VI_VAND: { + SStream_concat(ss, "vand.vi"); + break; + } + case RISCV_VI_VXOR: { + SStream_concat(ss, "vxor.vi"); + break; + } + case RISCV_VI_VSADD: { + SStream_concat(ss, "vsadd.vi"); + break; + } + case RISCV_VI_VSRA: { + SStream_concat(ss, "vsra.vi"); + break; + } + case RISCV_VI_VSSRL: { + SStream_concat(ss, "vssrl.vi"); + break; + } + case RISCV_VI_VSADDU: { + SStream_concat(ss, "vsaddu.vi"); + break; + } + case RISCV_VI_VSLL: { + SStream_concat(ss, "vsll.vi"); + break; + } + case RISCV_VI_VRSUB: { + SStream_concat(ss, "vrsub.vi"); + break; + } + case RISCV_VI_VADD: { + SStream_concat(ss, "vadd.vi"); + break; + } + case RISCV_VI_VOR: { + SStream_concat(ss, "vor.vi"); + break; + } + case RISCV_VI_VSSRA: { + SStream_concat(ss, "vssra.vi"); + break; + } + } +} +void nistype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_NIS_VNSRL: { + SStream_concat(ss, "vnsrl.wi"); + break; + } + case RISCV_NIS_VNSRA: { + SStream_concat(ss, "vnsra.wi"); + break; + } + } +} +void nitype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_NI_VNCLIPU: { + SStream_concat(ss, "vnclipu.wi"); + break; + } + case RISCV_NI_VNCLIP: { + SStream_concat(ss, "vnclip.wi"); + break; + } + } +} +void visg_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VI_VRGATHER: { + SStream_concat(ss, "vrgather.vi"); + break; + } + case RISCV_VI_VSLIDEDOWN: { + SStream_concat(ss, "vslidedown.vi"); + break; + } + case RISCV_VI_VSLIDEUP: { + SStream_concat(ss, "vslideup.vi"); + break; + } + } +} +void simm_string(uint64_t member, SStream *ss) { + switch (member) { + case 0x01: { + SStream_concat(ss, "2"); + break; + } + case 0x07: { + SStream_concat(ss, "8"); + break; + } + case 0x00: { + SStream_concat(ss, "1"); + break; + } + case 0x03: { + SStream_concat(ss, "4"); + break; + } + } +} +void mvvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_MVV_VDIV: { + SStream_concat(ss, "vdiv.vv"); + break; + } + case RISCV_MVV_VREMU: { + SStream_concat(ss, "vremu.vv"); + break; + } + case RISCV_MVV_VAADDU: { + SStream_concat(ss, "vaaddu.vv"); + break; + } + case RISCV_MVV_VMULHSU: { + SStream_concat(ss, "vmulhsu.vv"); + break; + } + case RISCV_MVV_VASUB: { + SStream_concat(ss, "vasub.vv"); + break; + } + case RISCV_MVV_VMULHU: { + SStream_concat(ss, "vmulhu.vv"); + break; + } + case RISCV_MVV_VDIVU: { + SStream_concat(ss, "vdivu.vv"); + break; + } + case RISCV_MVV_VMULH: { + SStream_concat(ss, "vmulh.vv"); + break; + } + case RISCV_MVV_VAADD: { + SStream_concat(ss, "vaadd.vv"); + break; + } + case RISCV_MVV_VMUL: { + SStream_concat(ss, "vmul.vv"); + break; + } + case RISCV_MVV_VREM: { + SStream_concat(ss, "vrem.vv"); + break; + } + case RISCV_MVV_VASUBU: { + SStream_concat(ss, "vasubu.vv"); + break; + } + } +} +void mvvmatype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_MVV_VMACC: { + SStream_concat(ss, "vmacc.vv"); + break; + } + case RISCV_MVV_VNMSUB: { + SStream_concat(ss, "vnmsub.vv"); + break; + } + case RISCV_MVV_VNMSAC: { + SStream_concat(ss, "vnmsac.vv"); + break; + } + case RISCV_MVV_VMADD: { + SStream_concat(ss, "vmadd.vv"); + break; + } + } +} +void wvvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_WVV_VSUBU: { + SStream_concat(ss, "vwsubu.vv"); + break; + } + case RISCV_WVV_VWMULSU: { + SStream_concat(ss, "vwmulsu.vv"); + break; + } + case RISCV_WVV_VADD: { + SStream_concat(ss, "vwadd.vv"); + break; + } + case RISCV_WVV_VWMUL: { + SStream_concat(ss, "vwmul.vv"); + break; + } + case RISCV_WVV_VADDU: { + SStream_concat(ss, "vwaddu.vv"); + break; + } + case RISCV_WVV_VWMULU: { + SStream_concat(ss, "vwmulu.vv"); + break; + } + case RISCV_WVV_VSUB: { + SStream_concat(ss, "vwsub.vv"); + break; + } + } +} +void wvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_WV_VSUB: { + SStream_concat(ss, "vwsub.wv"); + break; + } + case RISCV_WV_VADDU: { + SStream_concat(ss, "vwaddu.wv"); + break; + } + case RISCV_WV_VSUBU: { + SStream_concat(ss, "vwsubu.wv"); + break; + } + case RISCV_WV_VADD: { + SStream_concat(ss, "vwadd.wv"); + break; + } + } +} +void wmvvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_WMVV_VWMACCU: { + SStream_concat(ss, "vwmaccu.vv"); + break; + } + case RISCV_WMVV_VWMACCSU: { + SStream_concat(ss, "vwmaccsu.vv"); + break; + } + case RISCV_WMVV_VWMACC: { + SStream_concat(ss, "vwmacc.vv"); + break; + } + } +} +void vext2type_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VEXT2_SVF2: { + SStream_concat(ss, "vsext.vf2"); + break; + } + case RISCV_VEXT2_ZVF2: { + SStream_concat(ss, "vzext.vf2"); + break; + } + } +} +void vext4type_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VEXT4_ZVF4: { + SStream_concat(ss, "vzext.vf4"); + break; + } + case RISCV_VEXT4_SVF4: { + SStream_concat(ss, "vsext.vf4"); + break; + } + } +} +void vext8type_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VEXT8_SVF8: { + SStream_concat(ss, "vsext.vf8"); + break; + } + case RISCV_VEXT8_ZVF8: { + SStream_concat(ss, "vzext.vf8"); + break; + } + } +} +void mvxtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_MVX_VMUL: { + SStream_concat(ss, "vmul.vx"); + break; + } + case RISCV_MVX_VREM: { + SStream_concat(ss, "vrem.vx"); + break; + } + case RISCV_MVX_VMULH: { + SStream_concat(ss, "vmulh.vx"); + break; + } + case RISCV_MVX_VDIV: { + SStream_concat(ss, "vdiv.vx"); + break; + } + case RISCV_MVX_VAADDU: { + SStream_concat(ss, "vaaddu.vx"); + break; + } + case RISCV_MVX_VSLIDE1DOWN: { + SStream_concat(ss, "vslide1down.vx"); + break; + } + case RISCV_MVX_VMULHSU: { + SStream_concat(ss, "vmulhsu.vx"); + break; + } + case RISCV_MVX_VSLIDE1UP: { + SStream_concat(ss, "vslide1up.vx"); + break; + } + case RISCV_MVX_VMULHU: { + SStream_concat(ss, "vmulhu.vx"); + break; + } + case RISCV_MVX_VASUBU: { + SStream_concat(ss, "vasubu.vx"); + break; + } + case RISCV_MVX_VREMU: { + SStream_concat(ss, "vremu.vx"); + break; + } + case RISCV_MVX_VDIVU: { + SStream_concat(ss, "vdivu.vx"); + break; + } + case RISCV_MVX_VAADD: { + SStream_concat(ss, "vaadd.vx"); + break; + } + case RISCV_MVX_VASUB: { + SStream_concat(ss, "vasub.vx"); + break; + } + } +} +void mvxmatype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_MVX_VNMSAC: { + SStream_concat(ss, "vnmsac.vx"); + break; + } + case RISCV_MVX_VMADD: { + SStream_concat(ss, "vmadd.vx"); + break; + } + case RISCV_MVX_VMACC: { + SStream_concat(ss, "vmacc.vx"); + break; + } + case RISCV_MVX_VNMSUB: { + SStream_concat(ss, "vnmsub.vx"); + break; + } + } +} +void wvxtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_WVX_VSUB: { + SStream_concat(ss, "vwsub.vx"); + break; + } + case RISCV_WVX_VADDU: { + SStream_concat(ss, "vwaddu.vx"); + break; + } + case RISCV_WVX_VADD: { + SStream_concat(ss, "vwadd.vx"); + break; + } + case RISCV_WVX_VSUBU: { + SStream_concat(ss, "vwsubu.vx"); + break; + } + case RISCV_WVX_VWMULSU: { + SStream_concat(ss, "vwmulsu.vx"); + break; + } + case RISCV_WVX_VWMUL: { + SStream_concat(ss, "vwmul.vx"); + break; + } + case RISCV_WVX_VWMULU: { + SStream_concat(ss, "vwmulu.vx"); + break; + } + } +} +void wxtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_WX_VSUB: { + SStream_concat(ss, "vwsub.wx"); + break; + } + case RISCV_WX_VSUBU: { + SStream_concat(ss, "vwsubu.wx"); + break; + } + case RISCV_WX_VADD: { + SStream_concat(ss, "vwadd.wx"); + break; + } + case RISCV_WX_VADDU: { + SStream_concat(ss, "vwaddu.wx"); + break; + } + } +} +void wmvxtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_WMVX_VWMACCU: { + SStream_concat(ss, "vwmaccu.vx"); + break; + } + case RISCV_WMVX_VWMACCSU: { + SStream_concat(ss, "vwmaccsu.vx"); + break; + } + case RISCV_WMVX_VWMACCUS: { + SStream_concat(ss, "vwmaccus.vx"); + break; + } + case RISCV_WMVX_VWMACC: { + SStream_concat(ss, "vwmacc.vx"); + break; + } + } +} +void fvvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FVV_VSGNJ: { + SStream_concat(ss, "vfsgnj.vv"); + break; + } + case RISCV_FVV_VMIN: { + SStream_concat(ss, "vfmin.vv"); + break; + } + case RISCV_FVV_VDIV: { + SStream_concat(ss, "vfdiv.vv"); + break; + } + case RISCV_FVV_VMAX: { + SStream_concat(ss, "vfmax.vv"); + break; + } + case RISCV_FVV_VADD: { + SStream_concat(ss, "vfadd.vv"); + break; + } + case RISCV_FVV_VSUB: { + SStream_concat(ss, "vfsub.vv"); + break; + } + case RISCV_FVV_VSGNJN: { + SStream_concat(ss, "vfsgnjn.vv"); + break; + } + case RISCV_FVV_VSGNJX: { + SStream_concat(ss, "vfsgnjx.vv"); + break; + } + case RISCV_FVV_VMUL: { + SStream_concat(ss, "vfmul.vv"); + break; + } + } +} +void fvvmatype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FVV_VNMSAC: { + SStream_concat(ss, "vfnmsac.vv"); + break; + } + case RISCV_FVV_VMACC: { + SStream_concat(ss, "vfmacc.vv"); + break; + } + case RISCV_FVV_VNMSUB: { + SStream_concat(ss, "vfnmsub.vv"); + break; + } + case RISCV_FVV_VMSAC: { + SStream_concat(ss, "vfmsac.vv"); + break; + } + case RISCV_FVV_VMADD: { + SStream_concat(ss, "vfmadd.vv"); + break; + } + case RISCV_FVV_VMSUB: { + SStream_concat(ss, "vfmsub.vv"); + break; + } + case RISCV_FVV_VNMACC: { + SStream_concat(ss, "vfnmacc.vv"); + break; + } + case RISCV_FVV_VNMADD: { + SStream_concat(ss, "vfnmadd.vv"); + break; + } + } +} +void fwvvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FWVV_VADD: { + SStream_concat(ss, "vfwadd.vv"); + break; + } + case RISCV_FWVV_VSUB: { + SStream_concat(ss, "vfwsub.vv"); + break; + } + case RISCV_FWVV_VMUL: { + SStream_concat(ss, "vfwmul.vv"); + break; + } + } +} +void fwvvmatype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FWVV_VMSAC: { + SStream_concat(ss, "vfwmsac.vv"); + break; + } + case RISCV_FWVV_VNMACC: { + SStream_concat(ss, "vfwnmacc.vv"); + break; + } + case RISCV_FWVV_VNMSAC: { + SStream_concat(ss, "vfwnmsac.vv"); + break; + } + case RISCV_FWVV_VMACC: { + SStream_concat(ss, "vfwmacc.vv"); + break; + } + } +} +void fwvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FWV_VADD: { + SStream_concat(ss, "vfwadd.wv"); + break; + } + case RISCV_FWV_VSUB: { + SStream_concat(ss, "vfwsub.wv"); + break; + } + } +} +void vfunary0_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FV_CVT_F_X: { + SStream_concat(ss, "vfcvt.f.x.v"); + break; + } + case RISCV_FV_CVT_X_F: { + SStream_concat(ss, "vfcvt.x.f.v"); + break; + } + case RISCV_FV_CVT_XU_F: { + SStream_concat(ss, "vfcvt.xu.f.v"); + break; + } + case RISCV_FV_CVT_RTZ_XU_F: { + SStream_concat(ss, "vfcvt.rtz.xu.f.v"); + break; + } + case RISCV_FV_CVT_RTZ_X_F: { + SStream_concat(ss, "vfcvt.rtz.x.f.v"); + break; + } + case RISCV_FV_CVT_F_XU: { + SStream_concat(ss, "vfcvt.f.xu.v"); + break; + } + } +} +void vfwunary0_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FWV_CVT_F_X: { + SStream_concat(ss, "vfwcvt.f.x.v"); + break; + } + case RISCV_FWV_CVT_F_XU: { + SStream_concat(ss, "vfwcvt.f.xu.v"); + break; + } + case RISCV_FWV_CVT_F_F: { + SStream_concat(ss, "vfwcvt.f.f.v"); + break; + } + case RISCV_FWV_CVT_X_F: { + SStream_concat(ss, "vfwcvt.x.f.v"); + break; + } + case RISCV_FWV_CVT_RTZ_XU_F: { + SStream_concat(ss, "vfwcvt.rtz.xu.f.v"); + break; + } + case RISCV_FWV_CVT_RTZ_X_F: { + SStream_concat(ss, "vfwcvt.rtz.x.f.v"); + break; + } + case RISCV_FWV_CVT_XU_F: { + SStream_concat(ss, "vfwcvt.xu.f.v"); + break; + } + } +} +void vfnunary0_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FNV_CVT_F_F: { + SStream_concat(ss, "vfncvt.f.f.w"); + break; + } + case RISCV_FNV_CVT_RTZ_XU_F: { + SStream_concat(ss, "vfncvt.rtz.xu.f.w"); + break; + } + case RISCV_FNV_CVT_F_XU: { + SStream_concat(ss, "vfncvt.f.xu.w"); + break; + } + case RISCV_FNV_CVT_F_X: { + SStream_concat(ss, "vfncvt.f.x.w"); + break; + } + case RISCV_FNV_CVT_RTZ_X_F: { + SStream_concat(ss, "vfncvt.rtz.x.f.w"); + break; + } + case RISCV_FNV_CVT_XU_F: { + SStream_concat(ss, "vfncvt.xu.f.w"); + break; + } + case RISCV_FNV_CVT_X_F: { + SStream_concat(ss, "vfncvt.x.f.w"); + break; + } + case RISCV_FNV_CVT_ROD_F_F: { + SStream_concat(ss, "vfncvt.rod.f.f.w"); + break; + } + } +} +void vfunary1_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FVV_VCLASS: { + SStream_concat(ss, "vfclass.v"); + break; + } + case RISCV_FVV_VREC7: { + SStream_concat(ss, "vfrec7.v"); + break; + } + case RISCV_FVV_VRSQRT7: { + SStream_concat(ss, "vfrsqrt7.v"); + break; + } + case RISCV_FVV_VSQRT: { + SStream_concat(ss, "vfsqrt.v"); + break; + } + } +} +void fvftype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VF_VMIN: { + SStream_concat(ss, "vfmin.vf"); + break; + } + case RISCV_VF_VSGNJ: { + SStream_concat(ss, "vfsgnj.vf"); + break; + } + case RISCV_VF_VSLIDE1UP: { + SStream_concat(ss, "vfslide1up.vf"); + break; + } + case RISCV_VF_VRSUB: { + SStream_concat(ss, "vfrsub.vf"); + break; + } + case RISCV_VF_VADD: { + SStream_concat(ss, "vfadd.vf"); + break; + } + case RISCV_VF_VSGNJX: { + SStream_concat(ss, "vfsgnjx.vf"); + break; + } + case RISCV_VF_VDIV: { + SStream_concat(ss, "vfdiv.vf"); + break; + } + case RISCV_VF_VSUB: { + SStream_concat(ss, "vfsub.vf"); + break; + } + case RISCV_VF_VRDIV: { + SStream_concat(ss, "vfrdiv.vf"); + break; + } + case RISCV_VF_VMUL: { + SStream_concat(ss, "vfmul.vf"); + break; + } + case RISCV_VF_VSGNJN: { + SStream_concat(ss, "vfsgnjn.vf"); + break; + } + case RISCV_VF_VMAX: { + SStream_concat(ss, "vfmax.vf"); + break; + } + case RISCV_VF_VSLIDE1DOWN: { + SStream_concat(ss, "vfslide1down.vf"); + break; + } + } +} +void fvfmatype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VF_VNMADD: { + SStream_concat(ss, "vfnmadd.vf"); + break; + } + case RISCV_VF_VMSUB: { + SStream_concat(ss, "vfmsub.vf"); + break; + } + case RISCV_VF_VMACC: { + SStream_concat(ss, "vfmacc.vf"); + break; + } + case RISCV_VF_VMADD: { + SStream_concat(ss, "vfmadd.vf"); + break; + } + case RISCV_VF_VNMSAC: { + SStream_concat(ss, "vfnmsac.vf"); + break; + } + case RISCV_VF_VMSAC: { + SStream_concat(ss, "vfmsac.vf"); + break; + } + case RISCV_VF_VNMACC: { + SStream_concat(ss, "vfnmacc.vf"); + break; + } + case RISCV_VF_VNMSUB: { + SStream_concat(ss, "vfnmsub.vf"); + break; + } + } +} +void fwvftype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FWVF_VADD: { + SStream_concat(ss, "vfwadd.vf"); + break; + } + case RISCV_FWVF_VSUB: { + SStream_concat(ss, "vfwsub.vf"); + break; + } + case RISCV_FWVF_VMUL: { + SStream_concat(ss, "vfwmul.vf"); + break; + } + } +} +void fwvfmatype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FWVF_VNMACC: { + SStream_concat(ss, "vfwnmacc.vf"); + break; + } + case RISCV_FWVF_VMACC: { + SStream_concat(ss, "vfwmacc.vf"); + break; + } + case RISCV_FWVF_VNMSAC: { + SStream_concat(ss, "vfwnmsac.vf"); + break; + } + case RISCV_FWVF_VMSAC: { + SStream_concat(ss, "vfwmsac.vf"); + break; + } + } +} +void fwftype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FWF_VSUB: { + SStream_concat(ss, "vfwsub.wf"); + break; + } + case RISCV_FWF_VADD: { + SStream_concat(ss, "vfwadd.wf"); + break; + } + } +} +void nfields_string(uint64_t member, SStream *ss) { + switch (member) { + case 0x7: { + SStream_concat(ss, "seg8"); + break; + } + case 0x5: { + SStream_concat(ss, "seg6"); + break; + } + case 0x1: { + SStream_concat(ss, "seg2"); + break; + } + case 0x3: { + SStream_concat(ss, "seg4"); + break; + } + case 0x2: { + SStream_concat(ss, "seg3"); + break; + } + case 0x4: { + SStream_concat(ss, "seg5"); + break; + } + case 0x6: { + SStream_concat(ss, "seg7"); + break; + } + case 0x0: { + SStream_concat(ss, ""); + break; + } + } +} +void vlewidth_bitsnumberstr(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VLE16: { + SStream_concat(ss, "16"); + break; + } + case RISCV_VLE32: { + SStream_concat(ss, "32"); + break; + } + case RISCV_VLE64: { + SStream_concat(ss, "64"); + break; + } + case RISCV_VLE8: { + SStream_concat(ss, "8"); + break; + } + } +} +void vmtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VLM: { + SStream_concat(ss, "vlm.v"); + break; + } + case RISCV_VSM: { + SStream_concat(ss, "vsm.v"); + break; + } + } +} +void mmtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_MM_VMANDN: { + SStream_concat(ss, "vmandn.mm"); + break; + } + case RISCV_MM_VMOR: { + SStream_concat(ss, "vmor.mm"); + break; + } + case RISCV_MM_VMXOR: { + SStream_concat(ss, "vmxor.mm"); + break; + } + case RISCV_MM_VMNOR: { + SStream_concat(ss, "vmnor.mm"); + break; + } + case RISCV_MM_VMORN: { + SStream_concat(ss, "vmorn.mm"); + break; + } + case RISCV_MM_VMAND: { + SStream_concat(ss, "vmand.mm"); + break; + } + case RISCV_MM_VMXNOR: { + SStream_concat(ss, "vmxnor.mm"); + break; + } + case RISCV_MM_VMNAND: { + SStream_concat(ss, "vmnand.mm"); + break; + } + } +} +void vvmtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VVM_VMADC: { + SStream_concat(ss, "vmadc.vvm"); + break; + } + case RISCV_VVM_VMSBC: { + SStream_concat(ss, "vmsbc.vvm"); + break; + } + } +} +void vvmctype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VVMC_VMADC: { + SStream_concat(ss, "vmadc.vv"); + break; + } + case RISCV_VVMC_VMSBC: { + SStream_concat(ss, "vmsbc.vv"); + break; + } + } +} +void vvmstype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VVMS_VSBC: { + SStream_concat(ss, "vsbc.vvm"); + break; + } + case RISCV_VVMS_VADC: { + SStream_concat(ss, "vadc.vvm"); + break; + } + } +} +void vvcmptype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VVCMP_VMSEQ: { + SStream_concat(ss, "vmseq.vv"); + break; + } + case RISCV_VVCMP_VMSLTU: { + SStream_concat(ss, "vmsltu.vv"); + break; + } + case RISCV_VVCMP_VMSLE: { + SStream_concat(ss, "vmsle.vv"); + break; + } + case RISCV_VVCMP_VMSLEU: { + SStream_concat(ss, "vmsleu.vv"); + break; + } + case RISCV_VVCMP_VMSNE: { + SStream_concat(ss, "vmsne.vv"); + break; + } + case RISCV_VVCMP_VMSLT: { + SStream_concat(ss, "vmslt.vv"); + break; + } + } +} +void vxmtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VXM_VMSBC: { + SStream_concat(ss, "vmsbc.vxm"); + break; + } + case RISCV_VXM_VMADC: { + SStream_concat(ss, "vmadc.vxm"); + break; + } + } +} +void vxmctype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VXMC_VMSBC: { + SStream_concat(ss, "vmsbc.vx"); + break; + } + case RISCV_VXMC_VMADC: { + SStream_concat(ss, "vmadc.vx"); + break; + } + } +} +void vxmstype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VXMS_VADC: { + SStream_concat(ss, "vadc.vxm"); + break; + } + case RISCV_VXMS_VSBC: { + SStream_concat(ss, "vsbc.vxm"); + break; + } + } +} +void vxcmptype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VXCMP_VMSLTU: { + SStream_concat(ss, "vmsltu.vx"); + break; + } + case RISCV_VXCMP_VMSLEU: { + SStream_concat(ss, "vmsleu.vx"); + break; + } + case RISCV_VXCMP_VMSNE: { + SStream_concat(ss, "vmsne.vx"); + break; + } + case RISCV_VXCMP_VMSGT: { + SStream_concat(ss, "vmsgt.vx"); + break; + } + case RISCV_VXCMP_VMSEQ: { + SStream_concat(ss, "vmseq.vx"); + break; + } + case RISCV_VXCMP_VMSGTU: { + SStream_concat(ss, "vmsgtu.vx"); + break; + } + case RISCV_VXCMP_VMSLT: { + SStream_concat(ss, "vmslt.vx"); + break; + } + case RISCV_VXCMP_VMSLE: { + SStream_concat(ss, "vmsle.vx"); + break; + } + } +} +void vimtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VIM_VMADC: { + SStream_concat(ss, "vmadc.vim"); + break; + } + } +} +void vimctype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VIMC_VMADC: { + SStream_concat(ss, "vmadc.vi"); + break; + } + } +} +void vimstype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VIMS_VADC: { + SStream_concat(ss, "vadc.vim"); + break; + } + } +} +void vicmptype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VICMP_VMSEQ: { + SStream_concat(ss, "vmseq.vi"); + break; + } + case RISCV_VICMP_VMSGTU: { + SStream_concat(ss, "vmsgtu.vi"); + break; + } + case RISCV_VICMP_VMSLEU: { + SStream_concat(ss, "vmsleu.vi"); + break; + } + case RISCV_VICMP_VMSLE: { + SStream_concat(ss, "vmsle.vi"); + break; + } + case RISCV_VICMP_VMSNE: { + SStream_concat(ss, "vmsne.vi"); + break; + } + case RISCV_VICMP_VMSGT: { + SStream_concat(ss, "vmsgt.vi"); + break; + } + } +} +void fvvmtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FVVM_VMFNE: { + SStream_concat(ss, "vmfne.vv"); + break; + } + case RISCV_FVVM_VMFEQ: { + SStream_concat(ss, "vmfeq.vv"); + break; + } + case RISCV_FVVM_VMFLT: { + SStream_concat(ss, "vmflt.vv"); + break; + } + case RISCV_FVVM_VMFLE: { + SStream_concat(ss, "vmfle.vv"); + break; + } + } +} +void fvfmtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_VFM_VMFNE: { + SStream_concat(ss, "vmfne.vf"); + break; + } + case RISCV_VFM_VMFGT: { + SStream_concat(ss, "vmfgt.vf"); + break; + } + case RISCV_VFM_VMFLT: { + SStream_concat(ss, "vmflt.vf"); + break; + } + case RISCV_VFM_VMFEQ: { + SStream_concat(ss, "vmfeq.vf"); + break; + } + case RISCV_VFM_VMFLE: { + SStream_concat(ss, "vmfle.vf"); + break; + } + case RISCV_VFM_VMFGE: { + SStream_concat(ss, "vmfge.vf"); + break; + } + } +} +void rivvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_IVV_VWREDSUMU: { + SStream_concat(ss, "vwredsumu.vs"); + break; + } + case RISCV_IVV_VWREDSUM: { + SStream_concat(ss, "vwredsum.vs"); + break; + } + } +} +void rmvvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_MVV_VREDAND: { + SStream_concat(ss, "vredand.vs"); + break; + } + case RISCV_MVV_VREDXOR: { + SStream_concat(ss, "vredxor.vs"); + break; + } + case RISCV_MVV_VREDOR: { + SStream_concat(ss, "vredor.vs"); + break; + } + case RISCV_MVV_VREDMIN: { + SStream_concat(ss, "vredmin.vs"); + break; + } + case RISCV_MVV_VREDMAXU: { + SStream_concat(ss, "vredmaxu.vs"); + break; + } + case RISCV_MVV_VREDMINU: { + SStream_concat(ss, "vredminu.vs"); + break; + } + case RISCV_MVV_VREDSUM: { + SStream_concat(ss, "vredsum.vs"); + break; + } + case RISCV_MVV_VREDMAX: { + SStream_concat(ss, "vredmax.vs"); + break; + } + } +} +void rfvvtype_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_FVV_VFWREDOSUM: { + SStream_concat(ss, "vfwredosum.vs"); + break; + } + case RISCV_FVV_VFREDOSUM: { + SStream_concat(ss, "vfredosum.vs"); + break; + } + case RISCV_FVV_VFREDUSUM: { + SStream_concat(ss, "vfredusum.vs"); + break; + } + case RISCV_FVV_VFREDMIN: { + SStream_concat(ss, "vfredmin.vs"); + break; + } + case RISCV_FVV_VFWREDUSUM: { + SStream_concat(ss, "vfwredusum.vs"); + break; + } + case RISCV_FVV_VFREDMAX: { + SStream_concat(ss, "vfredmax.vs"); + break; + } + } +} +void cbop_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_CBO_INVAL: { + SStream_concat(ss, "cbo.inval"); + break; + } + case RISCV_CBO_CLEAN: { + SStream_concat(ss, "cbo.clean"); + break; + } + case RISCV_CBO_FLUSH: { + SStream_concat(ss, "cbo.flush"); + break; + } + } +} +void vsha2c_mnemonic(uint64_t member, SStream *ss) { + switch (member) { + case RISCV_ZVK_VSHA2CH: { + SStream_concat(ss, "vsha2ch.vv"); + break; + } + case RISCV_ZVK_VSHA2CL: { + SStream_concat(ss, "vsha2cl.vv"); + break; + } + } +} +#endif diff --git a/arch/RISCV/RISCVBaseInfo.h b/arch/RISCV/RISCVBaseInfo.h deleted file mode 100644 index e6ae1fcb57..0000000000 --- a/arch/RISCV/RISCVBaseInfo.h +++ /dev/null @@ -1,106 +0,0 @@ -//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains small standalone enum definitions for the RISCV target -// useful for the compiler back-end and the MC libraries. -// -//===----------------------------------------------------------------------===// -#ifndef CS_RISCVBASEINFO_H -#define CS_RISCVBASEINFO_H -#include "../../cs_priv.h" - -//#include "RISCVMCTargetDesc.h" - -// RISCVII - This namespace holds all of the target specific flags that -// instruction info tracks. All definitions must match RISCVInstrFormats.td. -enum { - IRISCVII_InstFormatPseudo = 0, - IRISCVII_InstFormatR = 1, - IRISCVII_InstFormatR4 = 2, - IRISCVII_InstFormatI = 3, - IRISCVII_InstFormatS = 4, - IRISCVII_InstFormatB = 5, - IRISCVII_InstFormatU = 6, - IRISCVII_InstFormatJ = 7, - IRISCVII_InstFormatCR = 8, - IRISCVII_InstFormatCI = 9, - IRISCVII_InstFormatCSS = 10, - IRISCVII_InstFormatCIW = 11, - IRISCVII_InstFormatCL = 12, - IRISCVII_InstFormatCS = 13, - IRISCVII_InstFormatCA = 14, - IRISCVII_InstFormatCB = 15, - IRISCVII_InstFormatCJ = 16, - IRISCVII_InstFormatOther = 17, - - IRISCVII_InstFormatMask = 31 -}; - -enum { - RISCVII_MO_None, - RISCVII_MO_LO, - RISCVII_MO_HI, - RISCVII_MO_PCREL_HI, -}; - -// Describes the predecessor/successor bits used in the FENCE instruction. -enum FenceField { - RISCVFenceField_I = 8, - RISCVFenceField_O = 4, - RISCVFenceField_R = 2, - RISCVFenceField_W = 1 -}; - -// Describes the supported floating point rounding mode encodings. -enum RoundingMode { - RISCVFPRndMode_RNE = 0, - RISCVFPRndMode_RTZ = 1, - RISCVFPRndMode_RDN = 2, - RISCVFPRndMode_RUP = 3, - RISCVFPRndMode_RMM = 4, - RISCVFPRndMode_DYN = 7, - RISCVFPRndMode_Invalid -}; - -inline static const char *roundingModeToString(enum RoundingMode RndMode) -{ - switch (RndMode) { - default: - CS_ASSERT(0 && "Unknown floating point rounding mode"); - case RISCVFPRndMode_RNE: - return "rne"; - case RISCVFPRndMode_RTZ: - return "rtz"; - case RISCVFPRndMode_RDN: - return "rdn"; - case RISCVFPRndMode_RUP: - return "rup"; - case RISCVFPRndMode_RMM: - return "rmm"; - case RISCVFPRndMode_DYN: - return "dyn"; - } -} - -inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode) -{ - switch (Mode) { - default: - return false; - case RISCVFPRndMode_RNE: - case RISCVFPRndMode_RTZ: - case RISCVFPRndMode_RDN: - case RISCVFPRndMode_RUP: - case RISCVFPRndMode_RMM: - case RISCVFPRndMode_DYN: - return true; - } -} - -#endif diff --git a/arch/RISCV/RISCVDecode.gen.inc b/arch/RISCV/RISCVDecode.gen.inc new file mode 100644 index 0000000000..2d7d6c1faf --- /dev/null +++ b/arch/RISCV/RISCVDecode.gen.inc @@ -0,0 +1,9946 @@ +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ + +#ifndef __RISCVDECODE_GEN_INC__ +#define __RISCVDECODE_GEN_INC__ +#include +#include +#include + +#include "RISCVAst.gen.inc" +#include "RISCVDecodeHelpers.h" + +#define SLICE_BITVEC(v, s, e) ((v >> s) & ((((uint64_t)1) << (e - s + 1)) - 1)) + +#define INDEX_BITVEC(v, i) ((v >> i) & 1) + +static void decode(struct ast *tree, uint64_t binary_stream, RVContext *ctx) { + //----------------------------UTYPE------------------------------// + { + uint64_t op = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 0, 6)) { + case 0x37: + op = RISCV_LUI; + break; + case 0x17: + op = RISCV_AUIPC; + break; + } + if (op != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t imm = SLICE_BITVEC(binary_stream, 12, 31); + tree->ast_node_type = RISCV_UTYPE; + tree->ast_node.utype.imm = imm; + tree->ast_node.utype.rd = rd; + tree->ast_node.utype.op = op; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_JAL------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x6F) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t imm_7_0 = SLICE_BITVEC(binary_stream, 12, 19); + uint64_t imm_8 = SLICE_BITVEC(binary_stream, 20, 20); + uint64_t imm_12_9 = SLICE_BITVEC(binary_stream, 21, 24); + uint64_t imm_18_13 = SLICE_BITVEC(binary_stream, 25, 30); + uint64_t imm_19 = SLICE_BITVEC(binary_stream, 31, 31); + tree->ast_node_type = RISCV_JAL; + tree->ast_node.riscv_jal.imm = (imm_19 << 23) | (imm_7_0 << 15) | + (imm_8 << 14) | (imm_18_13 << 8) | + (imm_12_9 << 4) | 0x0; + tree->ast_node.riscv_jal.rd = rd; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_JALR------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x67 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t imm = SLICE_BITVEC(binary_stream, 20, 31); + tree->ast_node_type = RISCV_JALR; + tree->ast_node.riscv_jalr.imm = imm; + tree->ast_node.riscv_jalr.rs1 = rs1; + tree->ast_node.riscv_jalr.rd = rd; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------BTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x63) { + uint64_t op = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + op = RISCV_BGEU; + break; + case 0x5: + op = RISCV_BGE; + break; + case 0x1: + op = RISCV_BNE; + break; + case 0x4: + op = RISCV_BLT; + break; + case 0x6: + op = RISCV_BLTU; + break; + case 0x0: + op = RISCV_BEQ; + break; + } + if (op != 0xFFFFFFFFFFFFFFFF) { + uint64_t imm5_0 = SLICE_BITVEC(binary_stream, 7, 7); + uint64_t imm5_4_1 = SLICE_BITVEC(binary_stream, 8, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t imm7_5_0 = SLICE_BITVEC(binary_stream, 25, 30); + uint64_t imm7_6 = SLICE_BITVEC(binary_stream, 31, 31); + tree->ast_node_type = RISCV_BTYPE; + tree->ast_node.btype.imm = (imm7_6 << 15) | (imm5_0 << 14) | + (imm7_5_0 << 8) | (imm5_4_1 << 4) | 0x0; + tree->ast_node.btype.rs2 = rs2; + tree->ast_node.btype.rs1 = rs1; + tree->ast_node.btype.op = op; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ITYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13) { + uint64_t op = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + op = RISCV_ANDI; + break; + case 0x3: + op = RISCV_SLTIU; + break; + case 0x2: + op = RISCV_SLTI; + break; + case 0x6: + op = RISCV_ORI; + break; + case 0x4: + op = RISCV_XORI; + break; + case 0x0: + op = RISCV_ADDI; + break; + } + if (op != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t imm = SLICE_BITVEC(binary_stream, 20, 31); + tree->ast_node_type = RISCV_ITYPE; + tree->ast_node.itype.imm = imm; + tree->ast_node.itype.rs1 = rs1; + tree->ast_node.itype.rd = rd; + tree->ast_node.itype.op = op; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHIFTIOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if ((ctx->xlen == 64) || (INDEX_BITVEC(shamt, 5) == 0)) { + tree->ast_node_type = RISCV_SHIFTIOP; + tree->ast_node.shiftiop.shamt = shamt; + tree->ast_node.shiftiop.rs1 = rs1; + tree->ast_node.shiftiop.rd = rd; + tree->ast_node.shiftiop.op = RISCV_SLLI; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHIFTIOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if ((ctx->xlen == 64) || (INDEX_BITVEC(shamt, 5) == 0)) { + tree->ast_node_type = RISCV_SHIFTIOP; + tree->ast_node.shiftiop.shamt = shamt; + tree->ast_node.shiftiop.rs1 = rs1; + tree->ast_node.shiftiop.rd = rd; + tree->ast_node.shiftiop.op = RISCV_SRLI; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHIFTIOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if ((ctx->xlen == 64) || (INDEX_BITVEC(shamt, 5) == 0)) { + tree->ast_node_type = RISCV_SHIFTIOP; + tree->ast_node.shiftiop.shamt = shamt; + tree->ast_node.shiftiop.rs1 = rs1; + tree->ast_node.shiftiop.rd = rd; + tree->ast_node.shiftiop.op = RISCV_SRAI; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_ADD; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_SLT; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_SLTU; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x7 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_AND; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_OR; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_XOR; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_SLL; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_SRL; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_SUB; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_RTYPE; + tree->ast_node.rtype.rs2 = rs2; + tree->ast_node.rtype.rs1 = rs1; + tree->ast_node.rtype.rd = rd; + tree->ast_node.rtype.op = RISCV_SRA; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------LOAD------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x03) { + uint64_t size = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 13)) { + case 0x1: + size = RISCV_HALF; + break; + case 0x3: + size = RISCV_DOUBLE; + break; + case 0x2: + size = RISCV_WORD; + break; + case 0x0: + size = RISCV_BYTE; + break; + } + if (size != 0xFFFFFFFFFFFFFFFF) { + uint64_t is_unsigned = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 14, 14)) { + case 0x1: + is_unsigned = RISCV_true; + break; + case 0x0: + is_unsigned = RISCV_false; + break; + } + if (is_unsigned != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t imm = SLICE_BITVEC(binary_stream, 20, 31); + if ((size_bytes_forwards(size, ctx) < ctx->xlen_bytes) || + ((not(is_unsigned, ctx)) && + (size_bytes_forwards(size, ctx) <= ctx->xlen_bytes))) { + tree->ast_node_type = RISCV_LOAD; + tree->ast_node.load.imm = imm; + tree->ast_node.load.rs1 = rs1; + tree->ast_node.load.rd = rd; + tree->ast_node.load.is_unsigned = is_unsigned; + tree->ast_node.load.width = size; + tree->ast_node.load.aq = 0; + tree->ast_node.load.rl = 0; + return; + } + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------STORE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x23 && + SLICE_BITVEC(binary_stream, 14, 14) == 0x0) { + uint64_t size = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 13)) { + case 0x1: + size = RISCV_HALF; + break; + case 0x3: + size = RISCV_DOUBLE; + break; + case 0x2: + size = RISCV_WORD; + break; + case 0x0: + size = RISCV_BYTE; + break; + } + if (size != 0xFFFFFFFFFFFFFFFF) { + uint64_t imm5 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t imm7 = SLICE_BITVEC(binary_stream, 25, 31); + if (size_bytes_forwards(size, ctx) <= ctx->xlen_bytes) { + tree->ast_node_type = RISCV_STORE; + tree->ast_node.store.imm = (imm7 << 5) | imm5; + tree->ast_node.store.rs2 = rs2; + tree->ast_node.store.rs1 = rs1; + tree->ast_node.store.width = size; + tree->ast_node.store.aq = 0; + tree->ast_node.store.rl = 0; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ADDIW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t imm = SLICE_BITVEC(binary_stream, 20, 31); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_ADDIW; + tree->ast_node.addiw.imm = imm; + tree->ast_node.addiw.rs1 = rs1; + tree->ast_node.addiw.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPEW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_RTYPEW; + tree->ast_node.rtypew.rs2 = rs2; + tree->ast_node.rtypew.rs1 = rs1; + tree->ast_node.rtypew.rd = rd; + tree->ast_node.rtypew.op = RISCV_ADDW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPEW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_RTYPEW; + tree->ast_node.rtypew.rs2 = rs2; + tree->ast_node.rtypew.rs1 = rs1; + tree->ast_node.rtypew.rd = rd; + tree->ast_node.rtypew.op = RISCV_SUBW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPEW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_RTYPEW; + tree->ast_node.rtypew.rs2 = rs2; + tree->ast_node.rtypew.rs1 = rs1; + tree->ast_node.rtypew.rd = rd; + tree->ast_node.rtypew.op = RISCV_SLLW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPEW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_RTYPEW; + tree->ast_node.rtypew.rs2 = rs2; + tree->ast_node.rtypew.rs1 = rs1; + tree->ast_node.rtypew.rd = rd; + tree->ast_node.rtypew.op = RISCV_SRLW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RTYPEW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_RTYPEW; + tree->ast_node.rtypew.rs2 = rs2; + tree->ast_node.rtypew.rs1 = rs1; + tree->ast_node.rtypew.rd = rd; + tree->ast_node.rtypew.op = RISCV_SRAW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHIFTIWOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 24); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_SHIFTIWOP; + tree->ast_node.shiftiwop.shamt = shamt; + tree->ast_node.shiftiwop.rs1 = rs1; + tree->ast_node.shiftiwop.rd = rd; + tree->ast_node.shiftiwop.op = RISCV_SLLIW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHIFTIWOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 24); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_SHIFTIWOP; + tree->ast_node.shiftiwop.shamt = shamt; + tree->ast_node.shiftiwop.rs1 = rs1; + tree->ast_node.shiftiwop.rd = rd; + tree->ast_node.shiftiwop.op = RISCV_SRLIW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHIFTIWOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 24); + if (ctx->xlen == 64) { + tree->ast_node_type = RISCV_SHIFTIWOP; + tree->ast_node.shiftiwop.shamt = shamt; + tree->ast_node.shiftiwop.rs1 = rs1; + tree->ast_node.shiftiwop.rd = rd; + tree->ast_node.shiftiwop.op = RISCV_SRAIW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FENCE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x0F && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 28, 31) == 0x0) { + uint64_t succ = SLICE_BITVEC(binary_stream, 20, 23); + uint64_t pred = SLICE_BITVEC(binary_stream, 24, 27); + tree->ast_node_type = RISCV_FENCE; + tree->ast_node.fence.pred = pred; + tree->ast_node.fence.succ = succ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------FENCE_TSO------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x0F && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 28, 31) == 0x8) { + uint64_t succ = SLICE_BITVEC(binary_stream, 20, 23); + uint64_t pred = SLICE_BITVEC(binary_stream, 24, 27); + tree->ast_node_type = RISCV_FENCE_TSO; + tree->ast_node.fence_tso.pred = pred; + tree->ast_node.fence_tso.succ = succ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------ECALL------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x000) { + tree->ast_node_type = RISCV_ECALL; + ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------MRET------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x18) { + tree->ast_node_type = RISCV_MRET; + ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------SRET------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x08) { + tree->ast_node_type = RISCV_SRET; + ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------EBREAK------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x001) { + tree->ast_node_type = RISCV_EBREAK; + ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------WFI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x105) { + tree->ast_node_type = RISCV_WFI; + ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------SFENCE_VMA------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x09) { + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + tree->ast_node_type = RISCV_SFENCE_VMA; + tree->ast_node.sfence_vma.rs1 = rs1; + tree->ast_node.sfence_vma.rs2 = rs2; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------FENCEI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x0F && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x000) { + if (currentlyEnabled(RISCV_Ext_Zifencei, ctx)) { + tree->ast_node_type = RISCV_FENCEI; + ; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------LOADRES------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x2F && + SLICE_BITVEC(binary_stream, 14, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 27, 31) == 0x02) { + uint64_t size = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 13)) { + case 0x1: + size = RISCV_HALF; + break; + case 0x3: + size = RISCV_DOUBLE; + break; + case 0x2: + size = RISCV_WORD; + break; + case 0x0: + size = RISCV_BYTE; + break; + } + if (size != 0xFFFFFFFFFFFFFFFF) { + uint64_t rl = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 25, 25)) { + case 0x1: + rl = RISCV_true; + break; + case 0x0: + rl = RISCV_false; + break; + } + if (rl != 0xFFFFFFFFFFFFFFFF) { + uint64_t aq = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 26)) { + case 0x1: + aq = RISCV_true; + break; + case 0x0: + aq = RISCV_false; + break; + } + if (aq != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zalrsc, ctx)) && + (lrsc_width_valid(size, ctx))) { + tree->ast_node_type = RISCV_LOADRES; + tree->ast_node.loadres.aq = aq; + tree->ast_node.loadres.rl = rl; + tree->ast_node.loadres.rs1 = rs1; + tree->ast_node.loadres.width = size; + tree->ast_node.loadres.rd = rd; + return; + } + } + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------STORECON------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x2F && + SLICE_BITVEC(binary_stream, 14, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 27, 31) == 0x03) { + uint64_t size = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 13)) { + case 0x1: + size = RISCV_HALF; + break; + case 0x3: + size = RISCV_DOUBLE; + break; + case 0x2: + size = RISCV_WORD; + break; + case 0x0: + size = RISCV_BYTE; + break; + } + if (size != 0xFFFFFFFFFFFFFFFF) { + uint64_t rl = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 25, 25)) { + case 0x1: + rl = RISCV_true; + break; + case 0x0: + rl = RISCV_false; + break; + } + if (rl != 0xFFFFFFFFFFFFFFFF) { + uint64_t aq = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 26)) { + case 0x1: + aq = RISCV_true; + break; + case 0x0: + aq = RISCV_false; + break; + } + if (aq != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zalrsc, ctx)) && + (lrsc_width_valid(size, ctx))) { + tree->ast_node_type = RISCV_STORECON; + tree->ast_node.storecon.aq = aq; + tree->ast_node.storecon.rl = rl; + tree->ast_node.storecon.rs2 = rs2; + tree->ast_node.storecon.rs1 = rs1; + tree->ast_node.storecon.width = size; + tree->ast_node.storecon.rd = rd; + return; + } + } + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AMO------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x2F && + SLICE_BITVEC(binary_stream, 14, 14) == 0x0) { + uint64_t size = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 13)) { + case 0x1: + size = RISCV_HALF; + break; + case 0x3: + size = RISCV_DOUBLE; + break; + case 0x2: + size = RISCV_WORD; + break; + case 0x0: + size = RISCV_BYTE; + break; + } + if (size != 0xFFFFFFFFFFFFFFFF) { + uint64_t rl = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 25, 25)) { + case 0x1: + rl = RISCV_true; + break; + case 0x0: + rl = RISCV_false; + break; + } + if (rl != 0xFFFFFFFFFFFFFFFF) { + uint64_t aq = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 26)) { + case 0x1: + aq = RISCV_true; + break; + case 0x0: + aq = RISCV_false; + break; + } + if (aq != 0xFFFFFFFFFFFFFFFF) { + uint64_t op = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 27, 31)) { + case 0x08: + op = RISCV_AMOOR; + break; + case 0x01: + op = RISCV_AMOSWAP; + break; + case 0x04: + op = RISCV_AMOXOR; + break; + case 0x10: + op = RISCV_AMOMIN; + break; + case 0x1C: + op = RISCV_AMOMAXU; + break; + case 0x14: + op = RISCV_AMOMAX; + break; + case 0x00: + op = RISCV_AMOADD; + break; + case 0x0C: + op = RISCV_AMOAND; + break; + case 0x18: + op = RISCV_AMOMINU; + break; + } + if (op != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zaamo, ctx)) && + (amo_width_valid(size, ctx))) { + tree->ast_node_type = RISCV_AMO; + tree->ast_node.amo.op = op; + tree->ast_node.amo.aq = aq; + tree->ast_node.amo.rl = rl; + tree->ast_node.amo.rs2 = rs2; + tree->ast_node.amo.rs1 = rs1; + tree->ast_node.amo.width = size; + tree->ast_node.amo.rd = rd; + return; + } + } + } + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MUL------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x01) { + struct mul_op mul_op; + uint8_t mul_op_is_valid = 0; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x1: + mul_op.high = 1; + mul_op.signed_rs1 = 1; + mul_op.signed_rs2 = 1; + mul_op_is_valid = 1; + break; + case 0x3: + mul_op.high = 1; + mul_op.signed_rs1 = 0; + mul_op.signed_rs2 = 0; + mul_op_is_valid = 1; + break; + case 0x2: + mul_op.high = 1; + mul_op.signed_rs1 = 1; + mul_op.signed_rs2 = 0; + mul_op_is_valid = 1; + break; + case 0x0: + mul_op.high = 0; + mul_op.signed_rs1 = 1; + mul_op.signed_rs2 = 1; + mul_op_is_valid = 1; + break; + } + if (mul_op_is_valid == 1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_M, ctx)) || + (currentlyEnabled(RISCV_Ext_Zmmul, ctx))) { + tree->ast_node_type = RISCV_MUL; + tree->ast_node.mul.rs2 = rs2; + tree->ast_node.mul.rs1 = rs1; + tree->ast_node.mul.rd = rd; + tree->ast_node.mul.mul_op = mul_op; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------DIV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 13, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x01) { + uint64_t s = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 12)) { + case 0x1: + s = RISCV_false; + break; + case 0x0: + s = RISCV_true; + break; + } + if (s != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_M, ctx)) { + tree->ast_node_type = RISCV_DIV; + tree->ast_node.div.rs2 = rs2; + tree->ast_node.div.rs1 = rs1; + tree->ast_node.div.rd = rd; + tree->ast_node.div.s = s; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------REM------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 13, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x01) { + uint64_t s = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 12)) { + case 0x1: + s = RISCV_false; + break; + case 0x0: + s = RISCV_true; + break; + } + if (s != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_M, ctx)) { + tree->ast_node_type = RISCV_REM; + tree->ast_node.rem.rs2 = rs2; + tree->ast_node.rem.rs1 = rs1; + tree->ast_node.rem.rd = rd; + tree->ast_node.rem.s = s; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MULW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x01) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((ctx->xlen == 64) && ((currentlyEnabled(RISCV_Ext_M, ctx)) || + (currentlyEnabled(RISCV_Ext_Zmmul, ctx)))) { + tree->ast_node_type = RISCV_MULW; + tree->ast_node.mulw.rs2 = rs2; + tree->ast_node.mulw.rs1 = rs1; + tree->ast_node.mulw.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------DIVW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 13, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x01) { + uint64_t s = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 12)) { + case 0x1: + s = RISCV_false; + break; + case 0x0: + s = RISCV_true; + break; + } + if (s != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_M, ctx))) { + tree->ast_node_type = RISCV_DIVW; + tree->ast_node.divw.rs2 = rs2; + tree->ast_node.divw.rs1 = rs1; + tree->ast_node.divw.rd = rd; + tree->ast_node.divw.s = s; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------REMW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 13, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x01) { + uint64_t s = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 12)) { + case 0x1: + s = RISCV_false; + break; + case 0x0: + s = RISCV_true; + break; + } + if (s != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_M, ctx))) { + tree->ast_node_type = RISCV_REMW; + tree->ast_node.remw.rs2 = rs2; + tree->ast_node.remw.rs1 = rs1; + tree->ast_node.remw.rd = rd; + tree->ast_node.remw.s = s; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------CSRReg------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 14, 14) == 0x0) { + uint64_t op = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 13)) { + case 0x1: + op = RISCV_CSRRW; + break; + case 0x3: + op = RISCV_CSRRC; + break; + case 0x2: + op = RISCV_CSRRS; + break; + } + if (op != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t csr = SLICE_BITVEC(binary_stream, 20, 31); + tree->ast_node_type = RISCV_CSRReg; + tree->ast_node.csrreg.csr = csr; + tree->ast_node.csrreg.rs1 = rs1; + tree->ast_node.csrreg.rd = rd; + tree->ast_node.csrreg.op = op; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------CSRImm------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 14, 14) == 0x1) { + uint64_t op = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 13)) { + case 0x1: + op = RISCV_CSRRW; + break; + case 0x3: + op = RISCV_CSRRC; + break; + case 0x2: + op = RISCV_CSRRS; + break; + } + if (op != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t imm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t csr = SLICE_BITVEC(binary_stream, 20, 31); + tree->ast_node_type = RISCV_CSRImm; + tree->ast_node.csrimm.csr = csr; + tree->ast_node.csrimm.imm = imm; + tree->ast_node.csrimm.rd = rd; + tree->ast_node.csrimm.op = op; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FENCE_RESERVED------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x0F && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t succ = SLICE_BITVEC(binary_stream, 20, 23); + uint64_t pred = SLICE_BITVEC(binary_stream, 24, 27); + uint64_t fm = SLICE_BITVEC(binary_stream, 28, 31); + if (((!(fm == 0x0)) && (!(fm == 0x8))) || + ((!(rs == ctx->zreg)) || (!(rd == ctx->zreg)))) { + tree->ast_node_type = RISCV_FENCE_RESERVED; + tree->ast_node.fence_reserved.fm = fm; + tree->ast_node.fence_reserved.pred = pred; + tree->ast_node.fence_reserved.succ = succ; + tree->ast_node.fence_reserved.rs = rs; + tree->ast_node.fence_reserved.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FENCEI_RESERVED------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x0F && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t imm = SLICE_BITVEC(binary_stream, 20, 31); + if ((!(imm == 0x000)) || ((!(rs == ctx->zreg)) || (!(rd == ctx->zreg)))) { + tree->ast_node_type = RISCV_FENCEI_RESERVED; + tree->ast_node.fencei_reserved.imm = imm; + tree->ast_node.fencei_reserved.rs = rs; + tree->ast_node.fencei_reserved.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------LOAD_FP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t imm = SLICE_BITVEC(binary_stream, 20, 31); + if (currentlyEnabled(RISCV_Ext_Zfhmin, ctx)) { + tree->ast_node_type = RISCV_LOAD_FP; + tree->ast_node.load_fp.imm = imm; + tree->ast_node.load_fp.rs1 = rs1; + tree->ast_node.load_fp.rd = rd; + tree->ast_node.load_fp.width = RISCV_HALF; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------LOAD_FP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t imm = SLICE_BITVEC(binary_stream, 20, 31); + if (currentlyEnabled(RISCV_Ext_F, ctx)) { + tree->ast_node_type = RISCV_LOAD_FP; + tree->ast_node.load_fp.imm = imm; + tree->ast_node.load_fp.rs1 = rs1; + tree->ast_node.load_fp.rd = rd; + tree->ast_node.load_fp.width = RISCV_WORD; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------LOAD_FP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t imm = SLICE_BITVEC(binary_stream, 20, 31); + if (currentlyEnabled(RISCV_Ext_D, ctx)) { + tree->ast_node_type = RISCV_LOAD_FP; + tree->ast_node.load_fp.imm = imm; + tree->ast_node.load_fp.rs1 = rs1; + tree->ast_node.load_fp.rd = rd; + tree->ast_node.load_fp.width = RISCV_DOUBLE; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------STORE_FP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x27 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t imm5 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t imm7 = SLICE_BITVEC(binary_stream, 25, 31); + if (currentlyEnabled(RISCV_Ext_Zfhmin, ctx)) { + tree->ast_node_type = RISCV_STORE_FP; + tree->ast_node.store_fp.imm = (imm7 << 5) | imm5; + tree->ast_node.store_fp.rs2 = rs2; + tree->ast_node.store_fp.rs1 = rs1; + tree->ast_node.store_fp.width = RISCV_HALF; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------STORE_FP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x27 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t imm5 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t imm7 = SLICE_BITVEC(binary_stream, 25, 31); + if (currentlyEnabled(RISCV_Ext_F, ctx)) { + tree->ast_node_type = RISCV_STORE_FP; + tree->ast_node.store_fp.imm = (imm7 << 5) | imm5; + tree->ast_node.store_fp.rs2 = rs2; + tree->ast_node.store_fp.rs1 = rs1; + tree->ast_node.store_fp.width = RISCV_WORD; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------STORE_FP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x27 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3) { + uint64_t imm5 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t imm7 = SLICE_BITVEC(binary_stream, 25, 31); + if (currentlyEnabled(RISCV_Ext_D, ctx)) { + tree->ast_node_type = RISCV_STORE_FP; + tree->ast_node.store_fp.imm = (imm7 << 5) | imm5; + tree->ast_node.store_fp.rs2 = rs2; + tree->ast_node.store_fp.rs1 = rs1; + tree->ast_node.store_fp.width = RISCV_DOUBLE; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x43 && + SLICE_BITVEC(binary_stream, 25, 26) == 0x0) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_MADD_TYPE_S; + tree->ast_node.f_madd_type_s.rs3 = rs3; + tree->ast_node.f_madd_type_s.rs2 = rs2; + tree->ast_node.f_madd_type_s.rs1 = rs1; + tree->ast_node.f_madd_type_s.rm = rm; + tree->ast_node.f_madd_type_s.rd = rd; + tree->ast_node.f_madd_type_s.op = RISCV_FMADD_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x47 && + SLICE_BITVEC(binary_stream, 25, 26) == 0x0) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_MADD_TYPE_S; + tree->ast_node.f_madd_type_s.rs3 = rs3; + tree->ast_node.f_madd_type_s.rs2 = rs2; + tree->ast_node.f_madd_type_s.rs1 = rs1; + tree->ast_node.f_madd_type_s.rm = rm; + tree->ast_node.f_madd_type_s.rd = rd; + tree->ast_node.f_madd_type_s.op = RISCV_FMSUB_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x4B && + SLICE_BITVEC(binary_stream, 25, 26) == 0x0) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_MADD_TYPE_S; + tree->ast_node.f_madd_type_s.rs3 = rs3; + tree->ast_node.f_madd_type_s.rs2 = rs2; + tree->ast_node.f_madd_type_s.rs1 = rs1; + tree->ast_node.f_madd_type_s.rm = rm; + tree->ast_node.f_madd_type_s.rd = rd; + tree->ast_node.f_madd_type_s.op = RISCV_FNMSUB_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x4F && + SLICE_BITVEC(binary_stream, 25, 26) == 0x0) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_MADD_TYPE_S; + tree->ast_node.f_madd_type_s.rs3 = rs3; + tree->ast_node.f_madd_type_s.rs2 = rs2; + tree->ast_node.f_madd_type_s.rs1 = rs1; + tree->ast_node.f_madd_type_s.rm = rm; + tree->ast_node.f_madd_type_s.rd = rd; + tree->ast_node.f_madd_type_s.op = RISCV_FNMADD_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x00) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_S; + tree->ast_node.f_bin_rm_type_s.rs2 = rs2; + tree->ast_node.f_bin_rm_type_s.rs1 = rs1; + tree->ast_node.f_bin_rm_type_s.rm = rm; + tree->ast_node.f_bin_rm_type_s.rd = rd; + tree->ast_node.f_bin_rm_type_s.op = RISCV_FADD_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x04) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_S; + tree->ast_node.f_bin_rm_type_s.rs2 = rs2; + tree->ast_node.f_bin_rm_type_s.rs1 = rs1; + tree->ast_node.f_bin_rm_type_s.rm = rm; + tree->ast_node.f_bin_rm_type_s.rd = rd; + tree->ast_node.f_bin_rm_type_s.op = RISCV_FSUB_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x08) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_S; + tree->ast_node.f_bin_rm_type_s.rs2 = rs2; + tree->ast_node.f_bin_rm_type_s.rs1 = rs1; + tree->ast_node.f_bin_rm_type_s.rm = rm; + tree->ast_node.f_bin_rm_type_s.rd = rd; + tree->ast_node.f_bin_rm_type_s.op = RISCV_FMUL_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x0C) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_S; + tree->ast_node.f_bin_rm_type_s.rs2 = rs2; + tree->ast_node.f_bin_rm_type_s.rs1 = rs1; + tree->ast_node.f_bin_rm_type_s.rm = rm; + tree->ast_node.f_bin_rm_type_s.rd = rd; + tree->ast_node.f_bin_rm_type_s.op = RISCV_FDIV_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x2C) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_S; + tree->ast_node.f_un_rm_ff_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_s.rm = rm; + tree->ast_node.f_un_rm_ff_type_s.rd = rd; + tree->ast_node.f_un_rm_ff_type_s.fsqrt_s = RISCV_FSQRT_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x60) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_S; + tree->ast_node.f_un_rm_fx_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_s.rm = rm; + tree->ast_node.f_un_rm_fx_type_s.rd = rd; + tree->ast_node.f_un_rm_fx_type_s.fcvt_lu_s = RISCV_FCVT_W_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x60) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_S; + tree->ast_node.f_un_rm_fx_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_s.rm = rm; + tree->ast_node.f_un_rm_fx_type_s.rd = rd; + tree->ast_node.f_un_rm_fx_type_s.fcvt_lu_s = RISCV_FCVT_WU_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x68) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_S; + tree->ast_node.f_un_rm_xf_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_s.rm = rm; + tree->ast_node.f_un_rm_xf_type_s.rd = rd; + tree->ast_node.f_un_rm_xf_type_s.fcvt_s_lu = RISCV_FCVT_S_W; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x68) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_S; + tree->ast_node.f_un_rm_xf_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_s.rm = rm; + tree->ast_node.f_un_rm_xf_type_s.rd = rd; + tree->ast_node.f_un_rm_xf_type_s.fcvt_s_lu = RISCV_FCVT_S_WU; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x60) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveSingleFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_S; + tree->ast_node.f_un_rm_fx_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_s.rm = rm; + tree->ast_node.f_un_rm_fx_type_s.rd = rd; + tree->ast_node.f_un_rm_fx_type_s.fcvt_lu_s = RISCV_FCVT_L_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x03 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x60) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveSingleFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_S; + tree->ast_node.f_un_rm_fx_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_s.rm = rm; + tree->ast_node.f_un_rm_fx_type_s.rd = rd; + tree->ast_node.f_un_rm_fx_type_s.fcvt_lu_s = RISCV_FCVT_LU_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x68) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveSingleFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_S; + tree->ast_node.f_un_rm_xf_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_s.rm = rm; + tree->ast_node.f_un_rm_xf_type_s.rd = rd; + tree->ast_node.f_un_rm_xf_type_s.fcvt_s_lu = RISCV_FCVT_S_L; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x03 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x68) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveSingleFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_S; + tree->ast_node.f_un_rm_xf_type_s.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_s.rm = rm; + tree->ast_node.f_un_rm_xf_type_s.rd = rd; + tree->ast_node.f_un_rm_xf_type_s.fcvt_s_lu = RISCV_FCVT_S_LU; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_TYPE_F_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_TYPE_F_S; + tree->ast_node.f_bin_type_f_s.rs2 = rs2; + tree->ast_node.f_bin_type_f_s.rs1 = rs1; + tree->ast_node.f_bin_type_f_s.rd = rd; + tree->ast_node.f_bin_type_f_s.fmax_s = RISCV_FSGNJ_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_TYPE_F_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_TYPE_F_S; + tree->ast_node.f_bin_type_f_s.rs2 = rs2; + tree->ast_node.f_bin_type_f_s.rs1 = rs1; + tree->ast_node.f_bin_type_f_s.rd = rd; + tree->ast_node.f_bin_type_f_s.fmax_s = RISCV_FSGNJN_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_TYPE_F_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_TYPE_F_S; + tree->ast_node.f_bin_type_f_s.rs2 = rs2; + tree->ast_node.f_bin_type_f_s.rs1 = rs1; + tree->ast_node.f_bin_type_f_s.rd = rd; + tree->ast_node.f_bin_type_f_s.fmax_s = RISCV_FSGNJX_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_TYPE_F_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x14) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_TYPE_F_S; + tree->ast_node.f_bin_type_f_s.rs2 = rs2; + tree->ast_node.f_bin_type_f_s.rs1 = rs1; + tree->ast_node.f_bin_type_f_s.rd = rd; + tree->ast_node.f_bin_type_f_s.fmax_s = RISCV_FMIN_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_TYPE_F_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x14) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_TYPE_F_S; + tree->ast_node.f_bin_type_f_s.rs2 = rs2; + tree->ast_node.f_bin_type_f_s.rs1 = rs1; + tree->ast_node.f_bin_type_f_s.rd = rd; + tree->ast_node.f_bin_type_f_s.fmax_s = RISCV_FMAX_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_TYPE_X_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x50) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_TYPE_X_S; + tree->ast_node.f_bin_type_x_s.rs2 = rs2; + tree->ast_node.f_bin_type_x_s.rs1 = rs1; + tree->ast_node.f_bin_type_x_s.rd = rd; + tree->ast_node.f_bin_type_x_s.fle_s = RISCV_FEQ_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_TYPE_X_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x50) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_TYPE_X_S; + tree->ast_node.f_bin_type_x_s.rs2 = rs2; + tree->ast_node.f_bin_type_x_s.rs1 = rs1; + tree->ast_node.f_bin_type_x_s.rd = rd; + tree->ast_node.f_bin_type_x_s.fle_s = RISCV_FLT_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_TYPE_X_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x50) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_TYPE_X_S; + tree->ast_node.f_bin_type_x_s.rs2 = rs2; + tree->ast_node.f_bin_type_x_s.rs1 = rs1; + tree->ast_node.f_bin_type_x_s.rd = rd; + tree->ast_node.f_bin_type_x_s.fle_s = RISCV_FLE_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_TYPE_X_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x70) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveSingleFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_TYPE_X_S; + tree->ast_node.f_un_type_x_s.rs1 = rs1; + tree->ast_node.f_un_type_x_s.rd = rd; + tree->ast_node.f_un_type_x_s.fmv_x_w = RISCV_FCLASS_S; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_TYPE_X_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x70) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_F, ctx)) { + tree->ast_node_type = RISCV_F_UN_TYPE_X_S; + tree->ast_node.f_un_type_x_s.rs1 = rs1; + tree->ast_node.f_un_type_x_s.rd = rd; + tree->ast_node.f_un_type_x_s.fmv_x_w = RISCV_FMV_X_W; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_TYPE_F_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x78) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_F, ctx)) { + tree->ast_node_type = RISCV_F_UN_TYPE_F_S; + tree->ast_node.f_un_type_f_s.rs1 = rs1; + tree->ast_node.f_un_type_f_s.rd = rd; + tree->ast_node.f_un_type_f_s.fmv_w_x = RISCV_FMV_W_X; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x43 && + SLICE_BITVEC(binary_stream, 25, 26) == 0x1) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if ((haveDoubleFPU(ctx)) && + (validDoubleRegs(4, rs3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_MADD_TYPE_D; + tree->ast_node.f_madd_type_d.rs3 = rs3; + tree->ast_node.f_madd_type_d.rs2 = rs2; + tree->ast_node.f_madd_type_d.rs1 = rs1; + tree->ast_node.f_madd_type_d.rm = rm; + tree->ast_node.f_madd_type_d.rd = rd; + tree->ast_node.f_madd_type_d.op = RISCV_FMADD_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x47 && + SLICE_BITVEC(binary_stream, 25, 26) == 0x1) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if ((haveDoubleFPU(ctx)) && + (validDoubleRegs(4, rs3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_MADD_TYPE_D; + tree->ast_node.f_madd_type_d.rs3 = rs3; + tree->ast_node.f_madd_type_d.rs2 = rs2; + tree->ast_node.f_madd_type_d.rs1 = rs1; + tree->ast_node.f_madd_type_d.rm = rm; + tree->ast_node.f_madd_type_d.rd = rd; + tree->ast_node.f_madd_type_d.op = RISCV_FMSUB_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x4B && + SLICE_BITVEC(binary_stream, 25, 26) == 0x1) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if ((haveDoubleFPU(ctx)) && + (validDoubleRegs(4, rs3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_MADD_TYPE_D; + tree->ast_node.f_madd_type_d.rs3 = rs3; + tree->ast_node.f_madd_type_d.rs2 = rs2; + tree->ast_node.f_madd_type_d.rs1 = rs1; + tree->ast_node.f_madd_type_d.rm = rm; + tree->ast_node.f_madd_type_d.rd = rd; + tree->ast_node.f_madd_type_d.op = RISCV_FNMSUB_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x4F && + SLICE_BITVEC(binary_stream, 25, 26) == 0x1) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if ((haveDoubleFPU(ctx)) && + (validDoubleRegs(4, rs3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_MADD_TYPE_D; + tree->ast_node.f_madd_type_d.rs3 = rs3; + tree->ast_node.f_madd_type_d.rs2 = rs2; + tree->ast_node.f_madd_type_d.rs1 = rs1; + tree->ast_node.f_madd_type_d.rm = rm; + tree->ast_node.f_madd_type_d.rd = rd; + tree->ast_node.f_madd_type_d.op = RISCV_FNMADD_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x01) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_D; + tree->ast_node.f_bin_rm_type_d.rs2 = rs2; + tree->ast_node.f_bin_rm_type_d.rs1 = rs1; + tree->ast_node.f_bin_rm_type_d.rm = rm; + tree->ast_node.f_bin_rm_type_d.rd = rd; + tree->ast_node.f_bin_rm_type_d.op = RISCV_FADD_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x05) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_D; + tree->ast_node.f_bin_rm_type_d.rs2 = rs2; + tree->ast_node.f_bin_rm_type_d.rs1 = rs1; + tree->ast_node.f_bin_rm_type_d.rm = rm; + tree->ast_node.f_bin_rm_type_d.rd = rd; + tree->ast_node.f_bin_rm_type_d.op = RISCV_FSUB_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x09) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_D; + tree->ast_node.f_bin_rm_type_d.rs2 = rs2; + tree->ast_node.f_bin_rm_type_d.rs1 = rs1; + tree->ast_node.f_bin_rm_type_d.rm = rm; + tree->ast_node.f_bin_rm_type_d.rd = rd; + tree->ast_node.f_bin_rm_type_d.op = RISCV_FMUL_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x0D) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_D; + tree->ast_node.f_bin_rm_type_d.rs2 = rs2; + tree->ast_node.f_bin_rm_type_d.rs1 = rs1; + tree->ast_node.f_bin_rm_type_d.rm = rm; + tree->ast_node.f_bin_rm_type_d.rd = rd; + tree->ast_node.f_bin_rm_type_d.op = RISCV_FDIV_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x2D) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_D; + tree->ast_node.f_un_rm_ff_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_d.rm = rm; + tree->ast_node.f_un_rm_ff_type_d.rd = rd; + tree->ast_node.f_un_rm_ff_type_d.fcvt_d_s = RISCV_FSQRT_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x61) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rs1, ctx))) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_D; + tree->ast_node.f_un_rm_fx_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_d.rm = rm; + tree->ast_node.f_un_rm_fx_type_d.rd = rd; + tree->ast_node.f_un_rm_fx_type_d.fcvt_lu_d = RISCV_FCVT_W_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x61) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rs1, ctx))) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_D; + tree->ast_node.f_un_rm_fx_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_d.rm = rm; + tree->ast_node.f_un_rm_fx_type_d.rd = rd; + tree->ast_node.f_un_rm_fx_type_d.fcvt_lu_d = RISCV_FCVT_WU_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x69) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rd, ctx))) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_D; + tree->ast_node.f_un_rm_xf_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_d.rm = rm; + tree->ast_node.f_un_rm_xf_type_d.rd = rd; + tree->ast_node.f_un_rm_xf_type_d.fcvt_d_lu = RISCV_FCVT_D_W; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x69) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rd, ctx))) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_D; + tree->ast_node.f_un_rm_xf_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_d.rm = rm; + tree->ast_node.f_un_rm_xf_type_d.rd = rd; + tree->ast_node.f_un_rm_xf_type_d.fcvt_d_lu = RISCV_FCVT_D_WU; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rs1, ctx))) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_D; + tree->ast_node.f_un_rm_ff_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_d.rm = rm; + tree->ast_node.f_un_rm_ff_type_d.rd = rd; + tree->ast_node.f_un_rm_ff_type_d.fcvt_d_s = RISCV_FCVT_S_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x21) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rd, ctx))) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_D; + tree->ast_node.f_un_rm_ff_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_d.rm = rm; + tree->ast_node.f_un_rm_ff_type_d.rd = rd; + tree->ast_node.f_un_rm_ff_type_d.fcvt_d_s = RISCV_FCVT_D_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x61) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_D; + tree->ast_node.f_un_rm_fx_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_d.rm = rm; + tree->ast_node.f_un_rm_fx_type_d.rd = rd; + tree->ast_node.f_un_rm_fx_type_d.fcvt_lu_d = RISCV_FCVT_L_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x03 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x61) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_D; + tree->ast_node.f_un_rm_fx_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_d.rm = rm; + tree->ast_node.f_un_rm_fx_type_d.rd = rd; + tree->ast_node.f_un_rm_fx_type_d.fcvt_lu_d = RISCV_FCVT_LU_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x69) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_D; + tree->ast_node.f_un_rm_xf_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_d.rm = rm; + tree->ast_node.f_un_rm_xf_type_d.rd = rd; + tree->ast_node.f_un_rm_xf_type_d.fcvt_d_lu = RISCV_FCVT_D_L; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x03 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x69) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_D; + tree->ast_node.f_un_rm_xf_type_d.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_d.rm = rm; + tree->ast_node.f_un_rm_xf_type_d.rd = rd; + tree->ast_node.f_un_rm_xf_type_d.fcvt_d_lu = RISCV_FCVT_D_LU; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x11) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_D; + tree->ast_node.f_bin_f_type_d.rs2 = rs2; + tree->ast_node.f_bin_f_type_d.rs1 = rs1; + tree->ast_node.f_bin_f_type_d.rd = rd; + tree->ast_node.f_bin_f_type_d.fmax_d = RISCV_FSGNJ_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x11) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_D; + tree->ast_node.f_bin_f_type_d.rs2 = rs2; + tree->ast_node.f_bin_f_type_d.rs1 = rs1; + tree->ast_node.f_bin_f_type_d.rd = rd; + tree->ast_node.f_bin_f_type_d.fmax_d = RISCV_FSGNJN_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x11) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_D; + tree->ast_node.f_bin_f_type_d.rs2 = rs2; + tree->ast_node.f_bin_f_type_d.rs1 = rs1; + tree->ast_node.f_bin_f_type_d.rd = rd; + tree->ast_node.f_bin_f_type_d.fmax_d = RISCV_FSGNJX_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x15) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_D; + tree->ast_node.f_bin_f_type_d.rs2 = rs2; + tree->ast_node.f_bin_f_type_d.rs1 = rs1; + tree->ast_node.f_bin_f_type_d.rd = rd; + tree->ast_node.f_bin_f_type_d.fmax_d = RISCV_FMIN_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x15) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(3, rs2, rs1, rd, ctx))) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_D; + tree->ast_node.f_bin_f_type_d.rs2 = rs2; + tree->ast_node.f_bin_f_type_d.rs1 = rs1; + tree->ast_node.f_bin_f_type_d.rd = rd; + tree->ast_node.f_bin_f_type_d.fmax_d = RISCV_FMAX_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_X_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x51) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(2, rs2, rs1, ctx))) { + tree->ast_node_type = RISCV_F_BIN_X_TYPE_D; + tree->ast_node.f_bin_x_type_d.rs2 = rs2; + tree->ast_node.f_bin_x_type_d.rs1 = rs1; + tree->ast_node.f_bin_x_type_d.rd = rd; + tree->ast_node.f_bin_x_type_d.fle_d = RISCV_FEQ_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_X_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x51) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(2, rs2, rs1, ctx))) { + tree->ast_node_type = RISCV_F_BIN_X_TYPE_D; + tree->ast_node.f_bin_x_type_d.rs2 = rs2; + tree->ast_node.f_bin_x_type_d.rs1 = rs1; + tree->ast_node.f_bin_x_type_d.rd = rd; + tree->ast_node.f_bin_x_type_d.fle_d = RISCV_FLT_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_X_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x51) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(2, rs2, rs1, ctx))) { + tree->ast_node_type = RISCV_F_BIN_X_TYPE_D; + tree->ast_node.f_bin_x_type_d.rs2 = rs2; + tree->ast_node.f_bin_x_type_d.rs1 = rs1; + tree->ast_node.f_bin_x_type_d.rd = rd; + tree->ast_node.f_bin_x_type_d.fle_d = RISCV_FLE_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_X_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x71) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rs1, ctx))) { + tree->ast_node_type = RISCV_F_UN_X_TYPE_D; + tree->ast_node.f_un_x_type_d.rs1 = rs1; + tree->ast_node.f_un_x_type_d.rd = rd; + tree->ast_node.f_un_x_type_d.fmv_x_d = RISCV_FCLASS_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_X_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x71) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_X_TYPE_D; + tree->ast_node.f_un_x_type_d.rs1 = rs1; + tree->ast_node.f_un_x_type_d.rd = rd; + tree->ast_node.f_un_x_type_d.fmv_x_d = RISCV_FMV_X_D; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_F_TYPE_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x79) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_F_TYPE_D; + tree->ast_node.f_un_f_type_d.rs1 = rs1; + tree->ast_node.f_un_f_type_d.rd = rd; + tree->ast_node.f_un_f_type_d.fmv_d_x = RISCV_FMV_D_X; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SINVAL_VMA------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x0B) { + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Svinval, ctx)) { + tree->ast_node_type = RISCV_SINVAL_VMA; + tree->ast_node.sinval_vma.rs1 = rs1; + tree->ast_node.sinval_vma.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SFENCE_W_INVAL------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x0C) { + if (currentlyEnabled(RISCV_Ext_Svinval, ctx)) { + tree->ast_node_type = RISCV_SFENCE_W_INVAL; + ; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SFENCE_INVAL_IR------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x0C) { + if (currentlyEnabled(RISCV_Ext_Svinval, ctx)) { + tree->ast_node_type = RISCV_SFENCE_INVAL_IR; + ; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_SLLIUW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x02) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if ((currentlyEnabled(RISCV_Ext_Zba, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_SLLIUW; + tree->ast_node.riscv_slliuw.shamt = shamt; + tree->ast_node.riscv_slliuw.rs1 = rs1; + tree->ast_node.riscv_slliuw.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBA_RTYPEUW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x04) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zba, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_ZBA_RTYPEUW; + tree->ast_node.zba_rtypeuw.rs2 = rs2; + tree->ast_node.zba_rtypeuw.rs1 = rs1; + tree->ast_node.zba_rtypeuw.rd = rd; + tree->ast_node.zba_rtypeuw.op = RISCV_ADDUW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBA_RTYPEUW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zba, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_ZBA_RTYPEUW; + tree->ast_node.zba_rtypeuw.rs2 = rs2; + tree->ast_node.zba_rtypeuw.rs1 = rs1; + tree->ast_node.zba_rtypeuw.rd = rd; + tree->ast_node.zba_rtypeuw.op = RISCV_SH1ADDUW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBA_RTYPEUW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zba, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_ZBA_RTYPEUW; + tree->ast_node.zba_rtypeuw.rs2 = rs2; + tree->ast_node.zba_rtypeuw.rs1 = rs1; + tree->ast_node.zba_rtypeuw.rd = rd; + tree->ast_node.zba_rtypeuw.op = RISCV_SH2ADDUW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBA_RTYPEUW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zba, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_ZBA_RTYPEUW; + tree->ast_node.zba_rtypeuw.rs2 = rs2; + tree->ast_node.zba_rtypeuw.rs1 = rs1; + tree->ast_node.zba_rtypeuw.rd = rd; + tree->ast_node.zba_rtypeuw.op = RISCV_SH3ADDUW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBA_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zba, ctx)) { + tree->ast_node_type = RISCV_ZBA_RTYPE; + tree->ast_node.zba_rtype.rs2 = rs2; + tree->ast_node.zba_rtype.rs1 = rs1; + tree->ast_node.zba_rtype.rd = rd; + tree->ast_node.zba_rtype.op = RISCV_SH1ADD; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBA_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zba, ctx)) { + tree->ast_node_type = RISCV_ZBA_RTYPE; + tree->ast_node.zba_rtype.rs2 = rs2; + tree->ast_node.zba_rtype.rs1 = rs1; + tree->ast_node.zba_rtype.rd = rd; + tree->ast_node.zba_rtype.op = RISCV_SH2ADD; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBA_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zba, ctx)) { + tree->ast_node_type = RISCV_ZBA_RTYPE; + tree->ast_node.zba_rtype.rs2 = rs2; + tree->ast_node.zba_rtype.rs1 = rs1; + tree->ast_node.zba_rtype.rd = rd; + tree->ast_node.zba_rtype.op = RISCV_SH3ADD; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_RORIW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x30) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 24); + if (((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) && + (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_RORIW; + tree->ast_node.riscv_roriw.shamt = shamt; + tree->ast_node.riscv_roriw.rs1 = rs1; + tree->ast_node.riscv_roriw.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_RORI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x18) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if (((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) && + ((ctx->xlen == 64) || (INDEX_BITVEC(shamt, 5) == 0))) { + tree->ast_node_type = RISCV_RORI; + tree->ast_node.riscv_rori.shamt = shamt; + tree->ast_node.riscv_rori.rs1 = rs1; + tree->ast_node.riscv_rori.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPEW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x30) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) && + (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_ZBB_RTYPEW; + tree->ast_node.zbb_rtypew.rs2 = rs2; + tree->ast_node.zbb_rtypew.rs1 = rs1; + tree->ast_node.zbb_rtypew.rd = rd; + tree->ast_node.zbb_rtypew.op = RISCV_ROLW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPEW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x30) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) && + (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_ZBB_RTYPEW; + tree->ast_node.zbb_rtypew.rs2 = rs2; + tree->ast_node.zbb_rtypew.rs1 = rs1; + tree->ast_node.zbb_rtypew.rd = rd; + tree->ast_node.zbb_rtypew.op = RISCV_RORW; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x7 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_ANDN; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_ORN; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_XNOR; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x05) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_MAX; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x7 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x05) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_MAXU; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x05) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_MIN; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x05) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_MINU; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x30) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_ROL; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x30) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) { + tree->ast_node_type = RISCV_ZBB_RTYPE; + tree->ast_node.zbb_rtype.rs2 = rs2; + tree->ast_node.zbb_rtype.rs1 = rs1; + tree->ast_node.zbb_rtype.rd = rd; + tree->ast_node.zbb_rtype.op = RISCV_ROR; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_EXTOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x04 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x30) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_ZBB_EXTOP; + tree->ast_node.zbb_extop.rs1 = rs1; + tree->ast_node.zbb_extop.rd = rd; + tree->ast_node.zbb_extop.op = RISCV_SEXTB; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_EXTOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x05 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x30) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_ZBB_EXTOP; + tree->ast_node.zbb_extop.rs1 = rs1; + tree->ast_node.zbb_extop.rd = rd; + tree->ast_node.zbb_extop.op = RISCV_SEXTH; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_EXTOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x04) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_ZBB_EXTOP; + tree->ast_node.zbb_extop.rs1 = rs1; + tree->ast_node.zbb_extop.rd = rd; + tree->ast_node.zbb_extop.op = RISCV_ZEXTH; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBB_EXTOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x04) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_ZBB_EXTOP; + tree->ast_node.zbb_extop.rs1 = rs1; + tree->ast_node.zbb_extop.rd = rd; + tree->ast_node.zbb_extop.op = RISCV_ZEXTH; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_REV8------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x698) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) && + (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_REV8; + tree->ast_node.riscv_rev8.rs1 = rs1; + tree->ast_node.riscv_rev8.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_REV8------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x6B8) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (((currentlyEnabled(RISCV_Ext_Zbb, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkb, ctx))) && + (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_REV8; + tree->ast_node.riscv_rev8.rs1 = rs1; + tree->ast_node.riscv_rev8.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_ORCB------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x287) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_ORCB; + tree->ast_node.riscv_orcb.rs1 = rs1; + tree->ast_node.riscv_orcb.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CPOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x602) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_CPOP; + tree->ast_node.riscv_cpop.rs1 = rs1; + tree->ast_node.riscv_cpop.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CPOPW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x602) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_CPOPW; + tree->ast_node.riscv_cpopw.rs1 = rs1; + tree->ast_node.riscv_cpopw.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CLZ------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x600) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_CLZ; + tree->ast_node.riscv_clz.rs1 = rs1; + tree->ast_node.riscv_clz.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CLZW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x600) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_CLZW; + tree->ast_node.riscv_clzw.rs1 = rs1; + tree->ast_node.riscv_clzw.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CTZ------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x601) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zbb, ctx)) { + tree->ast_node_type = RISCV_CTZ; + tree->ast_node.riscv_ctz.rs1 = rs1; + tree->ast_node.riscv_ctz.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CTZW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x1B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x601) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zbb, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_CTZW; + tree->ast_node.riscv_ctzw.rs1 = rs1; + tree->ast_node.riscv_ctzw.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CLMUL------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x05) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zbc, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkc, ctx))) { + tree->ast_node_type = RISCV_CLMUL; + tree->ast_node.riscv_clmul.rs2 = rs2; + tree->ast_node.riscv_clmul.rs1 = rs1; + tree->ast_node.riscv_clmul.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CLMULH------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x05) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zbc, ctx)) || + (currentlyEnabled(RISCV_Ext_Zbkc, ctx))) { + tree->ast_node_type = RISCV_CLMULH; + tree->ast_node.riscv_clmulh.rs2 = rs2; + tree->ast_node.riscv_clmulh.rs1 = rs1; + tree->ast_node.riscv_clmulh.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_CLMULR------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x05) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbc, ctx)) { + tree->ast_node_type = RISCV_CLMULR; + tree->ast_node.riscv_clmulr.rs2 = rs2; + tree->ast_node.riscv_clmulr.rs1 = rs1; + tree->ast_node.riscv_clmulr.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBS_IOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if ((currentlyEnabled(RISCV_Ext_Zbs, ctx)) && + ((ctx->xlen == 64) || (INDEX_BITVEC(shamt, 5) == 0))) { + tree->ast_node_type = RISCV_ZBS_IOP; + tree->ast_node.zbs_iop.shamt = shamt; + tree->ast_node.zbs_iop.rs1 = rs1; + tree->ast_node.zbs_iop.rd = rd; + tree->ast_node.zbs_iop.op = RISCV_BCLRI; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBS_IOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if ((currentlyEnabled(RISCV_Ext_Zbs, ctx)) && + ((ctx->xlen == 64) || (INDEX_BITVEC(shamt, 5) == 0))) { + tree->ast_node_type = RISCV_ZBS_IOP; + tree->ast_node.zbs_iop.shamt = shamt; + tree->ast_node.zbs_iop.rs1 = rs1; + tree->ast_node.zbs_iop.rd = rd; + tree->ast_node.zbs_iop.op = RISCV_BEXTI; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBS_IOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x1A) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if ((currentlyEnabled(RISCV_Ext_Zbs, ctx)) && + ((ctx->xlen == 64) || (INDEX_BITVEC(shamt, 5) == 0))) { + tree->ast_node_type = RISCV_ZBS_IOP; + tree->ast_node.zbs_iop.shamt = shamt; + tree->ast_node.zbs_iop.rs1 = rs1; + tree->ast_node.zbs_iop.rd = rd; + tree->ast_node.zbs_iop.op = RISCV_BINVI; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBS_IOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x0A) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t shamt = SLICE_BITVEC(binary_stream, 20, 25); + if ((currentlyEnabled(RISCV_Ext_Zbs, ctx)) && + ((ctx->xlen == 64) || (INDEX_BITVEC(shamt, 5) == 0))) { + tree->ast_node_type = RISCV_ZBS_IOP; + tree->ast_node.zbs_iop.shamt = shamt; + tree->ast_node.zbs_iop.rs1 = rs1; + tree->ast_node.zbs_iop.rd = rd; + tree->ast_node.zbs_iop.op = RISCV_BSETI; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBS_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x24) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbs, ctx)) { + tree->ast_node_type = RISCV_ZBS_RTYPE; + tree->ast_node.zbs_rtype.rs2 = rs2; + tree->ast_node.zbs_rtype.rs1 = rs1; + tree->ast_node.zbs_rtype.rd = rd; + tree->ast_node.zbs_rtype.op = RISCV_BCLR; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBS_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x24) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbs, ctx)) { + tree->ast_node_type = RISCV_ZBS_RTYPE; + tree->ast_node.zbs_rtype.rs2 = rs2; + tree->ast_node.zbs_rtype.rs1 = rs1; + tree->ast_node.zbs_rtype.rd = rd; + tree->ast_node.zbs_rtype.op = RISCV_BEXT; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBS_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x34) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbs, ctx)) { + tree->ast_node_type = RISCV_ZBS_RTYPE; + tree->ast_node.zbs_rtype.rs2 = rs2; + tree->ast_node.zbs_rtype.rs1 = rs1; + tree->ast_node.zbs_rtype.rd = rd; + tree->ast_node.zbs_rtype.op = RISCV_BINV; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBS_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x14) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbs, ctx)) { + tree->ast_node_type = RISCV_ZBS_RTYPE; + tree->ast_node.zbs_rtype.rs2 = rs2; + tree->ast_node.zbs_rtype.rs1 = rs1; + tree->ast_node.zbs_rtype.rd = rd; + tree->ast_node.zbs_rtype.op = RISCV_BSET; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x02) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_H; + tree->ast_node.f_bin_rm_type_h.rs2 = rs2; + tree->ast_node.f_bin_rm_type_h.rs1 = rs1; + tree->ast_node.f_bin_rm_type_h.rm = rm; + tree->ast_node.f_bin_rm_type_h.rd = rd; + tree->ast_node.f_bin_rm_type_h.op = RISCV_FADD_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x06) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_H; + tree->ast_node.f_bin_rm_type_h.rs2 = rs2; + tree->ast_node.f_bin_rm_type_h.rs1 = rs1; + tree->ast_node.f_bin_rm_type_h.rm = rm; + tree->ast_node.f_bin_rm_type_h.rd = rd; + tree->ast_node.f_bin_rm_type_h.op = RISCV_FSUB_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x0A) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_H; + tree->ast_node.f_bin_rm_type_h.rs2 = rs2; + tree->ast_node.f_bin_rm_type_h.rs1 = rs1; + tree->ast_node.f_bin_rm_type_h.rm = rm; + tree->ast_node.f_bin_rm_type_h.rd = rd; + tree->ast_node.f_bin_rm_type_h.op = RISCV_FMUL_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_RM_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x0E) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_RM_TYPE_H; + tree->ast_node.f_bin_rm_type_h.rs2 = rs2; + tree->ast_node.f_bin_rm_type_h.rs1 = rs1; + tree->ast_node.f_bin_rm_type_h.rm = rm; + tree->ast_node.f_bin_rm_type_h.rd = rd; + tree->ast_node.f_bin_rm_type_h.op = RISCV_FDIV_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x43 && + SLICE_BITVEC(binary_stream, 25, 26) == 0x2) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_MADD_TYPE_H; + tree->ast_node.f_madd_type_h.rs3 = rs3; + tree->ast_node.f_madd_type_h.rs2 = rs2; + tree->ast_node.f_madd_type_h.rs1 = rs1; + tree->ast_node.f_madd_type_h.rm = rm; + tree->ast_node.f_madd_type_h.rd = rd; + tree->ast_node.f_madd_type_h.op = RISCV_FMADD_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x47 && + SLICE_BITVEC(binary_stream, 25, 26) == 0x2) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_MADD_TYPE_H; + tree->ast_node.f_madd_type_h.rs3 = rs3; + tree->ast_node.f_madd_type_h.rs2 = rs2; + tree->ast_node.f_madd_type_h.rs1 = rs1; + tree->ast_node.f_madd_type_h.rm = rm; + tree->ast_node.f_madd_type_h.rd = rd; + tree->ast_node.f_madd_type_h.op = RISCV_FMSUB_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x4B && + SLICE_BITVEC(binary_stream, 25, 26) == 0x2) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_MADD_TYPE_H; + tree->ast_node.f_madd_type_h.rs3 = rs3; + tree->ast_node.f_madd_type_h.rs2 = rs2; + tree->ast_node.f_madd_type_h.rs1 = rs1; + tree->ast_node.f_madd_type_h.rm = rm; + tree->ast_node.f_madd_type_h.rd = rd; + tree->ast_node.f_madd_type_h.op = RISCV_FNMSUB_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_MADD_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x4F && + SLICE_BITVEC(binary_stream, 25, 26) == 0x2) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t rs3 = SLICE_BITVEC(binary_stream, 27, 31); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_MADD_TYPE_H; + tree->ast_node.f_madd_type_h.rs3 = rs3; + tree->ast_node.f_madd_type_h.rs2 = rs2; + tree->ast_node.f_madd_type_h.rs1 = rs1; + tree->ast_node.f_madd_type_h.rm = rm; + tree->ast_node.f_madd_type_h.rd = rd; + tree->ast_node.f_madd_type_h.op = RISCV_FNMADD_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x12) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_H; + tree->ast_node.f_bin_f_type_h.rs2 = rs2; + tree->ast_node.f_bin_f_type_h.rs1 = rs1; + tree->ast_node.f_bin_f_type_h.rd = rd; + tree->ast_node.f_bin_f_type_h.fmax_h = RISCV_FSGNJ_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x12) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_H; + tree->ast_node.f_bin_f_type_h.rs2 = rs2; + tree->ast_node.f_bin_f_type_h.rs1 = rs1; + tree->ast_node.f_bin_f_type_h.rd = rd; + tree->ast_node.f_bin_f_type_h.fmax_h = RISCV_FSGNJN_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x12) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_H; + tree->ast_node.f_bin_f_type_h.rs2 = rs2; + tree->ast_node.f_bin_f_type_h.rs1 = rs1; + tree->ast_node.f_bin_f_type_h.rd = rd; + tree->ast_node.f_bin_f_type_h.fmax_h = RISCV_FSGNJX_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x16) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_H; + tree->ast_node.f_bin_f_type_h.rs2 = rs2; + tree->ast_node.f_bin_f_type_h.rs1 = rs1; + tree->ast_node.f_bin_f_type_h.rd = rd; + tree->ast_node.f_bin_f_type_h.fmax_h = RISCV_FMIN_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_F_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x16) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_F_TYPE_H; + tree->ast_node.f_bin_f_type_h.rs2 = rs2; + tree->ast_node.f_bin_f_type_h.rs1 = rs1; + tree->ast_node.f_bin_f_type_h.rd = rd; + tree->ast_node.f_bin_f_type_h.fmax_h = RISCV_FMAX_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_X_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x52) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_X_TYPE_H; + tree->ast_node.f_bin_x_type_h.rs2 = rs2; + tree->ast_node.f_bin_x_type_h.rs1 = rs1; + tree->ast_node.f_bin_x_type_h.rd = rd; + tree->ast_node.f_bin_x_type_h.fle_h = RISCV_FEQ_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_X_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x52) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_X_TYPE_H; + tree->ast_node.f_bin_x_type_h.rs2 = rs2; + tree->ast_node.f_bin_x_type_h.rs1 = rs1; + tree->ast_node.f_bin_x_type_h.rd = rd; + tree->ast_node.f_bin_x_type_h.fle_h = RISCV_FLT_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_BIN_X_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x52) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_BIN_X_TYPE_H; + tree->ast_node.f_bin_x_type_h.rs2 = rs2; + tree->ast_node.f_bin_x_type_h.rs1 = rs1; + tree->ast_node.f_bin_x_type_h.rd = rd; + tree->ast_node.f_bin_x_type_h.fle_h = RISCV_FLE_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x2E) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_H; + tree->ast_node.f_un_rm_ff_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_h.rm = rm; + tree->ast_node.f_un_rm_ff_type_h.rd = rd; + tree->ast_node.f_un_rm_ff_type_h.fcvt_d_h = RISCV_FSQRT_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x62) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_H; + tree->ast_node.f_un_rm_fx_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_h.rm = rm; + tree->ast_node.f_un_rm_fx_type_h.rd = rd; + tree->ast_node.f_un_rm_fx_type_h.fcvt_lu_h = RISCV_FCVT_W_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x62) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_H; + tree->ast_node.f_un_rm_fx_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_h.rm = rm; + tree->ast_node.f_un_rm_fx_type_h.rd = rd; + tree->ast_node.f_un_rm_fx_type_h.fcvt_lu_h = RISCV_FCVT_WU_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x6A) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_H; + tree->ast_node.f_un_rm_xf_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_h.rm = rm; + tree->ast_node.f_un_rm_xf_type_h.rd = rd; + tree->ast_node.f_un_rm_xf_type_h.fcvt_h_lu = RISCV_FCVT_H_W; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x6A) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_H; + tree->ast_node.f_un_rm_xf_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_h.rm = rm; + tree->ast_node.f_un_rm_xf_type_h.rd = rd; + tree->ast_node.f_un_rm_xf_type_h.fcvt_h_lu = RISCV_FCVT_H_WU; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x22) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveHalfMin(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_H; + tree->ast_node.f_un_rm_ff_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_h.rm = rm; + tree->ast_node.f_un_rm_ff_type_h.rd = rd; + tree->ast_node.f_un_rm_ff_type_h.fcvt_d_h = RISCV_FCVT_H_S; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x22) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveHalfMin(ctx)) && + ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rs1, ctx)))) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_H; + tree->ast_node.f_un_rm_ff_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_h.rm = rm; + tree->ast_node.f_un_rm_ff_type_h.rd = rd; + tree->ast_node.f_un_rm_ff_type_h.fcvt_d_h = RISCV_FCVT_H_D; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveHalfMin(ctx)) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_H; + tree->ast_node.f_un_rm_ff_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_h.rm = rm; + tree->ast_node.f_un_rm_ff_type_h.rd = rd; + tree->ast_node.f_un_rm_ff_type_h.fcvt_d_h = RISCV_FCVT_S_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x21) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveHalfMin(ctx)) && + ((haveDoubleFPU(ctx)) && (validDoubleRegs(1, rd, ctx)))) { + tree->ast_node_type = RISCV_F_UN_RM_FF_TYPE_H; + tree->ast_node.f_un_rm_ff_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_ff_type_h.rm = rm; + tree->ast_node.f_un_rm_ff_type_h.rd = rd; + tree->ast_node.f_un_rm_ff_type_h.fcvt_d_h = RISCV_FCVT_D_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x62) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveHalfFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_H; + tree->ast_node.f_un_rm_fx_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_h.rm = rm; + tree->ast_node.f_un_rm_fx_type_h.rd = rd; + tree->ast_node.f_un_rm_fx_type_h.fcvt_lu_h = RISCV_FCVT_L_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_FX_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x03 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x62) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveHalfFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_FX_TYPE_H; + tree->ast_node.f_un_rm_fx_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_fx_type_h.rm = rm; + tree->ast_node.f_un_rm_fx_type_h.rd = rd; + tree->ast_node.f_un_rm_fx_type_h.fcvt_lu_h = RISCV_FCVT_LU_H; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x6A) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveHalfFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_H; + tree->ast_node.f_un_rm_xf_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_h.rm = rm; + tree->ast_node.f_un_rm_xf_type_h.rd = rd; + tree->ast_node.f_un_rm_xf_type_h.fcvt_h_lu = RISCV_FCVT_H_L; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_RM_XF_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x03 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x6A) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((haveHalfFPU(ctx)) && (!(ctx->xlen < 64))) { + tree->ast_node_type = RISCV_F_UN_RM_XF_TYPE_H; + tree->ast_node.f_un_rm_xf_type_h.rs1 = rs1; + tree->ast_node.f_un_rm_xf_type_h.rm = rm; + tree->ast_node.f_un_rm_xf_type_h.rd = rd; + tree->ast_node.f_un_rm_xf_type_h.fcvt_h_lu = RISCV_FCVT_H_LU; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_X_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x72) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (haveHalfFPU(ctx)) { + tree->ast_node_type = RISCV_F_UN_X_TYPE_H; + tree->ast_node.f_un_x_type_h.rs1 = rs1; + tree->ast_node.f_un_x_type_h.rd = rd; + tree->ast_node.f_un_x_type_h.fmv_x_h = RISCV_FCLASS_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_X_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x72) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zfhmin, ctx)) { + tree->ast_node_type = RISCV_F_UN_X_TYPE_H; + tree->ast_node.f_un_x_type_h.rs1 = rs1; + tree->ast_node.f_un_x_type_h.rd = rd; + tree->ast_node.f_un_x_type_h.fmv_x_h = RISCV_FMV_X_H; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------F_UN_F_TYPE_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x7A) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zfhmin, ctx)) { + tree->ast_node_type = RISCV_F_UN_F_TYPE_H; + tree->ast_node.f_un_f_type_h.rs1 = rs1; + tree->ast_node.f_un_f_type_h.rd = rd; + tree->ast_node.f_un_f_type_h.fmv_h_x = RISCV_FMV_H_X; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLI_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x7A) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zfh, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FLI_H; + tree->ast_node.riscv_fli_h.constantidx = rs1; + tree->ast_node.riscv_fli_h.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLI_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x78) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zfa, ctx)) { + tree->ast_node_type = RISCV_FLI_S; + tree->ast_node.riscv_fli_s.constantidx = rs1; + tree->ast_node.riscv_fli_s.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLI_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x79) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FLI_D; + tree->ast_node.riscv_fli_d.constantidx = rs1; + tree->ast_node.riscv_fli_d.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FMINM_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x16) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zfh, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FMINM_H; + tree->ast_node.riscv_fminm_h.rs2 = rs2; + tree->ast_node.riscv_fminm_h.rs1 = rs1; + tree->ast_node.riscv_fminm_h.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FMAXM_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x16) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zfh, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FMAXM_H; + tree->ast_node.riscv_fmaxm_h.rs2 = rs2; + tree->ast_node.riscv_fmaxm_h.rs1 = rs1; + tree->ast_node.riscv_fmaxm_h.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FMINM_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x14) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zfa, ctx)) { + tree->ast_node_type = RISCV_FMINM_S; + tree->ast_node.riscv_fminm_s.rs2 = rs2; + tree->ast_node.riscv_fminm_s.rs1 = rs1; + tree->ast_node.riscv_fminm_s.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FMAXM_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x14) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zfa, ctx)) { + tree->ast_node_type = RISCV_FMAXM_S; + tree->ast_node.riscv_fmaxm_s.rs2 = rs2; + tree->ast_node.riscv_fmaxm_s.rs1 = rs1; + tree->ast_node.riscv_fmaxm_s.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FMINM_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x15) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FMINM_D; + tree->ast_node.riscv_fminm_d.rs2 = rs2; + tree->ast_node.riscv_fminm_d.rs1 = rs1; + tree->ast_node.riscv_fminm_d.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FMAXM_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x15) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FMAXM_D; + tree->ast_node.riscv_fmaxm_d.rs2 = rs2; + tree->ast_node.riscv_fmaxm_d.rs1 = rs1; + tree->ast_node.riscv_fmaxm_d.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FROUND_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x04 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x22) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zfh, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FROUND_H; + tree->ast_node.riscv_fround_h.rs1 = rs1; + tree->ast_node.riscv_fround_h.rm = rm; + tree->ast_node.riscv_fround_h.rd = rd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FROUNDNX_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x05 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x22) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zfh, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FROUNDNX_H; + tree->ast_node.riscv_froundnx_h.rs1 = rs1; + tree->ast_node.riscv_froundnx_h.rm = rm; + tree->ast_node.riscv_froundnx_h.rd = rd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FROUND_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x04 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zfa, ctx)) { + tree->ast_node_type = RISCV_FROUND_S; + tree->ast_node.riscv_fround_s.rs1 = rs1; + tree->ast_node.riscv_fround_s.rm = rm; + tree->ast_node.riscv_fround_s.rd = rd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FROUNDNX_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x05 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x20) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zfa, ctx)) { + tree->ast_node_type = RISCV_FROUNDNX_S; + tree->ast_node.riscv_froundnx_s.rs1 = rs1; + tree->ast_node.riscv_froundnx_s.rm = rm; + tree->ast_node.riscv_froundnx_s.rd = rd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FROUND_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x04 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x21) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FROUND_D; + tree->ast_node.riscv_fround_d.rs1 = rs1; + tree->ast_node.riscv_fround_d.rm = rm; + tree->ast_node.riscv_fround_d.rd = rd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FROUNDNX_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x05 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x21) { + uint64_t rm = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + rm = RISCV_RM_DYN; + break; + case 0x1: + rm = RISCV_RM_RTZ; + break; + case 0x3: + rm = RISCV_RM_RUP; + break; + case 0x2: + rm = RISCV_RM_RDN; + break; + case 0x4: + rm = RISCV_RM_RMM; + break; + case 0x0: + rm = RISCV_RM_RNE; + break; + } + if (rm != 0xFFFFFFFFFFFFFFFF) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FROUNDNX_D; + tree->ast_node.riscv_froundnx_d.rs1 = rs1; + tree->ast_node.riscv_froundnx_d.rm = rm; + tree->ast_node.riscv_froundnx_d.rd = rd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FMVH_X_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x71) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + ((currentlyEnabled(RISCV_Ext_Zfa, ctx)) && (in32BitMode(ctx)))) { + tree->ast_node_type = RISCV_FMVH_X_D; + tree->ast_node.riscv_fmvh_x_d.rs1 = rs1; + tree->ast_node.riscv_fmvh_x_d.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FMVP_D_X------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x59) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + ((currentlyEnabled(RISCV_Ext_Zfa, ctx)) && (in32BitMode(ctx)))) { + tree->ast_node_type = RISCV_FMVP_D_X; + tree->ast_node.riscv_fmvp_d_x.rs2 = rs2; + tree->ast_node.riscv_fmvp_d_x.rs1 = rs1; + tree->ast_node.riscv_fmvp_d_x.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLEQ_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x52) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zfh, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FLEQ_H; + tree->ast_node.riscv_fleq_h.rs2 = rs2; + tree->ast_node.riscv_fleq_h.rs1 = rs1; + tree->ast_node.riscv_fleq_h.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLTQ_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x52) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zfh, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FLTQ_H; + tree->ast_node.riscv_fltq_h.rs2 = rs2; + tree->ast_node.riscv_fltq_h.rs1 = rs1; + tree->ast_node.riscv_fltq_h.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLEQ_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x50) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zfa, ctx)) { + tree->ast_node_type = RISCV_FLEQ_S; + tree->ast_node.riscv_fleq_s.rs2 = rs2; + tree->ast_node.riscv_fleq_s.rs1 = rs1; + tree->ast_node.riscv_fleq_s.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLTQ_S------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x50) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zfa, ctx)) { + tree->ast_node_type = RISCV_FLTQ_S; + tree->ast_node.riscv_fltq_s.rs2 = rs2; + tree->ast_node.riscv_fltq_s.rs1 = rs1; + tree->ast_node.riscv_fltq_s.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLEQ_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x51) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FLEQ_D; + tree->ast_node.riscv_fleq_d.rs2 = rs2; + tree->ast_node.riscv_fleq_d.rs1 = rs1; + tree->ast_node.riscv_fleq_d.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FLTQ_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x51) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FLTQ_D; + tree->ast_node.riscv_fltq_d.rs2 = rs2; + tree->ast_node.riscv_fltq_d.rs1 = rs1; + tree->ast_node.riscv_fltq_d.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_FCVTMOD_W_D------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x53 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x08 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x61) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_D, ctx)) && + (currentlyEnabled(RISCV_Ext_Zfa, ctx))) { + tree->ast_node_type = RISCV_FCVTMOD_W_D; + tree->ast_node.riscv_fcvtmod_w_d.rs1 = rs1; + tree->ast_node.riscv_fcvtmod_w_d.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA256SUM0------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zknh, ctx)) { + tree->ast_node_type = RISCV_SHA256SUM0; + tree->ast_node.sha256sum0.rs1 = rs1; + tree->ast_node.sha256sum0.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA256SUM1------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x01 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zknh, ctx)) { + tree->ast_node_type = RISCV_SHA256SUM1; + tree->ast_node.sha256sum1.rs1 = rs1; + tree->ast_node.sha256sum1.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA256SIG0------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x02 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zknh, ctx)) { + tree->ast_node_type = RISCV_SHA256SIG0; + tree->ast_node.sha256sig0.rs1 = rs1; + tree->ast_node.sha256sig0.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA256SIG1------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x03 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zknh, ctx)) { + tree->ast_node_type = RISCV_SHA256SIG1; + tree->ast_node.sha256sig1.rs1 = rs1; + tree->ast_node.sha256sig1.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES32ESMI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x13) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t bs = SLICE_BITVEC(binary_stream, 30, 31); + if ((currentlyEnabled(RISCV_Ext_Zkne, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_AES32ESMI; + tree->ast_node.aes32esmi.bs = bs; + tree->ast_node.aes32esmi.rs2 = rs2; + tree->ast_node.aes32esmi.rs1 = rs1; + tree->ast_node.aes32esmi.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES32ESI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x11) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t bs = SLICE_BITVEC(binary_stream, 30, 31); + if ((currentlyEnabled(RISCV_Ext_Zkne, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_AES32ESI; + tree->ast_node.aes32esi.bs = bs; + tree->ast_node.aes32esi.rs2 = rs2; + tree->ast_node.aes32esi.rs1 = rs1; + tree->ast_node.aes32esi.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES32DSMI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x17) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t bs = SLICE_BITVEC(binary_stream, 30, 31); + if ((currentlyEnabled(RISCV_Ext_Zknd, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_AES32DSMI; + tree->ast_node.aes32dsmi.bs = bs; + tree->ast_node.aes32dsmi.rs2 = rs2; + tree->ast_node.aes32dsmi.rs1 = rs1; + tree->ast_node.aes32dsmi.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES32DSI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x15) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t bs = SLICE_BITVEC(binary_stream, 30, 31); + if ((currentlyEnabled(RISCV_Ext_Zknd, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_AES32DSI; + tree->ast_node.aes32dsi.bs = bs; + tree->ast_node.aes32dsi.rs2 = rs2; + tree->ast_node.aes32dsi.rs1 = rs1; + tree->ast_node.aes32dsi.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SUM0R------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_SHA512SUM0R; + tree->ast_node.sha512sum0r.rs2 = rs2; + tree->ast_node.sha512sum0r.rs1 = rs1; + tree->ast_node.sha512sum0r.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SUM1R------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x09 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_SHA512SUM1R; + tree->ast_node.sha512sum1r.rs2 = rs2; + tree->ast_node.sha512sum1r.rs1 = rs1; + tree->ast_node.sha512sum1r.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SIG0L------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x0A && + SLICE_BITVEC(binary_stream, 30, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_SHA512SIG0L; + tree->ast_node.sha512sig0l.rs2 = rs2; + tree->ast_node.sha512sig0l.rs1 = rs1; + tree->ast_node.sha512sig0l.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SIG0H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x0E && + SLICE_BITVEC(binary_stream, 30, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_SHA512SIG0H; + tree->ast_node.sha512sig0h.rs2 = rs2; + tree->ast_node.sha512sig0h.rs1 = rs1; + tree->ast_node.sha512sig0h.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SIG1L------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x0B && + SLICE_BITVEC(binary_stream, 30, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_SHA512SIG1L; + tree->ast_node.sha512sig1l.rs2 = rs2; + tree->ast_node.sha512sig1l.rs1 = rs1; + tree->ast_node.sha512sig1l.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SIG1H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x0F && + SLICE_BITVEC(binary_stream, 30, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_SHA512SIG1H; + tree->ast_node.sha512sig1h.rs2 = rs2; + tree->ast_node.sha512sig1h.rs1 = rs1; + tree->ast_node.sha512sig1h.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES64KS1I------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 24, 24) == 0x1 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x18 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rnum = SLICE_BITVEC(binary_stream, 20, 23); + if (((currentlyEnabled(RISCV_Ext_Zkne, ctx)) || + (currentlyEnabled(RISCV_Ext_Zknd, ctx))) && + ((ctx->xlen == 64) && (rnum < 0xB))) { + tree->ast_node_type = RISCV_AES64KS1I; + tree->ast_node.aes64ks1i.rnum = rnum; + tree->ast_node.aes64ks1i.rs1 = rs1; + tree->ast_node.aes64ks1i.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES64IM------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x18 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zknd, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_AES64IM; + tree->ast_node.aes64im.rs1 = rs1; + tree->ast_node.aes64im.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES64KS2------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x1F && + SLICE_BITVEC(binary_stream, 30, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (((currentlyEnabled(RISCV_Ext_Zkne, ctx)) || + (currentlyEnabled(RISCV_Ext_Zknd, ctx))) && + (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_AES64KS2; + tree->ast_node.aes64ks2.rs2 = rs2; + tree->ast_node.aes64ks2.rs1 = rs1; + tree->ast_node.aes64ks2.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES64ESM------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x1B && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zkne, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_AES64ESM; + tree->ast_node.aes64esm.rs2 = rs2; + tree->ast_node.aes64esm.rs1 = rs1; + tree->ast_node.aes64esm.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES64ES------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x19 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zkne, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_AES64ES; + tree->ast_node.aes64es.rs2 = rs2; + tree->ast_node.aes64es.rs1 = rs1; + tree->ast_node.aes64es.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES64DSM------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x1F && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zknd, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_AES64DSM; + tree->ast_node.aes64dsm.rs2 = rs2; + tree->ast_node.aes64dsm.rs1 = rs1; + tree->ast_node.aes64dsm.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------AES64DS------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x1D && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zknd, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_AES64DS; + tree->ast_node.aes64ds.rs2 = rs2; + tree->ast_node.aes64ds.rs1 = rs1; + tree->ast_node.aes64ds.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SUM0------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x04 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_SHA512SUM0; + tree->ast_node.sha512sum0.rs1 = rs1; + tree->ast_node.sha512sum0.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SUM1------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x05 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_SHA512SUM1; + tree->ast_node.sha512sum1.rs1 = rs1; + tree->ast_node.sha512sum1.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SIG0------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x06 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_SHA512SIG0; + tree->ast_node.sha512sig0.rs1 = rs1; + tree->ast_node.sha512sig0.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SHA512SIG1------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x07 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zknh, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_SHA512SIG1; + tree->ast_node.sha512sig1.rs1 = rs1; + tree->ast_node.sha512sig1.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SM3P0------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x08 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zksh, ctx)) { + tree->ast_node_type = RISCV_SM3P0; + tree->ast_node.sm3p0.rs1 = rs1; + tree->ast_node.sm3p0.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SM3P1------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x09 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x08 && + SLICE_BITVEC(binary_stream, 30, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zksh, ctx)) { + tree->ast_node_type = RISCV_SM3P1; + tree->ast_node.sm3p1.rs1 = rs1; + tree->ast_node.sm3p1.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SM4ED------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x18) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t bs = SLICE_BITVEC(binary_stream, 30, 31); + if (currentlyEnabled(RISCV_Ext_Zksed, ctx)) { + tree->ast_node_type = RISCV_SM4ED; + tree->ast_node.sm4ed.bs = bs; + tree->ast_node.sm4ed.rs2 = rs2; + tree->ast_node.sm4ed.rs1 = rs1; + tree->ast_node.sm4ed.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------SM4KS------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 29) == 0x1A) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t bs = SLICE_BITVEC(binary_stream, 30, 31); + if (currentlyEnabled(RISCV_Ext_Zksed, ctx)) { + tree->ast_node_type = RISCV_SM4KS; + tree->ast_node.sm4ks.bs = bs; + tree->ast_node.sm4ks.rs2 = rs2; + tree->ast_node.sm4ks.rs1 = rs1; + tree->ast_node.sm4ks.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBKB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x04) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbkb, ctx)) { + tree->ast_node_type = RISCV_ZBKB_RTYPE; + tree->ast_node.zbkb_rtype.rs2 = rs2; + tree->ast_node.zbkb_rtype.rs1 = rs1; + tree->ast_node.zbkb_rtype.rd = rd; + tree->ast_node.zbkb_rtype.op = RISCV_PACK; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBKB_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x7 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x04) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbkb, ctx)) { + tree->ast_node_type = RISCV_ZBKB_RTYPE; + tree->ast_node.zbkb_rtype.rs2 = rs2; + tree->ast_node.zbkb_rtype.rs1 = rs1; + tree->ast_node.zbkb_rtype.rd = rd; + tree->ast_node.zbkb_rtype.op = RISCV_PACKH; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZBKB_PACKW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x3B && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x04) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if ((currentlyEnabled(RISCV_Ext_Zbkb, ctx)) && (ctx->xlen == 64)) { + tree->ast_node_type = RISCV_ZBKB_PACKW; + tree->ast_node.zbkb_packw.rs2 = rs2; + tree->ast_node.zbkb_packw.rs1 = rs1; + tree->ast_node.zbkb_packw.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_ZIP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x08F) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zbkb, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_ZIP; + tree->ast_node.riscv_zip.rs1 = rs1; + tree->ast_node.riscv_zip.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_UNZIP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x08F) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if ((currentlyEnabled(RISCV_Ext_Zbkb, ctx)) && (ctx->xlen == 32)) { + tree->ast_node_type = RISCV_UNZIP; + tree->ast_node.riscv_unzip.rs1 = rs1; + tree->ast_node.riscv_unzip.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_BREV8------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x13 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x687) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zbkb, ctx)) { + tree->ast_node_type = RISCV_BREV8; + tree->ast_node.riscv_brev8.rs1 = rs1; + tree->ast_node.riscv_brev8.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_XPERM8------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x14) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbkx, ctx)) { + tree->ast_node_type = RISCV_XPERM8; + tree->ast_node.riscv_xperm8.rs2 = rs2; + tree->ast_node.riscv_xperm8.rs1 = rs1; + tree->ast_node.riscv_xperm8.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_XPERM4------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x14) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zbkx, ctx)) { + tree->ast_node_type = RISCV_XPERM4; + tree->ast_node.riscv_xperm4.rs2 = rs2; + tree->ast_node.riscv_xperm4.rs1 = rs1; + tree->ast_node.riscv_xperm4.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZICOND_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x07) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zicond, ctx)) { + tree->ast_node_type = RISCV_ZICOND_RTYPE; + tree->ast_node.zicond_rtype.rs2 = rs2; + tree->ast_node.zicond_rtype.rs1 = rs1; + tree->ast_node.zicond_rtype.rd = rd; + tree->ast_node.zicond_rtype.riscv_czero_nez = RISCV_CZERO_EQZ; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZICOND_RTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x33 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x7 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x07) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_Zicond, ctx)) { + tree->ast_node_type = RISCV_ZICOND_RTYPE; + tree->ast_node.zicond_rtype.rs2 = rs2; + tree->ast_node.zicond_rtype.rs1 = rs1; + tree->ast_node.zicond_rtype.rd = rd; + tree->ast_node.zicond_rtype.riscv_czero_nez = RISCV_CZERO_NEZ; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSETVLI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x7 && + SLICE_BITVEC(binary_stream, 28, 31) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t lmul = SLICE_BITVEC(binary_stream, 20, 22); + uint64_t sew = SLICE_BITVEC(binary_stream, 23, 25); + uint64_t ta = SLICE_BITVEC(binary_stream, 26, 26); + uint64_t ma = SLICE_BITVEC(binary_stream, 27, 27); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VSETVLI; + tree->ast_node.vsetvli.ma = ma; + tree->ast_node.vsetvli.ta = ta; + tree->ast_node.vsetvli.sew = sew; + tree->ast_node.vsetvli.lmul = lmul; + tree->ast_node.vsetvli.rs1 = rs1; + tree->ast_node.vsetvli.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSETVL------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x7 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x40) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VSETVL; + tree->ast_node.vsetvl.rs2 = rs2; + tree->ast_node.vsetvl.rs1 = rs1; + tree->ast_node.vsetvl.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSETIVLI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x7 && + SLICE_BITVEC(binary_stream, 28, 31) == 0xC) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t uimm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t lmul = SLICE_BITVEC(binary_stream, 20, 22); + uint64_t sew = SLICE_BITVEC(binary_stream, 23, 25); + uint64_t ta = SLICE_BITVEC(binary_stream, 26, 26); + uint64_t ma = SLICE_BITVEC(binary_stream, 27, 27); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VSETIVLI; + tree->ast_node.vsetivli.ma = ma; + tree->ast_node.vsetivli.ta = ta; + tree->ast_node.vsetivli.sew = sew; + tree->ast_node.vsetivli.lmul = lmul; + tree->ast_node.vsetivli.uimm = uimm; + tree->ast_node.vsetivli.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x06: + funct6 = RISCV_VV_VMAXU; + break; + case 0x25: + funct6 = RISCV_VV_VSLL; + break; + case 0x23: + funct6 = RISCV_VV_VSSUB; + break; + case 0x09: + funct6 = RISCV_VV_VAND; + break; + case 0x00: + funct6 = RISCV_VV_VADD; + break; + case 0x0A: + funct6 = RISCV_VV_VOR; + break; + case 0x0C: + funct6 = RISCV_VV_VRGATHER; + break; + case 0x2B: + funct6 = RISCV_VV_VSSRA; + break; + case 0x02: + funct6 = RISCV_VV_VSUB; + break; + case 0x20: + funct6 = RISCV_VV_VSADDU; + break; + case 0x28: + funct6 = RISCV_VV_VSRL; + break; + case 0x0B: + funct6 = RISCV_VV_VXOR; + break; + case 0x07: + funct6 = RISCV_VV_VMAX; + break; + case 0x04: + funct6 = RISCV_VV_VMINU; + break; + case 0x22: + funct6 = RISCV_VV_VSSUBU; + break; + case 0x27: + funct6 = RISCV_VV_VSMUL; + break; + case 0x0E: + funct6 = RISCV_VV_VRGATHEREI16; + break; + case 0x2A: + funct6 = RISCV_VV_VSSRL; + break; + case 0x05: + funct6 = RISCV_VV_VMIN; + break; + case 0x21: + funct6 = RISCV_VV_VSADD; + break; + case 0x29: + funct6 = RISCV_VV_VSRA; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VVTYPE; + tree->ast_node.vvtype.funct6 = funct6; + tree->ast_node.vvtype.vm = vm; + tree->ast_node.vvtype.vs2 = vs2; + tree->ast_node.vvtype.vs1 = vs1; + tree->ast_node.vvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------NVSTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2C: + funct6 = RISCV_NVS_VNSRL; + break; + case 0x2D: + funct6 = RISCV_NVS_VNSRA; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_NVSTYPE; + tree->ast_node.nvstype.funct6 = funct6; + tree->ast_node.nvstype.vm = vm; + tree->ast_node.nvstype.vs2 = vs2; + tree->ast_node.nvstype.vs1 = vs1; + tree->ast_node.nvstype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------NVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2E: + funct6 = RISCV_NV_VNCLIPU; + break; + case 0x2F: + funct6 = RISCV_NV_VNCLIP; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_NVTYPE; + tree->ast_node.nvtype.funct6 = funct6; + tree->ast_node.nvtype.vm = vm; + tree->ast_node.nvtype.vs2 = vs2; + tree->ast_node.nvtype.vs1 = vs1; + tree->ast_node.nvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MASKTYPEV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MASKTYPEV; + tree->ast_node.masktypev.vs2 = vs2; + tree->ast_node.masktypev.vs1 = vs1; + tree->ast_node.masktypev.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MOVETYPEV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MOVETYPEV; + tree->ast_node.movetypev.vs1 = vs1; + tree->ast_node.movetypev.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VXTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x06: + funct6 = RISCV_VX_VMAXU; + break; + case 0x25: + funct6 = RISCV_VX_VSLL; + break; + case 0x23: + funct6 = RISCV_VX_VSSUB; + break; + case 0x09: + funct6 = RISCV_VX_VAND; + break; + case 0x00: + funct6 = RISCV_VX_VADD; + break; + case 0x0A: + funct6 = RISCV_VX_VOR; + break; + case 0x2B: + funct6 = RISCV_VX_VSSRA; + break; + case 0x02: + funct6 = RISCV_VX_VSUB; + break; + case 0x20: + funct6 = RISCV_VX_VSADDU; + break; + case 0x28: + funct6 = RISCV_VX_VSRL; + break; + case 0x0B: + funct6 = RISCV_VX_VXOR; + break; + case 0x07: + funct6 = RISCV_VX_VMAX; + break; + case 0x04: + funct6 = RISCV_VX_VMINU; + break; + case 0x22: + funct6 = RISCV_VX_VSSUBU; + break; + case 0x27: + funct6 = RISCV_VX_VSMUL; + break; + case 0x2A: + funct6 = RISCV_VX_VSSRL; + break; + case 0x03: + funct6 = RISCV_VX_VRSUB; + break; + case 0x05: + funct6 = RISCV_VX_VMIN; + break; + case 0x21: + funct6 = RISCV_VX_VSADD; + break; + case 0x29: + funct6 = RISCV_VX_VSRA; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VXTYPE; + tree->ast_node.vxtype.funct6 = funct6; + tree->ast_node.vxtype.vm = vm; + tree->ast_node.vxtype.vs2 = vs2; + tree->ast_node.vxtype.rs1 = rs1; + tree->ast_node.vxtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------NXSTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2C: + funct6 = RISCV_NXS_VNSRL; + break; + case 0x2D: + funct6 = RISCV_NXS_VNSRA; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_NXSTYPE; + tree->ast_node.nxstype.funct6 = funct6; + tree->ast_node.nxstype.vm = vm; + tree->ast_node.nxstype.vs2 = vs2; + tree->ast_node.nxstype.rs1 = rs1; + tree->ast_node.nxstype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------NXTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2E: + funct6 = RISCV_NX_VNCLIPU; + break; + case 0x2F: + funct6 = RISCV_NX_VNCLIP; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_NXTYPE; + tree->ast_node.nxtype.funct6 = funct6; + tree->ast_node.nxtype.vm = vm; + tree->ast_node.nxtype.vs2 = vs2; + tree->ast_node.nxtype.rs1 = rs1; + tree->ast_node.nxtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VXSG------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x0E: + funct6 = RISCV_VX_VSLIDEUP; + break; + case 0x0C: + funct6 = RISCV_VX_VRGATHER; + break; + case 0x0F: + funct6 = RISCV_VX_VSLIDEDOWN; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VXSG; + tree->ast_node.vxsg.funct6 = funct6; + tree->ast_node.vxsg.vm = vm; + tree->ast_node.vxsg.vs2 = vs2; + tree->ast_node.vxsg.rs1 = rs1; + tree->ast_node.vxsg.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MASKTYPEX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MASKTYPEX; + tree->ast_node.masktypex.vs2 = vs2; + tree->ast_node.masktypex.rs1 = rs1; + tree->ast_node.masktypex.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MOVETYPEX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MOVETYPEX; + tree->ast_node.movetypex.rs1 = rs1; + tree->ast_node.movetypex.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VITYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x28: + funct6 = RISCV_VI_VSRL; + break; + case 0x0B: + funct6 = RISCV_VI_VXOR; + break; + case 0x25: + funct6 = RISCV_VI_VSLL; + break; + case 0x09: + funct6 = RISCV_VI_VAND; + break; + case 0x00: + funct6 = RISCV_VI_VADD; + break; + case 0x0A: + funct6 = RISCV_VI_VOR; + break; + case 0x2A: + funct6 = RISCV_VI_VSSRL; + break; + case 0x03: + funct6 = RISCV_VI_VRSUB; + break; + case 0x21: + funct6 = RISCV_VI_VSADD; + break; + case 0x2B: + funct6 = RISCV_VI_VSSRA; + break; + case 0x29: + funct6 = RISCV_VI_VSRA; + break; + case 0x20: + funct6 = RISCV_VI_VSADDU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VITYPE; + tree->ast_node.vitype.funct6 = funct6; + tree->ast_node.vitype.vm = vm; + tree->ast_node.vitype.vs2 = vs2; + tree->ast_node.vitype.simm = simm; + tree->ast_node.vitype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------NISTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2C: + funct6 = RISCV_NIS_VNSRL; + break; + case 0x2D: + funct6 = RISCV_NIS_VNSRA; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_NISTYPE; + tree->ast_node.nistype.funct6 = funct6; + tree->ast_node.nistype.vm = vm; + tree->ast_node.nistype.vs2 = vs2; + tree->ast_node.nistype.simm = simm; + tree->ast_node.nistype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------NITYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2E: + funct6 = RISCV_NI_VNCLIPU; + break; + case 0x2F: + funct6 = RISCV_NI_VNCLIP; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_NITYPE; + tree->ast_node.nitype.funct6 = funct6; + tree->ast_node.nitype.vm = vm; + tree->ast_node.nitype.vs2 = vs2; + tree->ast_node.nitype.simm = simm; + tree->ast_node.nitype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VISG------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x0E: + funct6 = RISCV_VI_VSLIDEUP; + break; + case 0x0C: + funct6 = RISCV_VI_VRGATHER; + break; + case 0x0F: + funct6 = RISCV_VI_VSLIDEDOWN; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VISG; + tree->ast_node.visg.funct6 = funct6; + tree->ast_node.visg.vm = vm; + tree->ast_node.visg.vs2 = vs2; + tree->ast_node.visg.simm = simm; + tree->ast_node.visg.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MASKTYPEI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MASKTYPEI; + tree->ast_node.masktypei.vs2 = vs2; + tree->ast_node.masktypei.simm = simm; + tree->ast_node.masktypei.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MOVETYPEI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MOVETYPEI; + tree->ast_node.movetypei.vd = vd; + tree->ast_node.movetypei.simm = simm; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VMVRTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x27) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VMVRTYPE; + tree->ast_node.vmvrtype.vs2 = vs2; + tree->ast_node.vmvrtype.simm = simm; + tree->ast_node.vmvrtype.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MVVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x08: + funct6 = RISCV_MVV_VAADDU; + break; + case 0x0B: + funct6 = RISCV_MVV_VASUB; + break; + case 0x25: + funct6 = RISCV_MVV_VMUL; + break; + case 0x23: + funct6 = RISCV_MVV_VREM; + break; + case 0x09: + funct6 = RISCV_MVV_VAADD; + break; + case 0x27: + funct6 = RISCV_MVV_VMULH; + break; + case 0x22: + funct6 = RISCV_MVV_VREMU; + break; + case 0x0A: + funct6 = RISCV_MVV_VASUBU; + break; + case 0x24: + funct6 = RISCV_MVV_VMULHU; + break; + case 0x26: + funct6 = RISCV_MVV_VMULHSU; + break; + case 0x21: + funct6 = RISCV_MVV_VDIV; + break; + case 0x20: + funct6 = RISCV_MVV_VDIVU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MVVTYPE; + tree->ast_node.mvvtype.funct6 = funct6; + tree->ast_node.mvvtype.vm = vm; + tree->ast_node.mvvtype.vs2 = vs2; + tree->ast_node.mvvtype.vs1 = vs1; + tree->ast_node.mvvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MVVMATYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2D: + funct6 = RISCV_MVV_VMACC; + break; + case 0x2F: + funct6 = RISCV_MVV_VNMSAC; + break; + case 0x2B: + funct6 = RISCV_MVV_VNMSUB; + break; + case 0x29: + funct6 = RISCV_MVV_VMADD; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MVVMATYPE; + tree->ast_node.mvvmatype.funct6 = funct6; + tree->ast_node.mvvmatype.vm = vm; + tree->ast_node.mvvmatype.vs2 = vs2; + tree->ast_node.mvvmatype.vs1 = vs1; + tree->ast_node.mvvmatype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------WVVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x3B: + funct6 = RISCV_WVV_VWMUL; + break; + case 0x33: + funct6 = RISCV_WVV_VSUB; + break; + case 0x3A: + funct6 = RISCV_WVV_VWMULSU; + break; + case 0x31: + funct6 = RISCV_WVV_VADD; + break; + case 0x30: + funct6 = RISCV_WVV_VADDU; + break; + case 0x32: + funct6 = RISCV_WVV_VSUBU; + break; + case 0x38: + funct6 = RISCV_WVV_VWMULU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_WVVTYPE; + tree->ast_node.wvvtype.funct6 = funct6; + tree->ast_node.wvvtype.vm = vm; + tree->ast_node.wvvtype.vs2 = vs2; + tree->ast_node.wvvtype.vs1 = vs1; + tree->ast_node.wvvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------WVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x36: + funct6 = RISCV_WV_VSUBU; + break; + case 0x35: + funct6 = RISCV_WV_VADD; + break; + case 0x37: + funct6 = RISCV_WV_VSUB; + break; + case 0x34: + funct6 = RISCV_WV_VADDU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_WVTYPE; + tree->ast_node.wvtype.funct6 = funct6; + tree->ast_node.wvtype.vm = vm; + tree->ast_node.wvtype.vs2 = vs2; + tree->ast_node.wvtype.vs1 = vs1; + tree->ast_node.wvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------WMVVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x3D: + funct6 = RISCV_WMVV_VWMACC; + break; + case 0x3C: + funct6 = RISCV_WMVV_VWMACCU; + break; + case 0x3F: + funct6 = RISCV_WMVV_VWMACCSU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_WMVVTYPE; + tree->ast_node.wmvvtype.funct6 = funct6; + tree->ast_node.wmvvtype.vm = vm; + tree->ast_node.wmvvtype.vs2 = vs2; + tree->ast_node.wmvvtype.vs1 = vs1; + tree->ast_node.wmvvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VEXT2TYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 15, 19)) { + case 0x06: + funct6 = RISCV_VEXT2_ZVF2; + break; + case 0x07: + funct6 = RISCV_VEXT2_SVF2; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VEXT2TYPE; + tree->ast_node.vext2type.funct6 = funct6; + tree->ast_node.vext2type.vm = vm; + tree->ast_node.vext2type.vs2 = vs2; + tree->ast_node.vext2type.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VEXT4TYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 15, 19)) { + case 0x04: + funct6 = RISCV_VEXT4_ZVF4; + break; + case 0x05: + funct6 = RISCV_VEXT4_SVF4; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VEXT4TYPE; + tree->ast_node.vext4type.funct6 = funct6; + tree->ast_node.vext4type.vm = vm; + tree->ast_node.vext4type.vs2 = vs2; + tree->ast_node.vext4type.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VEXT8TYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 15, 19)) { + case 0x03: + funct6 = RISCV_VEXT8_SVF8; + break; + case 0x02: + funct6 = RISCV_VEXT8_ZVF8; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VEXT8TYPE; + tree->ast_node.vext8type.funct6 = funct6; + tree->ast_node.vext8type.vm = vm; + tree->ast_node.vext8type.vs2 = vs2; + tree->ast_node.vext8type.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VMVXS------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VMVXS; + tree->ast_node.vmvxs.vs2 = vs2; + tree->ast_node.vmvxs.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MVVCOMPRESS------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MVVCOMPRESS; + tree->ast_node.mvvcompress.vs2 = vs2; + tree->ast_node.mvvcompress.vs1 = vs1; + tree->ast_node.mvvcompress.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MVXTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x08: + funct6 = RISCV_MVX_VAADDU; + break; + case 0x0B: + funct6 = RISCV_MVX_VASUB; + break; + case 0x25: + funct6 = RISCV_MVX_VMUL; + break; + case 0x23: + funct6 = RISCV_MVX_VREM; + break; + case 0x09: + funct6 = RISCV_MVX_VAADD; + break; + case 0x27: + funct6 = RISCV_MVX_VMULH; + break; + case 0x22: + funct6 = RISCV_MVX_VREMU; + break; + case 0x0A: + funct6 = RISCV_MVX_VASUBU; + break; + case 0x24: + funct6 = RISCV_MVX_VMULHU; + break; + case 0x0E: + funct6 = RISCV_MVX_VSLIDE1UP; + break; + case 0x26: + funct6 = RISCV_MVX_VMULHSU; + break; + case 0x21: + funct6 = RISCV_MVX_VDIV; + break; + case 0x0F: + funct6 = RISCV_MVX_VSLIDE1DOWN; + break; + case 0x20: + funct6 = RISCV_MVX_VDIVU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MVXTYPE; + tree->ast_node.mvxtype.funct6 = funct6; + tree->ast_node.mvxtype.vm = vm; + tree->ast_node.mvxtype.vs2 = vs2; + tree->ast_node.mvxtype.rs1 = rs1; + tree->ast_node.mvxtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MVXMATYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2D: + funct6 = RISCV_MVX_VMACC; + break; + case 0x2F: + funct6 = RISCV_MVX_VNMSAC; + break; + case 0x2B: + funct6 = RISCV_MVX_VNMSUB; + break; + case 0x29: + funct6 = RISCV_MVX_VMADD; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MVXMATYPE; + tree->ast_node.mvxmatype.funct6 = funct6; + tree->ast_node.mvxmatype.vm = vm; + tree->ast_node.mvxmatype.vs2 = vs2; + tree->ast_node.mvxmatype.rs1 = rs1; + tree->ast_node.mvxmatype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------WVXTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x3B: + funct6 = RISCV_WVX_VWMUL; + break; + case 0x33: + funct6 = RISCV_WVX_VSUB; + break; + case 0x3A: + funct6 = RISCV_WVX_VWMULSU; + break; + case 0x31: + funct6 = RISCV_WVX_VADD; + break; + case 0x30: + funct6 = RISCV_WVX_VADDU; + break; + case 0x32: + funct6 = RISCV_WVX_VSUBU; + break; + case 0x38: + funct6 = RISCV_WVX_VWMULU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_WVXTYPE; + tree->ast_node.wvxtype.funct6 = funct6; + tree->ast_node.wvxtype.vm = vm; + tree->ast_node.wvxtype.vs2 = vs2; + tree->ast_node.wvxtype.rs1 = rs1; + tree->ast_node.wvxtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------WXTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x36: + funct6 = RISCV_WX_VSUBU; + break; + case 0x35: + funct6 = RISCV_WX_VADD; + break; + case 0x37: + funct6 = RISCV_WX_VSUB; + break; + case 0x34: + funct6 = RISCV_WX_VADDU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_WXTYPE; + tree->ast_node.wxtype.funct6 = funct6; + tree->ast_node.wxtype.vm = vm; + tree->ast_node.wxtype.vs2 = vs2; + tree->ast_node.wxtype.rs1 = rs1; + tree->ast_node.wxtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------WMVXTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x3E: + funct6 = RISCV_WMVX_VWMACCUS; + break; + case 0x3D: + funct6 = RISCV_WMVX_VWMACC; + break; + case 0x3C: + funct6 = RISCV_WMVX_VWMACCU; + break; + case 0x3F: + funct6 = RISCV_WMVX_VWMACCSU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_WMVXTYPE; + tree->ast_node.wmvxtype.funct6 = funct6; + tree->ast_node.wmvxtype.vm = vm; + tree->ast_node.wmvxtype.vs2 = vs2; + tree->ast_node.wmvxtype.rs1 = rs1; + tree->ast_node.wmvxtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VMVSX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x10) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VMVSX; + tree->ast_node.vmvsx.rs1 = rs1; + tree->ast_node.vmvsx.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FVVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x08: + funct6 = RISCV_FVV_VSGNJ; + break; + case 0x06: + funct6 = RISCV_FVV_VMAX; + break; + case 0x04: + funct6 = RISCV_FVV_VMIN; + break; + case 0x09: + funct6 = RISCV_FVV_VSGNJN; + break; + case 0x00: + funct6 = RISCV_FVV_VADD; + break; + case 0x0A: + funct6 = RISCV_FVV_VSGNJX; + break; + case 0x24: + funct6 = RISCV_FVV_VMUL; + break; + case 0x02: + funct6 = RISCV_FVV_VSUB; + break; + case 0x20: + funct6 = RISCV_FVV_VDIV; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FVVTYPE; + tree->ast_node.fvvtype.funct6 = funct6; + tree->ast_node.fvvtype.vm = vm; + tree->ast_node.fvvtype.vs2 = vs2; + tree->ast_node.fvvtype.vs1 = vs1; + tree->ast_node.fvvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FVVMATYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x28: + funct6 = RISCV_FVV_VMADD; + break; + case 0x2C: + funct6 = RISCV_FVV_VMACC; + break; + case 0x2D: + funct6 = RISCV_FVV_VNMACC; + break; + case 0x2E: + funct6 = RISCV_FVV_VMSAC; + break; + case 0x2F: + funct6 = RISCV_FVV_VNMSAC; + break; + case 0x2A: + funct6 = RISCV_FVV_VMSUB; + break; + case 0x2B: + funct6 = RISCV_FVV_VNMSUB; + break; + case 0x29: + funct6 = RISCV_FVV_VNMADD; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FVVMATYPE; + tree->ast_node.fvvmatype.funct6 = funct6; + tree->ast_node.fvvmatype.vm = vm; + tree->ast_node.fvvmatype.vs2 = vs2; + tree->ast_node.fvvmatype.vs1 = vs1; + tree->ast_node.fvvmatype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FWVVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x30: + funct6 = RISCV_FWVV_VADD; + break; + case 0x32: + funct6 = RISCV_FWVV_VSUB; + break; + case 0x38: + funct6 = RISCV_FWVV_VMUL; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FWVVTYPE; + tree->ast_node.fwvvtype.funct6 = funct6; + tree->ast_node.fwvvtype.vm = vm; + tree->ast_node.fwvvtype.vs2 = vs2; + tree->ast_node.fwvvtype.vs1 = vs1; + tree->ast_node.fwvvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FWVVMATYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x3E: + funct6 = RISCV_FWVV_VMSAC; + break; + case 0x3D: + funct6 = RISCV_FWVV_VNMACC; + break; + case 0x3C: + funct6 = RISCV_FWVV_VMACC; + break; + case 0x3F: + funct6 = RISCV_FWVV_VNMSAC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FWVVMATYPE; + tree->ast_node.fwvvmatype.funct6 = funct6; + tree->ast_node.fwvvmatype.vm = vm; + tree->ast_node.fwvvmatype.vs1 = vs1; + tree->ast_node.fwvvmatype.vs2 = vs2; + tree->ast_node.fwvvmatype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FWVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x36: + funct6 = RISCV_FWV_VSUB; + break; + case 0x34: + funct6 = RISCV_FWV_VADD; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FWVTYPE; + tree->ast_node.fwvtype.funct6 = funct6; + tree->ast_node.fwvtype.vm = vm; + tree->ast_node.fwvtype.vs2 = vs2; + tree->ast_node.fwvtype.vs1 = vs1; + tree->ast_node.fwvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFUNARY0------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vfunary0 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 15, 19)) { + case 0x01: + vfunary0 = RISCV_FV_CVT_X_F; + break; + case 0x06: + vfunary0 = RISCV_FV_CVT_RTZ_XU_F; + break; + case 0x07: + vfunary0 = RISCV_FV_CVT_RTZ_X_F; + break; + case 0x00: + vfunary0 = RISCV_FV_CVT_XU_F; + break; + case 0x03: + vfunary0 = RISCV_FV_CVT_F_X; + break; + case 0x02: + vfunary0 = RISCV_FV_CVT_F_XU; + break; + } + if (vfunary0 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFUNARY0; + tree->ast_node.vfunary0.vm = vm; + tree->ast_node.vfunary0.vs2 = vs2; + tree->ast_node.vfunary0.vfunary0 = vfunary0; + tree->ast_node.vfunary0.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFWUNARY0------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vfwunary0 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 15, 19)) { + case 0x08: + vfwunary0 = RISCV_FWV_CVT_XU_F; + break; + case 0x0B: + vfwunary0 = RISCV_FWV_CVT_F_X; + break; + case 0x09: + vfwunary0 = RISCV_FWV_CVT_X_F; + break; + case 0x0A: + vfwunary0 = RISCV_FWV_CVT_F_XU; + break; + case 0x0E: + vfwunary0 = RISCV_FWV_CVT_RTZ_XU_F; + break; + case 0x0C: + vfwunary0 = RISCV_FWV_CVT_F_F; + break; + case 0x0F: + vfwunary0 = RISCV_FWV_CVT_RTZ_X_F; + break; + } + if (vfwunary0 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFWUNARY0; + tree->ast_node.vfwunary0.vm = vm; + tree->ast_node.vfwunary0.vs2 = vs2; + tree->ast_node.vfwunary0.vfwunary0 = vfwunary0; + tree->ast_node.vfwunary0.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFNUNARY0------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vfnunary0 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 15, 19)) { + case 0x15: + vfnunary0 = RISCV_FNV_CVT_ROD_F_F; + break; + case 0x13: + vfnunary0 = RISCV_FNV_CVT_F_X; + break; + case 0x10: + vfnunary0 = RISCV_FNV_CVT_XU_F; + break; + case 0x12: + vfnunary0 = RISCV_FNV_CVT_F_XU; + break; + case 0x14: + vfnunary0 = RISCV_FNV_CVT_F_F; + break; + case 0x16: + vfnunary0 = RISCV_FNV_CVT_RTZ_XU_F; + break; + case 0x11: + vfnunary0 = RISCV_FNV_CVT_X_F; + break; + case 0x17: + vfnunary0 = RISCV_FNV_CVT_RTZ_X_F; + break; + } + if (vfnunary0 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFNUNARY0; + tree->ast_node.vfnunary0.vm = vm; + tree->ast_node.vfnunary0.vs2 = vs2; + tree->ast_node.vfnunary0.vfnunary0 = vfnunary0; + tree->ast_node.vfnunary0.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFUNARY1------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x13) { + uint64_t vfunary1 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 15, 19)) { + case 0x04: + vfunary1 = RISCV_FVV_VRSQRT7; + break; + case 0x10: + vfunary1 = RISCV_FVV_VCLASS; + break; + case 0x00: + vfunary1 = RISCV_FVV_VSQRT; + break; + case 0x05: + vfunary1 = RISCV_FVV_VREC7; + break; + } + if (vfunary1 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFUNARY1; + tree->ast_node.vfunary1.vm = vm; + tree->ast_node.vfunary1.vs2 = vs2; + tree->ast_node.vfunary1.vfunary1 = vfunary1; + tree->ast_node.vfunary1.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFMVFS------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFMVFS; + tree->ast_node.vfmvfs.vs2 = vs2; + tree->ast_node.vfmvfs.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FVFTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x08: + funct6 = RISCV_VF_VSGNJ; + break; + case 0x06: + funct6 = RISCV_VF_VMAX; + break; + case 0x04: + funct6 = RISCV_VF_VMIN; + break; + case 0x09: + funct6 = RISCV_VF_VSGNJN; + break; + case 0x27: + funct6 = RISCV_VF_VRSUB; + break; + case 0x00: + funct6 = RISCV_VF_VADD; + break; + case 0x0A: + funct6 = RISCV_VF_VSGNJX; + break; + case 0x24: + funct6 = RISCV_VF_VMUL; + break; + case 0x0E: + funct6 = RISCV_VF_VSLIDE1UP; + break; + case 0x21: + funct6 = RISCV_VF_VRDIV; + break; + case 0x02: + funct6 = RISCV_VF_VSUB; + break; + case 0x0F: + funct6 = RISCV_VF_VSLIDE1DOWN; + break; + case 0x20: + funct6 = RISCV_VF_VDIV; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FVFTYPE; + tree->ast_node.fvftype.funct6 = funct6; + tree->ast_node.fvftype.vm = vm; + tree->ast_node.fvftype.vs2 = vs2; + tree->ast_node.fvftype.rs1 = rs1; + tree->ast_node.fvftype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FVFMATYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x28: + funct6 = RISCV_VF_VMADD; + break; + case 0x2C: + funct6 = RISCV_VF_VMACC; + break; + case 0x2D: + funct6 = RISCV_VF_VNMACC; + break; + case 0x2E: + funct6 = RISCV_VF_VMSAC; + break; + case 0x2F: + funct6 = RISCV_VF_VNMSAC; + break; + case 0x2A: + funct6 = RISCV_VF_VMSUB; + break; + case 0x2B: + funct6 = RISCV_VF_VNMSUB; + break; + case 0x29: + funct6 = RISCV_VF_VNMADD; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FVFMATYPE; + tree->ast_node.fvfmatype.funct6 = funct6; + tree->ast_node.fvfmatype.vm = vm; + tree->ast_node.fvfmatype.vs2 = vs2; + tree->ast_node.fvfmatype.rs1 = rs1; + tree->ast_node.fvfmatype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FWVFTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x30: + funct6 = RISCV_FWVF_VADD; + break; + case 0x32: + funct6 = RISCV_FWVF_VSUB; + break; + case 0x38: + funct6 = RISCV_FWVF_VMUL; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FWVFTYPE; + tree->ast_node.fwvftype.funct6 = funct6; + tree->ast_node.fwvftype.vm = vm; + tree->ast_node.fwvftype.vs2 = vs2; + tree->ast_node.fwvftype.rs1 = rs1; + tree->ast_node.fwvftype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FWVFMATYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x3E: + funct6 = RISCV_FWVF_VMSAC; + break; + case 0x3D: + funct6 = RISCV_FWVF_VNMACC; + break; + case 0x3C: + funct6 = RISCV_FWVF_VMACC; + break; + case 0x3F: + funct6 = RISCV_FWVF_VNMSAC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FWVFMATYPE; + tree->ast_node.fwvfmatype.funct6 = funct6; + tree->ast_node.fwvfmatype.vm = vm; + tree->ast_node.fwvfmatype.rs1 = rs1; + tree->ast_node.fwvfmatype.vs2 = vs2; + tree->ast_node.fwvfmatype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FWFTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x36: + funct6 = RISCV_FWF_VSUB; + break; + case 0x34: + funct6 = RISCV_FWF_VADD; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FWFTYPE; + tree->ast_node.fwftype.funct6 = funct6; + tree->ast_node.fwftype.vm = vm; + tree->ast_node.fwftype.vs2 = vs2; + tree->ast_node.fwftype.rs1 = rs1; + tree->ast_node.fwftype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFMERGE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFMERGE; + tree->ast_node.vfmerge.vs2 = vs2; + tree->ast_node.vfmerge.rs1 = rs1; + tree->ast_node.vfmerge.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFMV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x17) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFMV; + tree->ast_node.vfmv.rs1 = rs1; + tree->ast_node.vfmv.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFMVSF------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x10) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFMVSF; + tree->ast_node.vfmvsf.rs1 = rs1; + tree->ast_node.vfmvsf.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VLSEGTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x0 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VLSEGTYPE; + tree->ast_node.vlsegtype.nf = nf; + tree->ast_node.vlsegtype.vm = vm; + tree->ast_node.vlsegtype.rs1 = rs1; + tree->ast_node.vlsegtype.width = width; + tree->ast_node.vlsegtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VLSEGFFTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x10 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x0 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VLSEGFFTYPE; + tree->ast_node.vlsegfftype.nf = nf; + tree->ast_node.vlsegfftype.vm = vm; + tree->ast_node.vlsegfftype.rs1 = rs1; + tree->ast_node.vlsegfftype.width = width; + tree->ast_node.vlsegfftype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSSEGTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x27 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x0 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vs3 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VSSEGTYPE; + tree->ast_node.vssegtype.nf = nf; + tree->ast_node.vssegtype.vm = vm; + tree->ast_node.vssegtype.rs1 = rs1; + tree->ast_node.vssegtype.width = width; + tree->ast_node.vssegtype.vs3 = vs3; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VLSSEGTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x2 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VLSSEGTYPE; + tree->ast_node.vlssegtype.nf = nf; + tree->ast_node.vlssegtype.vm = vm; + tree->ast_node.vlssegtype.rs2 = rs2; + tree->ast_node.vlssegtype.rs1 = rs1; + tree->ast_node.vlssegtype.width = width; + tree->ast_node.vlssegtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSSSEGTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x27 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x2 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vs3 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VSSSEGTYPE; + tree->ast_node.vsssegtype.nf = nf; + tree->ast_node.vsssegtype.vm = vm; + tree->ast_node.vsssegtype.rs2 = rs2; + tree->ast_node.vsssegtype.rs1 = rs1; + tree->ast_node.vsssegtype.width = width; + tree->ast_node.vsssegtype.vs3 = vs3; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VLUXSEGTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x1 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VLUXSEGTYPE; + tree->ast_node.vluxsegtype.nf = nf; + tree->ast_node.vluxsegtype.vm = vm; + tree->ast_node.vluxsegtype.vs2 = vs2; + tree->ast_node.vluxsegtype.rs1 = rs1; + tree->ast_node.vluxsegtype.width = width; + tree->ast_node.vluxsegtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VLOXSEGTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x3 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VLOXSEGTYPE; + tree->ast_node.vloxsegtype.nf = nf; + tree->ast_node.vloxsegtype.vm = vm; + tree->ast_node.vloxsegtype.vs2 = vs2; + tree->ast_node.vloxsegtype.rs1 = rs1; + tree->ast_node.vloxsegtype.width = width; + tree->ast_node.vloxsegtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSUXSEGTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x27 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x1 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vs3 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VSUXSEGTYPE; + tree->ast_node.vsuxsegtype.nf = nf; + tree->ast_node.vsuxsegtype.vm = vm; + tree->ast_node.vsuxsegtype.vs2 = vs2; + tree->ast_node.vsuxsegtype.rs1 = rs1; + tree->ast_node.vsuxsegtype.width = width; + tree->ast_node.vsuxsegtype.vs3 = vs3; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSOXSEGTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x27 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x3 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vs3 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VSOXSEGTYPE; + tree->ast_node.vsoxsegtype.nf = nf; + tree->ast_node.vsoxsegtype.vm = vm; + tree->ast_node.vsoxsegtype.vs2 = vs2; + tree->ast_node.vsoxsegtype.rs1 = rs1; + tree->ast_node.vsoxsegtype.width = width; + tree->ast_node.vsoxsegtype.vs3 = vs3; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VLRETYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x07 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x08 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x0 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t width = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 12, 14)) { + case 0x7: + width = RISCV_VLE64; + break; + case 0x5: + width = RISCV_VLE16; + break; + case 0x6: + width = RISCV_VLE32; + break; + case 0x0: + width = RISCV_VLE8; + break; + } + if (width != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VLRETYPE; + tree->ast_node.vlretype.nf = nf; + tree->ast_node.vlretype.rs1 = rs1; + tree->ast_node.vlretype.width = width; + tree->ast_node.vlretype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSRETYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x27 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x08 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x0 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0) { + uint64_t vs3 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t nf = SLICE_BITVEC(binary_stream, 29, 31); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VSRETYPE; + tree->ast_node.vsretype.nf = nf; + tree->ast_node.vsretype.rs1 = rs1; + tree->ast_node.vsretype.vs3 = vs3; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VMTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x0B && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 26, 27) == 0x0 && + SLICE_BITVEC(binary_stream, 28, 28) == 0x0 && + SLICE_BITVEC(binary_stream, 29, 31) == 0x0) { + uint64_t op = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 0, 6)) { + case 0x07: + op = RISCV_VLM; + break; + case 0x27: + op = RISCV_VSM; + break; + } + if (op != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd_or_vs3 = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VMTYPE; + tree->ast_node.vmtype.rs1 = rs1; + tree->ast_node.vmtype.vd_or_vs3 = vd_or_vs3; + tree->ast_node.vmtype.op = op; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------MMTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x19: + funct6 = RISCV_MM_VMAND; + break; + case 0x1B: + funct6 = RISCV_MM_VMXOR; + break; + case 0x1C: + funct6 = RISCV_MM_VMORN; + break; + case 0x1A: + funct6 = RISCV_MM_VMOR; + break; + case 0x1E: + funct6 = RISCV_MM_VMNOR; + break; + case 0x1D: + funct6 = RISCV_MM_VMNAND; + break; + case 0x18: + funct6 = RISCV_MM_VMANDN; + break; + case 0x1F: + funct6 = RISCV_MM_VMXNOR; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_MMTYPE; + tree->ast_node.mmtype.funct6 = funct6; + tree->ast_node.mmtype.vs2 = vs2; + tree->ast_node.mmtype.vs1 = vs1; + tree->ast_node.mmtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VCPOP_M------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x10 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VCPOP_M; + tree->ast_node.vcpop_m.vm = vm; + tree->ast_node.vcpop_m.vs2 = vs2; + tree->ast_node.vcpop_m.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VFIRST_M------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x11 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x10) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VFIRST_M; + tree->ast_node.vfirst_m.vm = vm; + tree->ast_node.vfirst_m.vs2 = vs2; + tree->ast_node.vfirst_m.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VMSBF_M------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x01 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x14) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VMSBF_M; + tree->ast_node.vmsbf_m.vm = vm; + tree->ast_node.vmsbf_m.vs2 = vs2; + tree->ast_node.vmsbf_m.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VMSIF_M------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x03 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x14) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VMSIF_M; + tree->ast_node.vmsif_m.vm = vm; + tree->ast_node.vmsif_m.vs2 = vs2; + tree->ast_node.vmsif_m.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VMSOF_M------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x02 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x14) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VMSOF_M; + tree->ast_node.vmsof_m.vm = vm; + tree->ast_node.vmsof_m.vs2 = vs2; + tree->ast_node.vmsof_m.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VIOTA_M------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x10 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x14) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VIOTA_M; + tree->ast_node.viota_m.vm = vm; + tree->ast_node.viota_m.vs2 = vs2; + tree->ast_node.viota_m.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VID_V------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x11 && + SLICE_BITVEC(binary_stream, 20, 24) == 0x00 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x14) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VID_V; + tree->ast_node.vid_v.vm = vm; + tree->ast_node.vid_v.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VVMTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x13: + funct6 = RISCV_VVM_VMSBC; + break; + case 0x11: + funct6 = RISCV_VVM_VMADC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VVMTYPE; + tree->ast_node.vvmtype.funct6 = funct6; + tree->ast_node.vvmtype.vs2 = vs2; + tree->ast_node.vvmtype.vs1 = vs1; + tree->ast_node.vvmtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VVMCTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x13: + funct6 = RISCV_VVMC_VMSBC; + break; + case 0x11: + funct6 = RISCV_VVMC_VMADC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VVMCTYPE; + tree->ast_node.vvmctype.funct6 = funct6; + tree->ast_node.vvmctype.vs2 = vs2; + tree->ast_node.vvmctype.vs1 = vs1; + tree->ast_node.vvmctype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VVMSTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x10: + funct6 = RISCV_VVMS_VADC; + break; + case 0x12: + funct6 = RISCV_VVMS_VSBC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VVMSTYPE; + tree->ast_node.vvmstype.funct6 = funct6; + tree->ast_node.vvmstype.vs2 = vs2; + tree->ast_node.vvmstype.vs1 = vs1; + tree->ast_node.vvmstype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VVCMPTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x19: + funct6 = RISCV_VVCMP_VMSNE; + break; + case 0x1B: + funct6 = RISCV_VVCMP_VMSLT; + break; + case 0x1C: + funct6 = RISCV_VVCMP_VMSLEU; + break; + case 0x1A: + funct6 = RISCV_VVCMP_VMSLTU; + break; + case 0x18: + funct6 = RISCV_VVCMP_VMSEQ; + break; + case 0x1D: + funct6 = RISCV_VVCMP_VMSLE; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VVCMPTYPE; + tree->ast_node.vvcmptype.funct6 = funct6; + tree->ast_node.vvcmptype.vm = vm; + tree->ast_node.vvcmptype.vs2 = vs2; + tree->ast_node.vvcmptype.vs1 = vs1; + tree->ast_node.vvcmptype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VXMTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x13: + funct6 = RISCV_VXM_VMSBC; + break; + case 0x11: + funct6 = RISCV_VXM_VMADC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VXMTYPE; + tree->ast_node.vxmtype.funct6 = funct6; + tree->ast_node.vxmtype.vs2 = vs2; + tree->ast_node.vxmtype.rs1 = rs1; + tree->ast_node.vxmtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VXMCTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x13: + funct6 = RISCV_VXMC_VMSBC; + break; + case 0x11: + funct6 = RISCV_VXMC_VMADC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VXMCTYPE; + tree->ast_node.vxmctype.funct6 = funct6; + tree->ast_node.vxmctype.vs2 = vs2; + tree->ast_node.vxmctype.rs1 = rs1; + tree->ast_node.vxmctype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VXMSTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x10: + funct6 = RISCV_VXMS_VADC; + break; + case 0x12: + funct6 = RISCV_VXMS_VSBC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VXMSTYPE; + tree->ast_node.vxmstype.funct6 = funct6; + tree->ast_node.vxmstype.vs2 = vs2; + tree->ast_node.vxmstype.rs1 = rs1; + tree->ast_node.vxmstype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VXCMPTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x19: + funct6 = RISCV_VXCMP_VMSNE; + break; + case 0x1B: + funct6 = RISCV_VXCMP_VMSLT; + break; + case 0x1C: + funct6 = RISCV_VXCMP_VMSLEU; + break; + case 0x1A: + funct6 = RISCV_VXCMP_VMSLTU; + break; + case 0x1E: + funct6 = RISCV_VXCMP_VMSGTU; + break; + case 0x18: + funct6 = RISCV_VXCMP_VMSEQ; + break; + case 0x1D: + funct6 = RISCV_VXCMP_VMSLE; + break; + case 0x1F: + funct6 = RISCV_VXCMP_VMSGT; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VXCMPTYPE; + tree->ast_node.vxcmptype.funct6 = funct6; + tree->ast_node.vxcmptype.vm = vm; + tree->ast_node.vxcmptype.vs2 = vs2; + tree->ast_node.vxcmptype.rs1 = rs1; + tree->ast_node.vxcmptype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VIMTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x11: + funct6 = RISCV_VIM_VMADC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VIMTYPE; + tree->ast_node.vimtype.funct6 = funct6; + tree->ast_node.vimtype.vs2 = vs2; + tree->ast_node.vimtype.simm = simm; + tree->ast_node.vimtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VIMCTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x11: + funct6 = RISCV_VIMC_VMADC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VIMCTYPE; + tree->ast_node.vimctype.funct6 = funct6; + tree->ast_node.vimctype.vs2 = vs2; + tree->ast_node.vimctype.simm = simm; + tree->ast_node.vimctype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VIMSTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x10: + funct6 = RISCV_VIMS_VADC; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VIMSTYPE; + tree->ast_node.vimstype.funct6 = funct6; + tree->ast_node.vimstype.vs2 = vs2; + tree->ast_node.vimstype.simm = simm; + tree->ast_node.vimstype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VICMPTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x19: + funct6 = RISCV_VICMP_VMSNE; + break; + case 0x1C: + funct6 = RISCV_VICMP_VMSLEU; + break; + case 0x1E: + funct6 = RISCV_VICMP_VMSGTU; + break; + case 0x18: + funct6 = RISCV_VICMP_VMSEQ; + break; + case 0x1D: + funct6 = RISCV_VICMP_VMSLE; + break; + case 0x1F: + funct6 = RISCV_VICMP_VMSGT; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t simm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_VICMPTYPE; + tree->ast_node.vicmptype.funct6 = funct6; + tree->ast_node.vicmptype.vm = vm; + tree->ast_node.vicmptype.vs2 = vs2; + tree->ast_node.vicmptype.simm = simm; + tree->ast_node.vicmptype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FVVMTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x19: + funct6 = RISCV_FVVM_VMFLE; + break; + case 0x1B: + funct6 = RISCV_FVVM_VMFLT; + break; + case 0x1C: + funct6 = RISCV_FVVM_VMFNE; + break; + case 0x18: + funct6 = RISCV_FVVM_VMFEQ; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FVVMTYPE; + tree->ast_node.fvvmtype.funct6 = funct6; + tree->ast_node.fvvmtype.vm = vm; + tree->ast_node.fvvmtype.vs2 = vs2; + tree->ast_node.fvvmtype.vs1 = vs1; + tree->ast_node.fvvmtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------FVFMTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x5) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x19: + funct6 = RISCV_VFM_VMFLE; + break; + case 0x1B: + funct6 = RISCV_VFM_VMFLT; + break; + case 0x1C: + funct6 = RISCV_VFM_VMFNE; + break; + case 0x18: + funct6 = RISCV_VFM_VMFEQ; + break; + case 0x1D: + funct6 = RISCV_VFM_VMFGT; + break; + case 0x1F: + funct6 = RISCV_VFM_VMFGE; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_FVFMTYPE; + tree->ast_node.fvfmtype.funct6 = funct6; + tree->ast_node.fvfmtype.vm = vm; + tree->ast_node.fvfmtype.vs2 = vs2; + tree->ast_node.fvfmtype.rs1 = rs1; + tree->ast_node.fvfmtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RIVVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x31: + funct6 = RISCV_IVV_VWREDSUM; + break; + case 0x30: + funct6 = RISCV_IVV_VWREDSUMU; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_RIVVTYPE; + tree->ast_node.rivvtype.funct6 = funct6; + tree->ast_node.rivvtype.vm = vm; + tree->ast_node.rivvtype.vs2 = vs2; + tree->ast_node.rivvtype.vs1 = vs1; + tree->ast_node.rivvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RMVVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x01: + funct6 = RISCV_MVV_VREDAND; + break; + case 0x06: + funct6 = RISCV_MVV_VREDMAXU; + break; + case 0x07: + funct6 = RISCV_MVV_VREDMAX; + break; + case 0x04: + funct6 = RISCV_MVV_VREDMINU; + break; + case 0x00: + funct6 = RISCV_MVV_VREDSUM; + break; + case 0x03: + funct6 = RISCV_MVV_VREDXOR; + break; + case 0x05: + funct6 = RISCV_MVV_VREDMIN; + break; + case 0x02: + funct6 = RISCV_MVV_VREDOR; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_RMVVTYPE; + tree->ast_node.rmvvtype.funct6 = funct6; + tree->ast_node.rmvvtype.vm = vm; + tree->ast_node.rmvvtype.vs2 = vs2; + tree->ast_node.rmvvtype.vs1 = vs1; + tree->ast_node.rmvvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RFVVTYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x33: + funct6 = RISCV_FVV_VFWREDOSUM; + break; + case 0x01: + funct6 = RISCV_FVV_VFREDUSUM; + break; + case 0x31: + funct6 = RISCV_FVV_VFWREDUSUM; + break; + case 0x07: + funct6 = RISCV_FVV_VFREDMAX; + break; + case 0x03: + funct6 = RISCV_FVV_VFREDOSUM; + break; + case 0x05: + funct6 = RISCV_FVV_VFREDMIN; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_V, ctx)) { + tree->ast_node_type = RISCV_RFVVTYPE; + tree->ast_node.rfvvtype.funct6 = funct6; + tree->ast_node.rfvvtype.vm = vm; + tree->ast_node.rfvvtype.vs2 = vs2; + tree->ast_node.rfvvtype.vs1 = vs1; + tree->ast_node.rfvvtype.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_ZICBOM------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x0F && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2) { + uint64_t cbop = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 20, 31)) { + case 0x000: + cbop = RISCV_CBO_INVAL; + break; + case 0x002: + cbop = RISCV_CBO_FLUSH; + break; + case 0x001: + cbop = RISCV_CBO_CLEAN; + break; + } + if (cbop != 0xFFFFFFFFFFFFFFFF) { + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zicbom, ctx)) { + tree->ast_node_type = RISCV_ZICBOM; + tree->ast_node.riscv_zicbom.cbo_inval = cbop; + tree->ast_node.riscv_zicbom.rs1 = rs1; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------RISCV_ZICBOZ------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x0F && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 20, 31) == 0x004) { + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + if (currentlyEnabled(RISCV_Ext_Zicboz, ctx)) { + tree->ast_node_type = RISCV_ZICBOZ; + tree->ast_node.riscv_zicboz = rs1; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VANDN_VV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x01) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VANDN_VV; + tree->ast_node.vandn_vv.vm = vm; + tree->ast_node.vandn_vv.vs1 = vs1; + tree->ast_node.vandn_vv.vs2 = vs2; + tree->ast_node.vandn_vv.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VANDN_VX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x01) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VANDN_VX; + tree->ast_node.vandn_vx.vm = vm; + tree->ast_node.vandn_vx.vs2 = vs2; + tree->ast_node.vandn_vx.rs1 = rs1; + tree->ast_node.vandn_vx.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VBREV_V------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x0A && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvbb, ctx)) { + tree->ast_node_type = RISCV_VBREV_V; + tree->ast_node.vbrev_v.vm = vm; + tree->ast_node.vbrev_v.vs2 = vs2; + tree->ast_node.vbrev_v.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VBREV8_V------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x08 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VBREV8_V; + tree->ast_node.vbrev8_v.vm = vm; + tree->ast_node.vbrev8_v.vs2 = vs2; + tree->ast_node.vbrev8_v.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VREV8_V------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x09 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VREV8_V; + tree->ast_node.vrev8_v.vm = vm; + tree->ast_node.vrev8_v.vs2 = vs2; + tree->ast_node.vrev8_v.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VCLZ_V------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x0C && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvbb, ctx)) { + tree->ast_node_type = RISCV_VCLZ_V; + tree->ast_node.vclz_v.vm = vm; + tree->ast_node.vclz_v.vs2 = vs2; + tree->ast_node.vclz_v.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VCTZ_V------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x0D && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvbb, ctx)) { + tree->ast_node_type = RISCV_VCTZ_V; + tree->ast_node.vctz_v.vm = vm; + tree->ast_node.vctz_v.vs2 = vs2; + tree->ast_node.vctz_v.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VCPOP_V------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 15, 19) == 0x0E && + SLICE_BITVEC(binary_stream, 26, 31) == 0x12) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvbb, ctx)) { + tree->ast_node_type = RISCV_VCPOP_V; + tree->ast_node.vcpop_v.vm = vm; + tree->ast_node.vcpop_v.vs2 = vs2; + tree->ast_node.vcpop_v.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VROL_VV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x15) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VROL_VV; + tree->ast_node.vrol_vv.vm = vm; + tree->ast_node.vrol_vv.vs1 = vs1; + tree->ast_node.vrol_vv.vs2 = vs2; + tree->ast_node.vrol_vv.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VROL_VX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x15) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VROL_VX; + tree->ast_node.vrol_vx.vm = vm; + tree->ast_node.vrol_vx.vs2 = vs2; + tree->ast_node.vrol_vx.rs1 = rs1; + tree->ast_node.vrol_vx.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VROR_VV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x14) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VROR_VV; + tree->ast_node.vror_vv.vm = vm; + tree->ast_node.vror_vv.vs1 = vs1; + tree->ast_node.vror_vv.vs2 = vs2; + tree->ast_node.vror_vv.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VROR_VX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x14) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VROR_VX; + tree->ast_node.vror_vx.vm = vm; + tree->ast_node.vror_vx.vs2 = vs2; + tree->ast_node.vror_vx.rs1 = rs1; + tree->ast_node.vror_vx.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VROR_VI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x14) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t uimm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvkb, ctx)) { + tree->ast_node_type = RISCV_VROR_VI; + tree->ast_node.vror_vi.vm = vm; + tree->ast_node.vror_vi.vs2 = vs2; + tree->ast_node.vror_vi.uimm = uimm; + tree->ast_node.vror_vi.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VWSLL_VV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x0 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x35) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvbb, ctx)) { + tree->ast_node_type = RISCV_VWSLL_VV; + tree->ast_node.vwsll_vv.vm = vm; + tree->ast_node.vwsll_vv.vs2 = vs2; + tree->ast_node.vwsll_vv.vs1 = vs1; + tree->ast_node.vwsll_vv.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VWSLL_VX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x35) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvbb, ctx)) { + tree->ast_node_type = RISCV_VWSLL_VX; + tree->ast_node.vwsll_vx.vm = vm; + tree->ast_node.vwsll_vx.vs2 = vs2; + tree->ast_node.vwsll_vx.rs1 = rs1; + tree->ast_node.vwsll_vx.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VWSLL_VI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x3 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x35) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t uimm = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if (currentlyEnabled(RISCV_Ext_Zvbb, ctx)) { + tree->ast_node_type = RISCV_VWSLL_VI; + tree->ast_node.vwsll_vi.vm = vm; + tree->ast_node.vwsll_vi.vs2 = vs2; + tree->ast_node.vwsll_vi.uimm = uimm; + tree->ast_node.vwsll_vi.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VCLMUL_VV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x0C) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if ((currentlyEnabled(RISCV_Ext_Zvbc, ctx)) && (get_sew(ctx) == 64)) { + tree->ast_node_type = RISCV_VCLMUL_VV; + tree->ast_node.vclmul_vv.vm = vm; + tree->ast_node.vclmul_vv.vs2 = vs2; + tree->ast_node.vclmul_vv.vs1 = vs1; + tree->ast_node.vclmul_vv.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VCLMUL_VX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x0C) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if ((currentlyEnabled(RISCV_Ext_Zvbc, ctx)) && (get_sew(ctx) == 64)) { + tree->ast_node_type = RISCV_VCLMUL_VX; + tree->ast_node.vclmul_vx.vm = vm; + tree->ast_node.vclmul_vx.vs2 = vs2; + tree->ast_node.vclmul_vx.rs1 = rs1; + tree->ast_node.vclmul_vx.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VCLMULH_VV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x0D) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if ((currentlyEnabled(RISCV_Ext_Zvbc, ctx)) && (get_sew(ctx) == 64)) { + tree->ast_node_type = RISCV_VCLMULH_VV; + tree->ast_node.vclmulh_vv.vm = vm; + tree->ast_node.vclmulh_vv.vs2 = vs2; + tree->ast_node.vclmulh_vv.vs1 = vs1; + tree->ast_node.vclmulh_vv.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VCLMULH_VX------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x57 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x6 && + SLICE_BITVEC(binary_stream, 26, 31) == 0x0D) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t vm = SLICE_BITVEC(binary_stream, 25, 25); + if ((currentlyEnabled(RISCV_Ext_Zvbc, ctx)) && (get_sew(ctx) == 64)) { + tree->ast_node_type = RISCV_VCLMULH_VX; + tree->ast_node.vclmulh_vx.vm = vm; + tree->ast_node.vclmulh_vx.vs2 = vs2; + tree->ast_node.vclmulh_vx.rs1 = rs1; + tree->ast_node.vclmulh_vx.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------VSHA2MS_VV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x77 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 31) == 0x5B) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (((currentlyEnabled(RISCV_Ext_Zvknha, ctx)) && (get_sew(ctx) == 32)) || + (((currentlyEnabled(RISCV_Ext_Zvknhb, ctx)) && + ((get_sew(ctx) == 32) || (get_sew(ctx) == 64))) && + (zvknhab_check_encdec(vs2, vs1, vd, ctx)))) { + tree->ast_node_type = RISCV_VSHA2MS_VV; + tree->ast_node.vsha2ms_vv.vs2 = vs2; + tree->ast_node.vsha2ms_vv.vs1 = vs1; + tree->ast_node.vsha2ms_vv.vd = vd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZVKSHA2TYPE------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x77 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x2 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1) { + uint64_t funct6 = 0xFFFFFFFFFFFFFFFF; + switch (SLICE_BITVEC(binary_stream, 26, 31)) { + case 0x2E: + funct6 = RISCV_ZVK_VSHA2CH; + break; + case 0x2F: + funct6 = RISCV_ZVK_VSHA2CL; + break; + } + if (funct6 != 0xFFFFFFFFFFFFFFFF) { + uint64_t vd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t vs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t vs2 = SLICE_BITVEC(binary_stream, 20, 24); + if (((currentlyEnabled(RISCV_Ext_Zvknha, ctx)) && (get_sew(ctx) == 32)) || + (((currentlyEnabled(RISCV_Ext_Zvknhb, ctx)) && + ((get_sew(ctx) == 32) || (get_sew(ctx) == 64))) && + (zvknhab_check_encdec(vs2, vs1, vd, ctx)))) { + tree->ast_node_type = RISCV_ZVKSHA2TYPE; + tree->ast_node.zvksha2type.funct6 = funct6; + tree->ast_node.zvksha2type.vs2 = vs2; + tree->ast_node.zvksha2type.vs1 = vs1; + tree->ast_node.zvksha2type.vd = vd; + return; + } + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZIMOP_MOP_R------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 22, 25) == 0x7 && + SLICE_BITVEC(binary_stream, 28, 29) == 0x0 && + SLICE_BITVEC(binary_stream, 31, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t mop_21_20 = SLICE_BITVEC(binary_stream, 20, 21); + uint64_t mop_27_26 = SLICE_BITVEC(binary_stream, 26, 27); + uint64_t mop_30 = SLICE_BITVEC(binary_stream, 30, 30); + if (currentlyEnabled(RISCV_Ext_Zimop, ctx)) { + tree->ast_node_type = RISCV_ZIMOP_MOP_R; + tree->ast_node.zimop_mop_r.mop = + (mop_30 << 4) | (mop_27_26 << 2) | mop_21_20; + tree->ast_node.zimop_mop_r.rs1 = rs1; + tree->ast_node.zimop_mop_r.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZIMOP_MOP_RR------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 6) == 0x73 && + SLICE_BITVEC(binary_stream, 12, 14) == 0x4 && + SLICE_BITVEC(binary_stream, 25, 25) == 0x1 && + SLICE_BITVEC(binary_stream, 28, 29) == 0x0 && + SLICE_BITVEC(binary_stream, 31, 31) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 15, 19); + uint64_t rs2 = SLICE_BITVEC(binary_stream, 20, 24); + uint64_t mop_27_26 = SLICE_BITVEC(binary_stream, 26, 27); + uint64_t mop_30 = SLICE_BITVEC(binary_stream, 30, 30); + if (currentlyEnabled(RISCV_Ext_Zimop, ctx)) { + tree->ast_node_type = RISCV_ZIMOP_MOP_RR; + tree->ast_node.zimop_mop_rr.mop = (mop_30 << 2) | mop_27_26; + tree->ast_node.zimop_mop_rr.rs2 = rs2; + tree->ast_node.zimop_mop_rr.rs1 = rs1; + tree->ast_node.zimop_mop_rr.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------STOP_FETCHING------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x3 && + SLICE_BITVEC(binary_stream, 2, 4) == 0x2 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x0 && + SLICE_BITVEC(binary_stream, 7, 7) == 0x0 && + SLICE_BITVEC(binary_stream, 8, 15) == 0x00 && + SLICE_BITVEC(binary_stream, 16, 31) == 0xfade) { + tree->ast_node_type = RISCV_STOP_FETCHING; + ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------THREAD_START------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x3 && + SLICE_BITVEC(binary_stream, 2, 4) == 0x2 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x0 && + SLICE_BITVEC(binary_stream, 7, 7) == 0x0 && + SLICE_BITVEC(binary_stream, 8, 15) == 0x00 && + SLICE_BITVEC(binary_stream, 16, 31) == 0xc0de) { + tree->ast_node_type = RISCV_THREAD_START; + ; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------ILLEGAL------------------------------// + { + uint64_t s = SLICE_BITVEC(binary_stream, 0, 31); + tree->ast_node_type = RISCV_ILLEGAL; + tree->ast_node.illegal = s; + return; + } + //------------------------------------------------------------------------------------// +} +#endif diff --git a/arch/RISCV/RISCVDecodeCompressed.gen.inc b/arch/RISCV/RISCVDecodeCompressed.gen.inc new file mode 100644 index 0000000000..079d70fcde --- /dev/null +++ b/arch/RISCV/RISCVDecodeCompressed.gen.inc @@ -0,0 +1,1081 @@ +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ + +#ifndef __RISCVDECODECOMPRESSED_GEN_INC__ +#define __RISCVDECODECOMPRESSED_GEN_INC__ +#include +#include +#include + +#include "RISCVAst.gen.inc" +#include "RISCVDecodeHelpers.h" + +#define SLICE_BITVEC(v, s, e) ((v >> s) & ((((uint64_t)1) << (e - s + 1)) - 1)) + +#define INDEX_BITVEC(v, i) ((v >> i) & 1) + +static void decode_compressed(struct ast *tree, uint64_t binary_stream, + RVContext *ctx) { + //----------------------------C_NOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 6) == 0x00 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x0) { + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_NOP; + ; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ADDI4SPN------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x0) { + uint64_t rd = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t nz3 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t nz2 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t nz96 = SLICE_BITVEC(binary_stream, 7, 10); + uint64_t nz54 = SLICE_BITVEC(binary_stream, 11, 12); + if ((!(((nz2 << 7) | (nz3 << 6) | (nz54 << 4) | nz96) == 0x00)) && + (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_ADDI4SPN; + tree->ast_node.c_addi4spn.rdc = rd; + tree->ast_node.c_addi4spn.nzimm = + (nz96 << 4) | (nz54 << 2) | (nz3 << 1) | nz2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x2) { + uint64_t rd = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui6 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t ui2 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_LW; + tree->ast_node.c_lw.uimm = (ui6 << 4) | (ui53 << 1) | ui2; + tree->ast_node.c_lw.rsc = rs1; + tree->ast_node.c_lw.rdc = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LD------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x3) { + uint64_t rd = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui76 = SLICE_BITVEC(binary_stream, 5, 6); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_LD; + tree->ast_node.c_ld.uimm = (ui76 << 3) | ui53; + tree->ast_node.c_ld.rsc = rs1; + tree->ast_node.c_ld.rdc = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x6) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui6 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t ui2 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_SW; + tree->ast_node.c_sw.uimm = (ui6 << 4) | (ui53 << 1) | ui2; + tree->ast_node.c_sw.rsc1 = rs1; + tree->ast_node.c_sw.rsc2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SD------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x7) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui76 = SLICE_BITVEC(binary_stream, 5, 6); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_SD; + tree->ast_node.c_sd.uimm = (ui76 << 3) | ui53; + tree->ast_node.c_sd.rsc1 = rs1; + tree->ast_node.c_sd.rsc2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ADDI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x0) { + uint64_t nzi40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t nzi5 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(((nzi40 << 1) | nzi5) == 0x00)) && + ((!(rsd == ctx->zreg)) && (currentlyEnabled(RISCV_Ext_Zca, ctx)))) { + tree->ast_node_type = RISCV_C_ADDI; + tree->ast_node.c_addi.nzi = (nzi5 << 5) | nzi40; + tree->ast_node.c_addi.rsd = rsd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_JAL------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x1) { + uint64_t i5 = SLICE_BITVEC(binary_stream, 2, 2); + uint64_t i31 = SLICE_BITVEC(binary_stream, 3, 5); + uint64_t i7 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t i6 = SLICE_BITVEC(binary_stream, 7, 7); + uint64_t i10 = SLICE_BITVEC(binary_stream, 8, 8); + uint64_t i98 = SLICE_BITVEC(binary_stream, 9, 10); + uint64_t i4 = SLICE_BITVEC(binary_stream, 11, 11); + uint64_t i11 = SLICE_BITVEC(binary_stream, 12, 12); + if ((ctx->xlen == 32) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_JAL; + tree->ast_node.c_jal = (i11 << 10) | (i10 << 9) | (i98 << 7) | (i7 << 6) | + (i6 << 5) | (i5 << 4) | (i4 << 3) | i31; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ADDIW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x1) { + uint64_t imm40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t imm5 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(rsd == ctx->zreg)) && + ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_Zca, ctx)))) { + tree->ast_node_type = RISCV_C_ADDIW; + tree->ast_node.c_addiw.imm = (imm5 << 5) | imm40; + tree->ast_node.c_addiw.rsd = rsd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x2) { + uint64_t imm40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t imm5 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(rd == ctx->zreg)) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_LI; + tree->ast_node.c_li.imm = (imm5 << 5) | imm40; + tree->ast_node.c_li.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ADDI16SP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x02 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x3) { + uint64_t nzi5 = SLICE_BITVEC(binary_stream, 2, 2); + uint64_t nzi87 = SLICE_BITVEC(binary_stream, 3, 4); + uint64_t nzi6 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t nzi4 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t nzi9 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(((nzi4 << 5) | (nzi5 << 4) | (nzi6 << 3) | (nzi87 << 1) | nzi9) == + 0x00)) && + (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_ADDI16SP; + tree->ast_node.c_addi16sp = + (nzi9 << 5) | (nzi87 << 3) | (nzi6 << 2) | (nzi5 << 1) | nzi4; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LUI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x3) { + uint64_t imm1612 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t imm17 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(rd == ctx->zreg)) && + ((!(rd == ctx->sp)) && ((!(((imm1612 << 1) | imm17) == 0x00)) && + (currentlyEnabled(RISCV_Ext_Zca, ctx))))) { + tree->ast_node_type = RISCV_C_LUI; + tree->ast_node.c_lui.imm = (imm17 << 5) | imm1612; + tree->ast_node.c_lui.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SRLI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t nzui40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t nzui5 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(((nzui40 << 1) | nzui5) == 0x00)) && + (((ctx->xlen == 64) || (nzui5 == 0x0)) && + (currentlyEnabled(RISCV_Ext_Zca, ctx)))) { + tree->ast_node_type = RISCV_C_SRLI; + tree->ast_node.c_srli.shamt = (nzui5 << 5) | nzui40; + tree->ast_node.c_srli.rsd = rsd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SRAI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t nzui40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t nzui5 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(((nzui40 << 1) | nzui5) == 0x00)) && + (((ctx->xlen == 64) || (nzui5 == 0x0)) && + (currentlyEnabled(RISCV_Ext_Zca, ctx)))) { + tree->ast_node_type = RISCV_C_SRAI; + tree->ast_node.c_srai.shamt = (nzui5 << 5) | nzui40; + tree->ast_node.c_srai.rsd = rsd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ANDI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t i40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t i5 = SLICE_BITVEC(binary_stream, 12, 12); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_ANDI; + tree->ast_node.c_andi.imm = (i5 << 5) | i40; + tree->ast_node.c_andi.rsd = rsd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SUB------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x0 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x3 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_SUB; + tree->ast_node.c_sub.rsd = rsd; + tree->ast_node.c_sub.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_XOR------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x1 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x3 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_XOR; + tree->ast_node.c_xor.rsd = rsd; + tree->ast_node.c_xor.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_OR------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x2 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x3 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_OR; + tree->ast_node.c_or.rsd = rsd; + tree->ast_node.c_or.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_AND------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x3 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x3 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_AND; + tree->ast_node.c_and.rsd = rsd; + tree->ast_node.c_and.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SUBW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x0 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x3 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + if ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_SUBW; + tree->ast_node.c_subw.rsd = rsd; + tree->ast_node.c_subw.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ADDW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x1 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x3 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + if ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_ADDW; + tree->ast_node.c_addw.rsd = rsd; + tree->ast_node.c_addw.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_J------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x5) { + uint64_t i5 = SLICE_BITVEC(binary_stream, 2, 2); + uint64_t i31 = SLICE_BITVEC(binary_stream, 3, 5); + uint64_t i7 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t i6 = SLICE_BITVEC(binary_stream, 7, 7); + uint64_t i10 = SLICE_BITVEC(binary_stream, 8, 8); + uint64_t i98 = SLICE_BITVEC(binary_stream, 9, 10); + uint64_t i4 = SLICE_BITVEC(binary_stream, 11, 11); + uint64_t i11 = SLICE_BITVEC(binary_stream, 12, 12); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_J; + tree->ast_node.c_j = (i11 << 10) | (i10 << 9) | (i98 << 7) | (i7 << 6) | + (i6 << 5) | (i5 << 4) | (i4 << 3) | i31; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_BEQZ------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x6) { + uint64_t i5 = SLICE_BITVEC(binary_stream, 2, 2); + uint64_t i21 = SLICE_BITVEC(binary_stream, 3, 4); + uint64_t i76 = SLICE_BITVEC(binary_stream, 5, 6); + uint64_t rs = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t i43 = SLICE_BITVEC(binary_stream, 10, 11); + uint64_t i8 = SLICE_BITVEC(binary_stream, 12, 12); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_BEQZ; + tree->ast_node.c_beqz.imm = + (i8 << 7) | (i76 << 5) | (i5 << 4) | (i43 << 2) | i21; + tree->ast_node.c_beqz.rs = rs; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_BNEZ------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x7) { + uint64_t i5 = SLICE_BITVEC(binary_stream, 2, 2); + uint64_t i21 = SLICE_BITVEC(binary_stream, 3, 4); + uint64_t i76 = SLICE_BITVEC(binary_stream, 5, 6); + uint64_t rs = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t i43 = SLICE_BITVEC(binary_stream, 10, 11); + uint64_t i8 = SLICE_BITVEC(binary_stream, 12, 12); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_BNEZ; + tree->ast_node.c_bnez.imm = + (i8 << 7) | (i76 << 5) | (i5 << 4) | (i43 << 2) | i21; + tree->ast_node.c_bnez.rs = rs; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SLLI------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x0) { + uint64_t nzui40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t nzui5 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(((nzui40 << 1) | nzui5) == 0x00)) && + ((!(rsd == ctx->zreg)) && (((ctx->xlen == 64) || (nzui5 == 0x0)) && + (currentlyEnabled(RISCV_Ext_Zca, ctx))))) { + tree->ast_node_type = RISCV_C_SLLI; + tree->ast_node.c_slli.shamt = (nzui5 << 5) | nzui40; + tree->ast_node.c_slli.rsd = rsd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LWSP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x2) { + uint64_t ui76 = SLICE_BITVEC(binary_stream, 2, 3); + uint64_t ui42 = SLICE_BITVEC(binary_stream, 4, 6); + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t ui5 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(rd == ctx->zreg)) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_LWSP; + tree->ast_node.c_lwsp.uimm = (ui76 << 4) | (ui5 << 3) | ui42; + tree->ast_node.c_lwsp.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LDSP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x3) { + uint64_t ui86 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui43 = SLICE_BITVEC(binary_stream, 5, 6); + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t ui5 = SLICE_BITVEC(binary_stream, 12, 12); + if ((!(rd == ctx->zreg)) && + ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_Zca, ctx)))) { + tree->ast_node_type = RISCV_C_LDSP; + tree->ast_node.c_ldsp.uimm = (ui86 << 3) | (ui5 << 2) | ui43; + tree->ast_node.c_ldsp.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SWSP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x6) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t ui76 = SLICE_BITVEC(binary_stream, 7, 8); + uint64_t ui52 = SLICE_BITVEC(binary_stream, 9, 12); + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_SWSP; + tree->ast_node.c_swsp.uimm = (ui76 << 4) | ui52; + tree->ast_node.c_swsp.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SDSP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x7) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t ui86 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if ((ctx->xlen == 64) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_SDSP; + tree->ast_node.c_sdsp.uimm = (ui86 << 3) | ui53; + tree->ast_node.c_sdsp.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_JR------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 2, 6) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 11); + if ((!(rs1 == ctx->zreg)) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_JR; + tree->ast_node.c_jr = rs1; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_JALR------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 2, 6) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 11); + if ((!(rs1 == ctx->zreg)) && (currentlyEnabled(RISCV_Ext_Zca, ctx))) { + tree->ast_node_type = RISCV_C_JALR; + tree->ast_node.c_jalr = rs1; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_MV------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + if ((!(rd == ctx->zreg)) && + ((!(rs2 == ctx->zreg)) && (currentlyEnabled(RISCV_Ext_Zca, ctx)))) { + tree->ast_node_type = RISCV_C_MV; + tree->ast_node.c_mv.rd = rd; + tree->ast_node.c_mv.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_EBREAK------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 2, 6) == 0x00 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + if (currentlyEnabled(RISCV_Ext_Zca, ctx)) { + tree->ast_node_type = RISCV_C_EBREAK; + ; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ADD------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 11); + if ((!(rsd == ctx->zreg)) && + ((!(rs2 == ctx->zreg)) && (currentlyEnabled(RISCV_Ext_Zca, ctx)))) { + tree->ast_node_type = RISCV_C_ADD; + tree->ast_node.c_add.rsd = rsd; + tree->ast_node.c_add.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_NOP_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x0) { + uint64_t im40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t im5 = SLICE_BITVEC(binary_stream, 12, 12); + if (!(((im40 << 1) | im5) == 0x00)) { + tree->ast_node_type = RISCV_C_NOP_HINT; + tree->ast_node.c_nop_hint = (im5 << 5) | im40; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ADDI_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 6) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x0) { + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 11); + if (!(rsd == ctx->zreg)) { + tree->ast_node_type = RISCV_C_ADDI_HINT; + tree->ast_node.c_addi_hint = rsd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LI_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x2) { + uint64_t imm40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t imm5 = SLICE_BITVEC(binary_stream, 12, 12); + tree->ast_node_type = RISCV_C_LI_HINT; + tree->ast_node.c_li_hint = (imm5 << 5) | imm40; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LUI_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x3) { + uint64_t imm1612 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t imm17 = SLICE_BITVEC(binary_stream, 12, 12); + if (!(((imm1612 << 1) | imm17) == 0x00)) { + tree->ast_node_type = RISCV_C_LUI_HINT; + tree->ast_node.c_lui_hint = (imm17 << 5) | imm1612; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_MV_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 6); + if (!(rs2 == ctx->zreg)) { + tree->ast_node_type = RISCV_C_MV_HINT; + tree->ast_node.c_mv_hint = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ADD_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 7, 11) == 0x00 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 6); + if (!(rs2 == ctx->zreg)) { + tree->ast_node_type = RISCV_C_ADD_HINT; + tree->ast_node.c_add_hint = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SLLI_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x0) { + uint64_t nzui40 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t nzui5 = SLICE_BITVEC(binary_stream, 12, 12); + if (((((nzui40 << 1) | nzui5) == 0x00) || (rsd == ctx->zreg)) && + ((ctx->xlen == 64) || (nzui5 == 0x0))) { + tree->ast_node_type = RISCV_C_SLLI_HINT; + tree->ast_node.c_slli_hint.shamt = (nzui5 << 5) | nzui40; + tree->ast_node.c_slli_hint.rsd = rsd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SRLI_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 6) == 0x00 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x0 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + tree->ast_node_type = RISCV_C_SRLI_HINT; + tree->ast_node.c_srli_hint = rsd; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SRAI_HINT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 6) == 0x00 && + SLICE_BITVEC(binary_stream, 10, 11) == 0x1 && + SLICE_BITVEC(binary_stream, 12, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rsd = SLICE_BITVEC(binary_stream, 7, 9); + tree->ast_node_type = RISCV_C_SRAI_HINT; + tree->ast_node.c_srai_hint = rsd; + return; + } + //------------------------------------------------------------------------------------// + + //----------------------------C_FLWSP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x3) { + uint64_t ui76 = SLICE_BITVEC(binary_stream, 2, 3); + uint64_t ui42 = SLICE_BITVEC(binary_stream, 4, 6); + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t ui5 = SLICE_BITVEC(binary_stream, 12, 12); + if (currentlyEnabled(RISCV_Ext_Zcf, ctx)) { + tree->ast_node_type = RISCV_C_FLWSP; + tree->ast_node.c_flwsp.imm = (ui76 << 4) | (ui5 << 3) | ui42; + tree->ast_node.c_flwsp.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_FSWSP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x7) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t ui76 = SLICE_BITVEC(binary_stream, 7, 8); + uint64_t ui52 = SLICE_BITVEC(binary_stream, 9, 12); + if (currentlyEnabled(RISCV_Ext_Zcf, ctx)) { + tree->ast_node_type = RISCV_C_FSWSP; + tree->ast_node.c_fswsp.uimm = (ui76 << 4) | ui52; + tree->ast_node.c_fswsp.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_FLW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x3) { + uint64_t rd = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui6 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t ui2 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if (currentlyEnabled(RISCV_Ext_Zcf, ctx)) { + tree->ast_node_type = RISCV_C_FLW; + tree->ast_node.c_flw.uimm = (ui6 << 4) | (ui53 << 1) | ui2; + tree->ast_node.c_flw.rsc = rs1; + tree->ast_node.c_flw.rdc = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_FSW------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x7) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui6 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t ui2 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if (currentlyEnabled(RISCV_Ext_Zcf, ctx)) { + tree->ast_node_type = RISCV_C_FSW; + tree->ast_node.c_fsw.uimm = (ui6 << 4) | (ui53 << 1) | ui2; + tree->ast_node.c_fsw.rsc1 = rs1; + tree->ast_node.c_fsw.rsc2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_FLDSP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x1) { + uint64_t ui86 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui43 = SLICE_BITVEC(binary_stream, 5, 6); + uint64_t rd = SLICE_BITVEC(binary_stream, 7, 11); + uint64_t ui5 = SLICE_BITVEC(binary_stream, 12, 12); + if (currentlyEnabled(RISCV_Ext_Zcd, ctx)) { + tree->ast_node_type = RISCV_C_FLDSP; + tree->ast_node.c_fldsp.uimm = (ui86 << 3) | (ui5 << 2) | ui43; + tree->ast_node.c_fldsp.rd = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_FSDSP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x5) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 6); + uint64_t ui86 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if (currentlyEnabled(RISCV_Ext_Zcd, ctx)) { + tree->ast_node_type = RISCV_C_FSDSP; + tree->ast_node.c_fsdsp.uimm = (ui86 << 3) | ui53; + tree->ast_node.c_fsdsp.rs2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_FLD------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x1) { + uint64_t rd = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui76 = SLICE_BITVEC(binary_stream, 5, 6); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if (currentlyEnabled(RISCV_Ext_Zcd, ctx)) { + tree->ast_node_type = RISCV_C_FLD; + tree->ast_node.c_fld.uimm = (ui76 << 3) | ui53; + tree->ast_node.c_fld.rsc = rs1; + tree->ast_node.c_fld.rdc = rd; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_FSD------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x5) { + uint64_t rs2 = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t ui76 = SLICE_BITVEC(binary_stream, 5, 6); + uint64_t rs1 = SLICE_BITVEC(binary_stream, 7, 9); + uint64_t ui53 = SLICE_BITVEC(binary_stream, 10, 12); + if (currentlyEnabled(RISCV_Ext_Zcd, ctx)) { + tree->ast_node_type = RISCV_C_FSD; + tree->ast_node.c_fsd.uimm = (ui76 << 3) | ui53; + tree->ast_node.c_fsd.rsc1 = rs1; + tree->ast_node.c_fsd.rsc2 = rs2; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LBU------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x0 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rdc = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t uimm1 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t uimm0 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t rs1c = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zcb, ctx)) { + tree->ast_node_type = RISCV_C_LBU; + tree->ast_node.c_lbu.uimm = (uimm1 << 1) | uimm0; + tree->ast_node.c_lbu.rdc = rdc; + tree->ast_node.c_lbu.rs1c = rs1c; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LHU------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 6, 6) == 0x0 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rdc = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t uimm1 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t rs1c = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zcb, ctx)) { + tree->ast_node_type = RISCV_C_LHU; + tree->ast_node.c_lhu.uimm = (uimm1 << 4) | 0x0; + tree->ast_node.c_lhu.rdc = rdc; + tree->ast_node.c_lhu.rs1c = rs1c; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_LH------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 6, 6) == 0x1 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x1 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rdc = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t uimm1 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t rs1c = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zcb, ctx)) { + tree->ast_node_type = RISCV_C_LH; + tree->ast_node.c_lh.uimm = (uimm1 << 4) | 0x0; + tree->ast_node.c_lh.rdc = rdc; + tree->ast_node.c_lh.rs1c = rs1c; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SB------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x2 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2c = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t uimm1 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t uimm0 = SLICE_BITVEC(binary_stream, 6, 6); + uint64_t rs1c = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zcb, ctx)) { + tree->ast_node_type = RISCV_C_SB; + tree->ast_node.c_sb.uimm = (uimm1 << 1) | uimm0; + tree->ast_node.c_sb.rs1c = rs1c; + tree->ast_node.c_sb.rs2c = rs2c; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SH------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x0 && + SLICE_BITVEC(binary_stream, 6, 6) == 0x0 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x3 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2c = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t uimm1 = SLICE_BITVEC(binary_stream, 5, 5); + uint64_t rs1c = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zcb, ctx)) { + tree->ast_node_type = RISCV_C_SH; + tree->ast_node.c_sh.uimm = (uimm1 << 4) | 0x0; + tree->ast_node.c_sh.rs1c = rs1c; + tree->ast_node.c_sh.rs2c = rs2c; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ZEXT_B------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 4) == 0x0 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x3 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x7 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rsdc = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zcb, ctx)) { + tree->ast_node_type = RISCV_C_ZEXT_B; + tree->ast_node.c_zext_b = rsdc; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SEXT_B------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 4) == 0x1 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x3 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x7 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rsdc = SLICE_BITVEC(binary_stream, 7, 9); + if ((currentlyEnabled(RISCV_Ext_Zcb, ctx)) && + (currentlyEnabled(RISCV_Ext_Zbb, ctx))) { + tree->ast_node_type = RISCV_C_SEXT_B; + tree->ast_node.c_sext_b = rsdc; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ZEXT_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 4) == 0x2 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x3 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x7 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rsdc = SLICE_BITVEC(binary_stream, 7, 9); + if ((currentlyEnabled(RISCV_Ext_Zcb, ctx)) && + (currentlyEnabled(RISCV_Ext_Zbb, ctx))) { + tree->ast_node_type = RISCV_C_ZEXT_H; + tree->ast_node.c_zext_h = rsdc; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_SEXT_H------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 4) == 0x3 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x3 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x7 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rsdc = SLICE_BITVEC(binary_stream, 7, 9); + if ((currentlyEnabled(RISCV_Ext_Zcb, ctx)) && + (currentlyEnabled(RISCV_Ext_Zbb, ctx))) { + tree->ast_node_type = RISCV_C_SEXT_H; + tree->ast_node.c_sext_h = rsdc; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ZEXT_W------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 4) == 0x4 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x3 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x7 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rsdc = SLICE_BITVEC(binary_stream, 7, 9); + if ((currentlyEnabled(RISCV_Ext_Zcb, ctx)) && + ((currentlyEnabled(RISCV_Ext_Zba, ctx)) && (ctx->xlen == 64))) { + tree->ast_node_type = RISCV_C_ZEXT_W; + tree->ast_node.c_zext_w = rsdc; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_NOT------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 4) == 0x5 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x3 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x7 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rsdc = SLICE_BITVEC(binary_stream, 7, 9); + if (currentlyEnabled(RISCV_Ext_Zcb, ctx)) { + tree->ast_node_type = RISCV_C_NOT; + tree->ast_node.c_not = rsdc; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_MUL------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 5, 6) == 0x2 && + SLICE_BITVEC(binary_stream, 10, 12) == 0x7 && + SLICE_BITVEC(binary_stream, 13, 15) == 0x4) { + uint64_t rs2c = SLICE_BITVEC(binary_stream, 2, 4); + uint64_t rsdc = SLICE_BITVEC(binary_stream, 7, 9); + if ((currentlyEnabled(RISCV_Ext_Zcb, ctx)) && + ((currentlyEnabled(RISCV_Ext_M, ctx)) || + (currentlyEnabled(RISCV_Ext_Zmmul, ctx)))) { + tree->ast_node_type = RISCV_C_MUL; + tree->ast_node.c_mul.rsdc = rsdc; + tree->ast_node.c_mul.rs2c = rs2c; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------ZCMOP------------------------------// + if (SLICE_BITVEC(binary_stream, 0, 1) == 0x1 && + SLICE_BITVEC(binary_stream, 2, 7) == 0x20 && + SLICE_BITVEC(binary_stream, 11, 15) == 0x0C) { + uint64_t mop = SLICE_BITVEC(binary_stream, 8, 10); + if (currentlyEnabled(RISCV_Ext_Zcmop, ctx)) { + tree->ast_node_type = RISCV_ZCMOP; + tree->ast_node.zcmop = mop; + return; + } + } + //------------------------------------------------------------------------------------// + + //----------------------------C_ILLEGAL------------------------------// + { + uint64_t s = SLICE_BITVEC(binary_stream, 0, 31); + tree->ast_node_type = RISCV_C_ILLEGAL; + tree->ast_node.c_illegal = s; + return; + } + //------------------------------------------------------------------------------------// +} +#endif diff --git a/arch/RISCV/RISCVDecodeHelpers.h b/arch/RISCV/RISCVDecodeHelpers.h new file mode 100644 index 0000000000..56174619f7 --- /dev/null +++ b/arch/RISCV/RISCVDecodeHelpers.h @@ -0,0 +1,432 @@ +#ifndef __RISCV_DECODE_HELPERS_H__ +#define __RISCV_DECODE_HELPERS_H__ + +#include "RISCVRVContextHelpers.h" + +#include + +#include "RISCVAst.gen.inc" + +typedef enum ExtensionType { + // Integer Multiplication and Division; not Machine! + RISCV_Ext_M = 1ULL << 0, + // Atomic Instructions + RISCV_Ext_A = 1ULL << 1, + // Single-Precision Floating-Point + RISCV_Ext_F = 1ULL << 2, + // Double-Precision Floating-Point + RISCV_Ext_D = 1ULL << 3, + // Compressed Instructions + RISCV_Ext_C = 1ULL << 4, + // Bit Manipulation + RISCV_Ext_B = 1ULL << 5, + // Vector Operations + RISCV_Ext_V = 1ULL << 6, + // Supervisor + RISCV_Ext_S = 1ULL << 7, + // User + RISCV_Ext_U = 1ULL << 8, + // Cache-Block Management Instructions + RISCV_Ext_Zicbom = 1ULL << 9, + // Cache-Block Zero Instructions + RISCV_Ext_Zicboz = 1ULL << 10, + // Base Counters and Timers + RISCV_Ext_Zicntr = 1ULL << 11, + // Integer Conditional Operations + RISCV_Ext_Zicond = 1ULL << 12, + // Instruction-Fetch Fence + RISCV_Ext_Zifencei = 1ULL << 13, + // Hardware Performance Counters + RISCV_Ext_Zihpm = 1ULL << 14, + // May-Be-Operations + RISCV_Ext_Zimop = 1ULL << 15, + // Multiplication and Division: Multiplication only + RISCV_Ext_Zmmul = 1ULL << 16, + // Atomic Memory Operations + RISCV_Ext_Zaamo = 1ULL << 17, + // Byte and Halfword Atomic Memory Operations + RISCV_Ext_Zabha = 1ULL << 18, + // Load-Reserved/Store-Conditional Instructions + RISCV_Ext_Zalrsc = 1ULL << 19, + // Additional Floating-Point Instructions + RISCV_Ext_Zfa = 1ULL << 20, + // Half-Precision Floating-Point + RISCV_Ext_Zfh = 1ULL << 21, + // Minimal Half-Precision Floating-Point + RISCV_Ext_Zfhmin = 1ULL << 22, + // Floating-Point in Integer Registers (single precision) + RISCV_Ext_Zfinx = 1ULL << 23, + // Floating-Point in Integer Registers (double precision) + RISCV_Ext_Zdinx = 1ULL << 24, + // Code Size Reduction: compressed instructions excluding floating point loads + // and stores + RISCV_Ext_Zca = 1ULL << 25, + // Code Size Reduction: additional 16-bit aliases + RISCV_Ext_Zcb = 1ULL << 26, + // Code Size Reduction: compressed double precision floating point loads and + // stores + RISCV_Ext_Zcd = 1ULL << 27, + // Code Size Reduction: compressed single precision floating point loads and + // stores + RISCV_Ext_Zcf = 1ULL << 28, + // Compressed May-Be-Operations + RISCV_Ext_Zcmop = 1ULL << 29, + // Bit Manipulation: Address generation + RISCV_Ext_Zba = 1ULL << 30, + // Bit Manipulation: Basic bit-manipulation + RISCV_Ext_Zbb = 1ULL << 31, + // Bit Manipulation: Carry-less multiplication + RISCV_Ext_Zbc = 1ULL << 32, + // Bit Manipulation: Bit-manipulation for Cryptography + RISCV_Ext_Zbkb = 1ULL << 33, + // Bit Manipulation: Carry-less multiplication for Cryptography + RISCV_Ext_Zbkc = 1ULL << 34, + // Bit Manipulation: Crossbar permutations + RISCV_Ext_Zbkx = 1ULL << 35, + // Bit Manipulation: Single-bit instructions + RISCV_Ext_Zbs = 1ULL << 36, + // Scalar & Entropy Source Instructions: NIST Suite: AES Decryption + RISCV_Ext_Zknd = 1ULL << 37, + // Scalar & Entropy Source Instructions: NIST Suite: AES Encryption + RISCV_Ext_Zkne = 1ULL << 38, + // Scalar & Entropy Source Instructions: NIST Suite: Hash Function + // Instructions + RISCV_Ext_Zknh = 1ULL << 39, + // Scalar & Entropy Source Instructions: Entropy Source ExtensionType + RISCV_Ext_Zkr = 1ULL << 40, + // Scalar & Entropy Source Instructions: ShangMi Suite: SM4 Block Cipher + // Instructions + RISCV_Ext_Zksed = 1ULL << 41, + // Scalar & Entropy Source Instructions: ShangMi Suite: SM3 Hash Cipher + // Instructions + RISCV_Ext_Zksh = 1ULL << 42, + // Floating-Point in Integer Registers (half precision) + RISCV_Ext_Zhinx = 1ULL << 43, + // Supervisor-mode Timer Interrupts + RISCV_Ext_Sstc = 1ULL << 44, + // Fine-Grained Address-Translation Cache Invalidation + RISCV_Ext_Svinval = 1ULL << 45, + // Vector Basic Bit-manipulation + RISCV_Ext_Zvbb = 1ULL << 46, + // Vector Cryptography Bit-manipulation + RISCV_Ext_Zvkb = 1ULL << 47, + // Vector Carryless Multiplication + RISCV_Ext_Zvbc = 1ULL << 48, + RISCV_Ext_Zvknhb = 1ULL << 49, + // NIST Suite: Vector SHA-2 Secure Hash + RISCV_Ext_Zvknha = 1ULL << 50, + // Count Overflow and Mode-Based Filtering + RISCV_Ext_Sscofpmf = 1ULL << 51, + // NAPOT Translation Contiguity + RISCV_Ext_Svnapot = 1ULL << 52, + // Page-Based Memory Types + RISCV_Ext_Svpbmt = 1ULL << 53, + // Cycle and Instret Privilege Mode Filtering + RISCV_Ext_Smcntrpmf = 1ULL << 54 +} ExtensionType; + +#define HART_SUPPORTS(e) (ctx->extensionsSupported & RISCV_##e) + +static inline bool currentlyEnabled(ExtensionType t, RVContext *ctx) { + switch (t) { + case RISCV_Ext_M: + return HART_SUPPORTS(Ext_M) && MISA(M) == 1; + case RISCV_Ext_A: + return HART_SUPPORTS(Ext_A) && MISA(A) == 1; + case RISCV_Ext_F: + return HART_SUPPORTS(Ext_F) && MISA(F) == 1 && MSTATUS(FS) != 0; + case RISCV_Ext_D: + return HART_SUPPORTS(Ext_D) && MISA(D) == 1 && MSTATUS(FS) != 0 && + ctx->flen >= 64; + case RISCV_Ext_C: + return HART_SUPPORTS(Ext_C) && MISA(C) == 1; + case RISCV_Ext_B: + return HART_SUPPORTS(Ext_B) && MISA(B) == 1; + case RISCV_Ext_V: + return HART_SUPPORTS(Ext_V) && MISA(V) == 1 && MSTATUS(VS) != 0; + case RISCV_Ext_S: + return HART_SUPPORTS(Ext_S) && MISA(S) == 1; + case RISCV_Ext_U: + return HART_SUPPORTS(Ext_U) && MISA(U) == 1; + case RISCV_Ext_Zicbom: + return HART_SUPPORTS(Ext_Zicbom); + case RISCV_Ext_Zicboz: + return HART_SUPPORTS(Ext_Zicboz); + case RISCV_Ext_Zicntr: + return HART_SUPPORTS(Ext_Zicntr); + case RISCV_Ext_Zicond: + return HART_SUPPORTS(Ext_Zicond); + case RISCV_Ext_Zifencei: + return HART_SUPPORTS(Ext_Zifencei); + case RISCV_Ext_Zihpm: + return HART_SUPPORTS(Ext_Zihpm) && currentlyEnabled(RISCV_Ext_Zicntr, ctx); + case RISCV_Ext_Zimop: + return HART_SUPPORTS(Ext_Zimop); + case RISCV_Ext_Zmmul: + return HART_SUPPORTS(Ext_Zmmul) || currentlyEnabled(RISCV_Ext_M, ctx); + case RISCV_Ext_Zaamo: + return HART_SUPPORTS(Ext_Zaamo) || currentlyEnabled(RISCV_Ext_A, ctx); + + case RISCV_Ext_Zabha: + return HART_SUPPORTS(Ext_Zabha) && currentlyEnabled(RISCV_Ext_Zaamo, ctx); + case RISCV_Ext_Zalrsc: + return HART_SUPPORTS(Ext_Zalrsc) || currentlyEnabled(RISCV_Ext_A, ctx); + case RISCV_Ext_Zfa: + return HART_SUPPORTS(Ext_Zfa) && currentlyEnabled(RISCV_Ext_F, ctx); + case RISCV_Ext_Zfh: + return HART_SUPPORTS(Ext_Zfh) && currentlyEnabled(RISCV_Ext_F, ctx); + case RISCV_Ext_Zfhmin: + return (HART_SUPPORTS(Ext_Zfhmin) && currentlyEnabled(RISCV_Ext_F, ctx)) || + currentlyEnabled(RISCV_Ext_Zfh, ctx); + // function clause currentlyEnabled(Ext_Zfinx) = sys_enable_zfinx() + case RISCV_Ext_Zfinx: + return HART_SUPPORTS(Ext_Zfinx); + case RISCV_Ext_Zdinx: + return HART_SUPPORTS(Ext_Zdinx) && ctx->flen >= 64; + case RISCV_Ext_Zca: + return HART_SUPPORTS(Ext_Zca) && + (currentlyEnabled(RISCV_Ext_C, ctx) || !HART_SUPPORTS(Ext_C)); + case RISCV_Ext_Zcb: + return HART_SUPPORTS(Ext_Zcb) && currentlyEnabled(RISCV_Ext_Zca, ctx); + case RISCV_Ext_Zcd: + return HART_SUPPORTS(Ext_Zcd) && currentlyEnabled(RISCV_Ext_Zca, ctx) && + currentlyEnabled(RISCV_Ext_D, ctx) && + (currentlyEnabled(RISCV_Ext_C, ctx) || !HART_SUPPORTS(Ext_C)); + case RISCV_Ext_Zcf: + return HART_SUPPORTS(Ext_Zcf) && currentlyEnabled(RISCV_Ext_Zca, ctx) && + currentlyEnabled(RISCV_Ext_F, ctx) && + (currentlyEnabled(RISCV_Ext_C, ctx) || !HART_SUPPORTS(Ext_C)); + case RISCV_Ext_Zcmop: + return HART_SUPPORTS(Ext_Zcmop) && currentlyEnabled(RISCV_Ext_Zca, ctx); + case RISCV_Ext_Zba: + return HART_SUPPORTS(Ext_Zba) || currentlyEnabled(RISCV_Ext_B, ctx); + case RISCV_Ext_Zbb: + return HART_SUPPORTS(Ext_Zbb) || currentlyEnabled(RISCV_Ext_B, ctx); + case RISCV_Ext_Zbc: + return HART_SUPPORTS(Ext_Zbc); + case RISCV_Ext_Zbkb: + return HART_SUPPORTS(Ext_Zbkb); + case RISCV_Ext_Zbkc: + return HART_SUPPORTS(Ext_Zbkc); + case RISCV_Ext_Zbkx: + return HART_SUPPORTS(Ext_Zbkx); + case RISCV_Ext_Zbs: + return HART_SUPPORTS(Ext_Zbs) || currentlyEnabled(RISCV_Ext_B, ctx); + case RISCV_Ext_Zknd: + return HART_SUPPORTS(Ext_Zknd); + case RISCV_Ext_Zkne: + return HART_SUPPORTS(Ext_Zkne); + case RISCV_Ext_Zknh: + return HART_SUPPORTS(Ext_Zknh); + case RISCV_Ext_Zkr: + return HART_SUPPORTS(Ext_Zkr); + case RISCV_Ext_Zksed: + return HART_SUPPORTS(Ext_Zksed); + case RISCV_Ext_Zksh: + return HART_SUPPORTS(Ext_Zksh); + case RISCV_Ext_Zhinx: + return HART_SUPPORTS(Ext_Zhinx) & currentlyEnabled(RISCV_Ext_Zfinx, ctx); + case RISCV_Ext_Sstc: + return HART_SUPPORTS(Ext_Sstc); + case RISCV_Ext_Svinval: + return HART_SUPPORTS(Ext_Svinval); + case RISCV_Ext_Zvbb: + return HART_SUPPORTS(Ext_Zvbb) && currentlyEnabled(RISCV_Ext_V, ctx); + case RISCV_Ext_Zvkb: + return (HART_SUPPORTS(Ext_Zvkb) || currentlyEnabled(RISCV_Ext_Zvbb, ctx)) && + currentlyEnabled(RISCV_Ext_V, ctx); + case RISCV_Ext_Zvbc: + return HART_SUPPORTS(Ext_Zvbc) && currentlyEnabled(RISCV_Ext_V, ctx); + case RISCV_Ext_Zvknhb: + return HART_SUPPORTS(Ext_Zvknhb) && currentlyEnabled(RISCV_Ext_V, ctx); + case RISCV_Ext_Zvknha: + return HART_SUPPORTS(Ext_Zvknha) && currentlyEnabled(RISCV_Ext_V, ctx); + // Not supported in the model yet. + // function clause currentlyEnabled(Ext_Svnapot) = false + // function clause currentlyEnabled(Ext_Svpbmt) = false + case RISCV_Ext_Svnapot: + case RISCV_Ext_Svpbmt: + return 0; + case RISCV_Ext_Sscofpmf: + return HART_SUPPORTS(Ext_Sscofpmf) && + currentlyEnabled(RISCV_Ext_Zihpm, ctx); + case RISCV_Ext_Smcntrpmf: + return HART_SUPPORTS(Ext_Smcntrpmf) && + currentlyEnabled(RISCV_Ext_Zicntr, ctx); + + default: + printf("currentlyEnabled: ERROR! Unknown extension.\n"); + return 0; + } +} + +static inline bool not(bool b, RVContext *ctx) { return !b; } + +static inline uint8_t size_bytes_forwards(enum word_width width, + RVContext *ctx) { + switch (width) { + case RISCV_BYTE: + return 1; + case RISCV_HALF: + return 2; + case RISCV_WORD: + return 4; + case RISCV_DOUBLE: + return 8; + default: + printf("size_bytes_forwards: ERROR! Unhandled word_width case"); + return 0xFF; + } +} + +static inline bool lrsc_width_valid(enum word_width width, RVContext *ctx) { + switch (width) { + case RISCV_WORD: + return 1; + case RISCV_DOUBLE: + return ctx->xlen >= 64; + default: + return 0; + } +} + +static inline bool amo_width_valid(enum word_width width, RVContext *ctx) { + switch (width) { + case RISCV_BYTE: + case RISCV_HALF: + return currentlyEnabled(RISCV_Ext_Zabha, ctx); + case RISCV_WORD: + return 1; + case RISCV_DOUBLE: + return ctx->xlen >= 64; + default: + return 0; + } +} + +static inline bool haveDoubleFPU(RVContext *ctx) { + return currentlyEnabled(RISCV_Ext_D, ctx) || + currentlyEnabled(RISCV_Ext_Zdinx, ctx); +} + +static inline bool haveSingleFPU(RVContext *ctx) { + return currentlyEnabled(RISCV_Ext_F, ctx) || + currentlyEnabled(RISCV_Ext_Zfinx, ctx); +} + +static inline bool haveHalfFPU(RVContext *ctx) { + return currentlyEnabled(RISCV_Ext_Zfh, ctx) || + currentlyEnabled(RISCV_Ext_Zhinx, ctx); +} + +static inline bool haveHalfMin(RVContext *ctx) { + return haveHalfFPU(ctx) || currentlyEnabled(RISCV_Ext_Zfhmin, ctx); +} + +static inline bool in32BitMode(RVContext *ctx) { return ctx->xlen == 32; } + +static inline bool validDoubleRegsN(uint8_t *regs, RVContext *ctx) { + if (currentlyEnabled(RISCV_Ext_Zdinx, ctx) && ctx->xlen == 32) { + for (uint8_t i = 0; regs[i] != 0xff; i++) { + if (regs[i] & 1) { + return 0; + } + } + } + return 1; +} + +#define validDoubleRegs(n, ...) validDoubleRegs##n(__VA_ARGS__) + +static inline bool validDoubleRegs1(uint8_t rs1, RVContext *ctx) { + uint8_t regs[] = {rs1, 0xFF}; + return validDoubleRegsN(regs, ctx); +} + +static inline bool validDoubleRegs2(uint8_t rs1, uint8_t rd, RVContext *ctx) { + uint8_t regs[] = {rs1, rd, 0xFF}; + return validDoubleRegsN(regs, ctx); +} + +static inline bool validDoubleRegs3(uint8_t rs2, uint8_t rs1, uint8_t rd, + RVContext *ctx) { + uint8_t regs[] = {rs2, rs1, rd, 0xFF}; + return validDoubleRegsN(regs, ctx); +} + +static inline bool validDoubleRegs4(uint8_t rs3, uint8_t rs2, uint8_t rs1, + uint8_t rd, RVContext *ctx) { + uint8_t regs[] = {rs3, rs2, rs1, rd, 0xFF}; + return validDoubleRegsN(regs, ctx); +} + +static inline uint32_t get_sew(RVContext *ctx) { + switch (VTYPE(VSEW)) { + case 3: + case 4: + case 5: + case 6: + return 1 << VTYPE(VSEW); + default: + printf( + "get_sew: ERROR!: Invalid vsew field of vector control register vtype"); + return 0; + } +} + +static inline int32_t get_lmul_pow(RVContext *ctx) { + switch (VTYPE(VLMUL)) { + case 0: + case 1: + case 2: + case 3: + return VTYPE(VLMUL); + case 5: + case 6: + case 7: + return VTYPE(VLMUL) - 8; + default: + printf("get_lmul_pow: ERROR!: Invalid vsew field of vector control " + "register vtype"); + return 0; + } +} + +static inline float get_lmul(int32_t lpow) { + if (lpow >= 0) + return 1 << lpow; + + switch (lpow) { + case -3: + return 1.0 / 8.0; + case -2: + return 0.25; + case -1: + return 0.5; + default: + printf("get_lmul: ERROR!: Invalid vsew field, unexpected value"); + } + // any number that appears strange and invalid + return (float)(~0); +} + +static inline bool zvk_check_encdec(int32_t egw, int32_t egs, RVContext *ctx) { + return (ctx->vl % egs == 0) && (ctx->vstart % egs == 0) && + (get_lmul(get_lmul_pow(ctx)) * ctx->vlen >= egw); +} + +static inline bool zvk_valid_reg_overlap(uint8_t rs, uint8_t rd, + int32_t emul_pow) { + uint64_t reg_group_size = (emul_pow > 0) ? 1 << emul_pow : 1; + return (rs + reg_group_size <= rd) || (rd + reg_group_size <= rs); +} +static inline bool zvknhab_check_encdec(uint8_t vs2, uint8_t vs1, uint8_t vd, + RVContext *ctx) { + uint32_t sew = get_sew(ctx); + int32_t lmulpow = get_lmul_pow(ctx); + return zvk_check_encdec(sew, 4, ctx) && + zvk_valid_reg_overlap(vs1, vd, lmulpow) && + zvk_valid_reg_overlap(vs2, vd, lmulpow); +} + +#endif \ No newline at end of file diff --git a/arch/RISCV/RISCVDisassembler.c b/arch/RISCV/RISCVDisassembler.c index 4b81da2aab..995d3e7dba 100644 --- a/arch/RISCV/RISCVDisassembler.c +++ b/arch/RISCV/RISCVDisassembler.c @@ -1,460 +1,47 @@ -//===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -/* Capstone Disassembly Engine */ -/* RISC-V Backend By Rodrigo Cortes Porto & - Shawn Chang , HardenedLinux@2018 */ - -#ifdef CAPSTONE_HAS_RISCV - -#include // DEBUG -#include -#include +#include "RISCVDisassembler.h" +#include "RISCVHelpers.h" +#include "RISCVDecode.gen.inc" +#include "RISCVDecodeCompressed.gen.inc" +#include "RISCVInsnMappings.gen.inc" +#include "RISCVOperands.gen.inc" #include "../../cs_priv.h" #include "../../utils.h" -#include "../../MCInst.h" -#include "../../MCInstrDesc.h" -#include "../../MCFixedLenDisassembler.h" -#include "../../MCRegisterInfo.h" -#include "../../MCDisassembler.h" -#include "../../MathExtras.h" -#include "../../Mapping.h" -#include "RISCVBaseInfo.h" -#include "RISCVDisassembler.h" - - -/* Need the feature infos define in - RISCVGenSubtargetInfo.inc. */ -#define GET_SUBTARGETINFO_ENUM -#include "RISCVGenSubtargetInfo.inc" - -/* When we specify the RISCV64 mode, It means It is RV64IMAFD. - Similar, RISCV32 means RV32IMAFD. -*/ -static uint64_t getFeatureBits(int mode) -{ - uint64_t ret = RISCV_FeatureStdExtM | RISCV_FeatureStdExtA | - RISCV_FeatureStdExtF | RISCV_FeatureStdExtD ; - - if (mode & CS_MODE_RISCV64) - ret |= RISCV_Feature64Bit; - if (mode & CS_MODE_RISCVC) - ret |= RISCV_FeatureStdExtC; - - return ret; -} - -#define GET_REGINFO_ENUM -#define GET_REGINFO_MC_DESC -#include "RISCVGenRegisterInfo.inc" -#define GET_INSTRINFO_ENUM -#include "RISCVGenInstrInfo.inc" - -static const unsigned GPRDecoderTable[] = { - RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, - RISCV_X4, RISCV_X5, RISCV_X6, RISCV_X7, - RISCV_X8, RISCV_X9, RISCV_X10, RISCV_X11, - RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, - RISCV_X16, RISCV_X17, RISCV_X18, RISCV_X19, - RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, - RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, - RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31 -}; - -static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo >= ARR_SIZE(GPRDecoderTable)) - return MCDisassembler_Fail; - - // We must define our own mapping from RegNo to register identifier. - // Accessing index RegNo in the register class will work in the case that - // registers were added in ascending order, but not in general. - Reg = GPRDecoderTable[RegNo]; - //Inst.addOperand(MCOperand::createReg(Reg)); - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static const unsigned FPR32DecoderTable[] = { - RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, - RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, - RISCV_F8_32, RISCV_F9_32, RISCV_F10_32, RISCV_F11_32, - RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, - RISCV_F16_32, RISCV_F17_32, RISCV_F18_32, RISCV_F19_32, - RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, - RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32, - RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32 -}; - -static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo >= ARR_SIZE(FPR32DecoderTable)) - return MCDisassembler_Fail; - - // We must define our own mapping from RegNo to register identifier. - // Accessing index RegNo in the register class will work in the case that - // registers were added in ascending order, but not in general. - Reg = FPR32DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > 8) - return MCDisassembler_Fail; - Reg = FPR32DecoderTable[RegNo + 8]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static const unsigned FPR64DecoderTable[] = { - RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, - RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, - RISCV_F8_64, RISCV_F9_64, RISCV_F10_64, RISCV_F11_64, - RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, - RISCV_F16_64, RISCV_F17_64, RISCV_F18_64, RISCV_F19_64, - RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, - RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64, - RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64 -}; - -static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo >= ARR_SIZE(FPR64DecoderTable)) - return MCDisassembler_Fail; - - // We must define our own mapping from RegNo to register identifier. - // Accessing index RegNo in the register class will work in the case that - // registers were added in ascending order, but not in general. - Reg = FPR64DecoderTable[RegNo]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > 8) - return MCDisassembler_Fail; - Reg = FPR64DecoderTable[RegNo + 8]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - if (RegNo == 0) - return MCDisassembler_Fail; - return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - if (RegNo == 2) - return MCDisassembler_Fail; - return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, - uint64_t Address, - const void *Decoder) -{ - unsigned Reg = 0; - - if (RegNo > 8) - return MCDisassembler_Fail; - - Reg = GPRDecoderTable[RegNo + 8]; - MCOperand_CreateReg0(Inst, Reg); - return MCDisassembler_Success; -} - -// Add implied SP operand for instructions *SP compressed instructions. The SP -// operand isn't explicitly encoded in the instruction. -static void addImplySP(MCInst *Inst, int64_t Address, const void *Decoder) -{ - if (MCInst_getOpcode(Inst) == RISCV_C_LWSP || - MCInst_getOpcode(Inst) == RISCV_C_SWSP || - MCInst_getOpcode(Inst) == RISCV_C_LDSP || - MCInst_getOpcode(Inst) == RISCV_C_SDSP || - MCInst_getOpcode(Inst) == RISCV_C_FLWSP || - MCInst_getOpcode(Inst) == RISCV_C_FSWSP || - MCInst_getOpcode(Inst) == RISCV_C_FLDSP || - MCInst_getOpcode(Inst) == RISCV_C_FSDSP || - MCInst_getOpcode(Inst) == RISCV_C_ADDI4SPN) { - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); - } - - if (MCInst_getOpcode(Inst) == RISCV_C_ADDI16SP) { - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); - DecodeGPRRegisterClass(Inst, 2, Address, Decoder); - } -} - -static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder, - unsigned N) -{ - //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); - addImplySP(Inst, Address, Decoder); - //Inst.addOperand(MCOperand::createImm(Imm)); - MCOperand_CreateImm0(Inst, Imm); - return MCDisassembler_Success; -} - -static DecodeStatus decodeUImmNonZeroOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder, - unsigned N) -{ - if (Imm == 0) - return MCDisassembler_Fail; - return decodeUImmOperand(Inst, Imm, Address, Decoder, N); -} - -static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, const void *Decoder, - unsigned N) -{ - //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); - addImplySP(Inst, Address, Decoder); - // Sign-extend the number in the bottom N bits of Imm - //Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); - MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); - return MCDisassembler_Success; -} - -static DecodeStatus decodeSImmNonZeroOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder, - unsigned N) -{ - if (Imm == 0) - return MCDisassembler_Fail; - return decodeSImmOperand(Inst, Imm, Address, Decoder, N); -} - -static DecodeStatus decodeSImmOperandAndLsl1(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder, - unsigned N) -{ - //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); - // Sign-extend the number in the bottom N bits of Imm after accounting for - // the fact that the N bit immediate is stored in N-1 bits (the LSB is - // always zero) - //Inst.addOperand(MCOperand::createImm(SignExtend64(Imm << 1))); - MCOperand_CreateImm0(Inst, SignExtend64(Imm << 1, N)); - return MCDisassembler_Success; -} - -static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder) -{ - //CS_ASSERT(isUInt<6>(Imm) && "Invalid immediate"); - if (Imm > 31) { - Imm = (SignExtend64(Imm, 6) & 0xfffff); - } - //Inst.addOperand(MCOperand::createImm(Imm)); - MCOperand_CreateImm0(Inst, Imm); - return MCDisassembler_Success; -} - -static DecodeStatus decodeFRMArg(MCInst *Inst, uint64_t Imm, - int64_t Address, - const void *Decoder) -{ - //CS_ASSERT(isUInt<3>(Imm) && "Invalid immediate"); - if (!RISCVFPRndMode_isValidRoundingMode(Imm)) - return MCDisassembler_Fail; - - //Inst.addOperand(MCOperand::createImm(Imm)); - MCOperand_CreateImm0(Inst, Imm); - return MCDisassembler_Success; -} - - -#include "RISCVGenDisassemblerTables.inc" - -static void init_MI_insn_detail(MCInst *MI) -{ - if (MI->flat_insn->detail) { - memset(MI->flat_insn->detail, 0, sizeof(cs_detail)); - } - - return; -} - -// mark the load/store instructions through the opcode. -static void markLSInsn(MCInst *MI, uint32_t in) -{ - /* - I ld 0000011 = 0x03 - st 0100011 = 0x23 - F/D ld 0000111 = 0x07 - st 0100111 = 0x27 - st 0101111 = 0x2f - */ -#define MASK_LS_INSN 0x0000007f - uint32_t opcode = in & MASK_LS_INSN; - if (0 == (opcode ^ 0x03) || 0 == (opcode ^ 0x07) || - 0 == (opcode ^ 0x23) || 0 == (opcode ^ 0x27) || - 0 == (opcode ^ 0x2f)) - MI->flat_insn->detail->riscv.need_effective_addr = true; -#undef MASK_LS_INSN - return; -} - -static void markCLSInsn(MCInst *MI, uint32_t in) -{ - // Unfortunately there is no obvious pattern in terms of RISC-V C instructions - // Thus, we compare the instruction IDs to see if it is a load/store instruction - unsigned id = MCInst_getOpcode(MI); - if (id == RISCV_C_FLD || id == RISCV_C_LW || - id == RISCV_C_FLW || id == RISCV_C_LD || - id == RISCV_C_FSD || id == RISCV_C_SW || - id == RISCV_C_FSW || id == RISCV_C_SD || - id == RISCV_C_FLDSP || id == RISCV_C_LWSP || - id == RISCV_C_FLWSP || id == RISCV_C_LDSP || - id == RISCV_C_FSDSP || id == RISCV_C_SWSP || - id == RISCV_C_FSWSP || id == RISCV_C_SDSP) { - RISCV_get_detail(MI)->need_effective_addr = true; - } - return; -} - -static DecodeStatus RISCVDisassembler_getInstruction(int mode, MCInst *MI, - const uint8_t *code, size_t code_len, - uint16_t *Size, uint64_t Address, - MCRegisterInfo *MRI) -{ - // TODO: This will need modification when supporting instruction set - // extensions with instructions > 32-bits (up to 176 bits wide). - uint32_t Inst = 0; - DecodeStatus Result; - - // It's a 32 bit instruction if bit 0 and 1 are 1. - if ((code[0] & 0x3) == 0x3) { - if (code_len < 4) { - *Size = 0; - return MCDisassembler_Fail; - } - - *Size = 4; - // Get the four bytes of the instruction. - //Encoded as little endian 32 bits. - Inst = code[0] | (code[1] << 8) | (code[2] << 16) | ((uint32_t)code[3] << 24); - init_MI_insn_detail(MI); - // Now we need mark what instruction need fix effective address output. - if (MI->csh->detail_opt) - markLSInsn(MI, Inst); - Result = decodeInstruction(DecoderTable32, MI, Inst, Address, MRI, mode); - } else { - if (code_len < 2) { - *Size = 0; - return MCDisassembler_Fail; - } - - // If not b4bit. - if (! (getFeatureBits(mode) & ((uint64_t)RISCV_Feature64Bit))) { - // Trying RISCV32Only_16 table (16-bit Instruction) - Inst = code[0] | (code[1] << 8); - init_MI_insn_detail(MI); - Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Inst, Address, - MRI, mode); - if (Result != MCDisassembler_Fail) { - *Size = 2; - return Result; - } - } +bool riscv_get_instruction(csh handle, + const uint8_t *code, size_t code_len, MCInst *instr, + uint16_t *size, uint64_t address, void *info) { + cs_insn *insn = instr->flat_insn; + + int sz = riscv_get_instruction_size(code[0]); + + RVContext ctx; + riscv_init_riscv_context(&ctx); + + struct ast instruction; + if (sz == 2) { + decode_compressed(&instruction, readBytes16(instr, code), &ctx); + } else if (sz == 4) { + decode(&instruction, readBytes32(instr, code), &ctx); + } else { + printf("RISCVDisassembler.c: Invalid Size %d, RISCV Instructions Are Either 2 Or 4 Bytes\n", sz); + return false; + } + + // VERY HACKY: use op_str as a temporary buffer to serialize the instruction struct + // so that the printer callback can later de-serialize it in order to stringify it + // alternatives: + // (1) duplicating the decoding again in the printer + // (2) doing all the work including decoding in the printer (and not here) + CS_ASSERT(sizeof(struct ast) < 160); + memcpy(insn->op_str, &instruction, sizeof(struct ast)); + + insn->id = get_insn_type(&instruction); + insn->address = address; - // Trying RISCV_C table (16-bit Instruction) - Inst = code[0] | (code[1] << 8); - init_MI_insn_detail(MI); - // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTable16, MI, Inst, Address, MRI, mode); - // Now we need mark what instruction need fix effective address output. - // Note that we mark it AFTER the instruction is decoded - // This is because there is no obvious pattern in terms of RISC-V C instructions - // So we compare the instruction IDs one by one - if (detail_is_set(MI)) - markCLSInsn(MI, Inst); - *Size = 2; - } - - return Result; -} - -bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, - void *info) -{ - cs_struct *handle = (cs_struct *)(uintptr_t)ud; - - return MCDisassembler_Success == - RISCVDisassembler_getInstruction(handle->mode, instr, - code, code_len, - size, address, - (MCRegisterInfo *)info); - -} - -void RISCV_init(MCRegisterInfo * MRI) -{ - /* - InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC, - RISCVMCRegisterClasses, 11, - RISCVRegUnitRoots, - 64, - RISCVRegDiffLists, - RISCVLaneMaskLists, - RISCVRegStrings, - RISCVRegClassStrings, - RISCVSubRegIdxLists, - 2, - RISCVSubRegIdxRanges, - RISCVRegEncodingTable); - */ - - MCRegisterInfo_InitMCRegisterInfo(MRI, RISCVRegDesc, 97, 0, 0, - RISCVMCRegisterClasses, 11, - 0, - 0, - RISCVRegDiffLists, - 0, - RISCVSubRegIdxLists, - 2, - 0); -} + *size = sz; -#endif + fill_operands(&instruction, insn->detail->riscv.operands, &(insn->detail->riscv.op_count)); + patch_operands(&instruction, insn->detail->riscv.operands, &(insn->detail->riscv.op_count), &ctx); + return true; +} \ No newline at end of file diff --git a/arch/RISCV/RISCVDisassembler.h b/arch/RISCV/RISCVDisassembler.h index 1cb70ea7c5..a903adada1 100644 --- a/arch/RISCV/RISCVDisassembler.h +++ b/arch/RISCV/RISCVDisassembler.h @@ -1,18 +1,5 @@ -/* Capstone Disassembly Engine */ -/* RISC-V Backend By Rodrigo Cortes Porto & - Shawn Chang , HardenedLinux@2018 */ - -#ifndef CS_RISCVDISASSEMBLER_H -#define CS_RISCVDISASSEMBLER_H - #include "../../include/capstone/capstone.h" -#include "../../MCRegisterInfo.h" #include "../../MCInst.h" -void RISCV_init(MCRegisterInfo *MRI); - -bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, - void *info); -#endif +bool riscv_get_instruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); \ No newline at end of file diff --git a/arch/RISCV/RISCVGenAsmWriter.inc b/arch/RISCV/RISCVGenAsmWriter.inc deleted file mode 100644 index c8a6aac644..0000000000 --- a/arch/RISCV/RISCVGenAsmWriter.inc +++ /dev/null @@ -1,2661 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* Assembly Writer Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#include // debug -#include -#include - - -/// printInstruction - This method is automatically generated by tablegen -/// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) -{ -#ifndef CAPSTONE_DIET - static const char AsmStrs[] = { - /* 0 */ 'l', 'l', 'a', 9, 0, - /* 5 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0, - /* 17 */ 's', 'r', 'a', 9, 0, - /* 22 */ 'l', 'b', 9, 0, - /* 26 */ 's', 'b', 9, 0, - /* 30 */ 'c', '.', 's', 'u', 'b', 9, 0, - /* 37 */ 'a', 'u', 'i', 'p', 'c', 9, 0, - /* 44 */ 'c', 's', 'r', 'r', 'c', 9, 0, - /* 51 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, - /* 59 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 68 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, - /* 78 */ 's', 'c', '.', 'd', 9, 0, - /* 84 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 92 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 101 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 111 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0, - /* 121 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0, - /* 131 */ 'f', 'l', 'e', '.', 'd', 9, 0, - /* 138 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0, - /* 147 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, - /* 157 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, - /* 165 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, - /* 173 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0, - /* 183 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0, - /* 193 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0, - /* 204 */ 'f', 'e', 'q', '.', 'd', 9, 0, - /* 211 */ 'l', 'r', '.', 'd', 9, 0, - /* 217 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0, - /* 226 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0, - /* 236 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, - /* 246 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, - /* 256 */ 'f', 'l', 't', '.', 'd', 9, 0, - /* 263 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, - /* 272 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0, - /* 283 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0, - /* 294 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0, - /* 305 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0, - /* 316 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, - /* 324 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, - /* 334 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0, - /* 343 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, - /* 351 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0, - /* 361 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0, - /* 371 */ 'c', '.', 'a', 'd', 'd', 9, 0, - /* 378 */ 'c', '.', 'l', 'd', 9, 0, - /* 384 */ 'c', '.', 'f', 'l', 'd', 9, 0, - /* 391 */ 'c', '.', 'a', 'n', 'd', 9, 0, - /* 398 */ 'c', '.', 's', 'd', 9, 0, - /* 404 */ 'c', '.', 'f', 's', 'd', 9, 0, - /* 411 */ 'f', 'e', 'n', 'c', 'e', 9, 0, - /* 418 */ 'b', 'g', 'e', 9, 0, - /* 423 */ 'b', 'n', 'e', 9, 0, - /* 428 */ 'm', 'u', 'l', 'h', 9, 0, - /* 434 */ 's', 'h', 9, 0, - /* 438 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0, - /* 447 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0, - /* 455 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0, - /* 463 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0, - /* 471 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0, - /* 479 */ 'w', 'f', 'i', 9, 0, - /* 484 */ 'c', '.', 'l', 'i', 9, 0, - /* 490 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0, - /* 498 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0, - /* 506 */ 'x', 'o', 'r', 'i', 9, 0, - /* 512 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0, - /* 520 */ 's', 'l', 't', 'i', 9, 0, - /* 526 */ 'c', '.', 'l', 'u', 'i', 9, 0, - /* 533 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0, - /* 541 */ 'c', '.', 'j', 9, 0, - /* 546 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0, - /* 556 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, - /* 566 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, - /* 576 */ 'c', '.', 'j', 'a', 'l', 9, 0, - /* 583 */ 't', 'a', 'i', 'l', 9, 0, - /* 589 */ 'e', 'c', 'a', 'l', 'l', 9, 0, - /* 596 */ 's', 'l', 'l', 9, 0, - /* 601 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0, - /* 610 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0, - /* 623 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0, - /* 636 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0, - /* 649 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0, - /* 663 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0, - /* 672 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, - /* 684 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, - /* 697 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0, - /* 711 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0, - /* 725 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0, - /* 738 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0, - /* 747 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0, - /* 760 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0, - /* 773 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0, - /* 786 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0, - /* 800 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0, - /* 809 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, - /* 821 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, - /* 834 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0, - /* 848 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0, - /* 862 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0, - /* 875 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 886 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 901 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 916 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 931 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 947 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 958 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 972 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 987 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1003 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1019 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1034 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1045 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1060 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1075 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1106 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1117 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1131 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1146 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1162 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1178 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, - /* 1193 */ 's', 'r', 'l', 9, 0, - /* 1198 */ 'm', 'u', 'l', 9, 0, - /* 1203 */ 'r', 'e', 'm', 9, 0, - /* 1208 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0, - /* 1220 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0, - /* 1231 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0, - /* 1240 */ 'c', '.', 'n', 'o', 'p', 9, 0, - /* 1247 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0, - /* 1259 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0, - /* 1267 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0, - /* 1276 */ 'c', '.', 's', 'd', 's', 'p', 9, 0, - /* 1284 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0, - /* 1293 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0, - /* 1301 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0, - /* 1310 */ 'c', '.', 's', 'w', 's', 'p', 9, 0, - /* 1318 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0, - /* 1327 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1336 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1349 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1362 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1375 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1389 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1398 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1410 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1423 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1437 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1451 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0, - /* 1464 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1473 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1486 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1499 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1512 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1526 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1535 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1547 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1560 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1574 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1588 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0, - /* 1601 */ 'b', 'e', 'q', 9, 0, - /* 1606 */ 'c', '.', 'j', 'r', 9, 0, - /* 1612 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0, - /* 1620 */ 'c', '.', 'o', 'r', 9, 0, - /* 1626 */ 'c', '.', 'x', 'o', 'r', 9, 0, - /* 1633 */ 'f', 's', 'u', 'b', '.', 's', 9, 0, - /* 1641 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0, - /* 1650 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, - /* 1660 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, - /* 1670 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0, - /* 1678 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0, - /* 1687 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, - /* 1697 */ 'f', 'l', 'e', '.', 's', 9, 0, - /* 1704 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0, - /* 1713 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, - /* 1723 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0, - /* 1731 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0, - /* 1739 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0, - /* 1749 */ 'f', 'e', 'q', '.', 's', 9, 0, - /* 1756 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, - /* 1766 */ 'f', 'l', 't', '.', 's', 9, 0, - /* 1773 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0, - /* 1782 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0, - /* 1793 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0, - /* 1804 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0, - /* 1812 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, - /* 1822 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0, - /* 1830 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0, - /* 1840 */ 'c', 's', 'r', 'r', 's', 9, 0, - /* 1847 */ 'm', 'r', 'e', 't', 9, 0, - /* 1853 */ 's', 'r', 'e', 't', 9, 0, - /* 1859 */ 'u', 'r', 'e', 't', 9, 0, - /* 1865 */ 'b', 'l', 't', 9, 0, - /* 1870 */ 's', 'l', 't', 9, 0, - /* 1875 */ 'l', 'b', 'u', 9, 0, - /* 1880 */ 'b', 'g', 'e', 'u', 9, 0, - /* 1886 */ 'm', 'u', 'l', 'h', 'u', 9, 0, - /* 1893 */ 's', 'l', 't', 'i', 'u', 9, 0, - /* 1900 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0, - /* 1911 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0, - /* 1922 */ 'r', 'e', 'm', 'u', 9, 0, - /* 1928 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0, - /* 1936 */ 'b', 'l', 't', 'u', 9, 0, - /* 1942 */ 's', 'l', 't', 'u', 9, 0, - /* 1948 */ 'd', 'i', 'v', 'u', 9, 0, - /* 1954 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0, - /* 1965 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0, - /* 1976 */ 'l', 'w', 'u', 9, 0, - /* 1981 */ 'd', 'i', 'v', 9, 0, - /* 1986 */ 'c', '.', 'm', 'v', 9, 0, - /* 1992 */ 's', 'c', '.', 'w', 9, 0, - /* 1998 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, - /* 2008 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0, - /* 2018 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0, - /* 2028 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0, - /* 2038 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0, - /* 2049 */ 'l', 'r', '.', 'w', 9, 0, - /* 2055 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0, - /* 2064 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0, - /* 2074 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, - /* 2084 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0, - /* 2095 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0, - /* 2106 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0, - /* 2115 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0, - /* 2125 */ 's', 'r', 'a', 'w', 9, 0, - /* 2131 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0, - /* 2139 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0, - /* 2147 */ 's', 'r', 'a', 'i', 'w', 9, 0, - /* 2154 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0, - /* 2163 */ 's', 'l', 'l', 'i', 'w', 9, 0, - /* 2170 */ 's', 'r', 'l', 'i', 'w', 9, 0, - /* 2177 */ 'c', '.', 'l', 'w', 9, 0, - /* 2183 */ 'c', '.', 'f', 'l', 'w', 9, 0, - /* 2190 */ 's', 'l', 'l', 'w', 9, 0, - /* 2196 */ 's', 'r', 'l', 'w', 9, 0, - /* 2202 */ 'm', 'u', 'l', 'w', 9, 0, - /* 2208 */ 'r', 'e', 'm', 'w', 9, 0, - /* 2214 */ 'c', 's', 'r', 'r', 'w', 9, 0, - /* 2221 */ 'c', '.', 's', 'w', 9, 0, - /* 2227 */ 'c', '.', 'f', 's', 'w', 9, 0, - /* 2234 */ 'r', 'e', 'm', 'u', 'w', 9, 0, - /* 2241 */ 'd', 'i', 'v', 'u', 'w', 9, 0, - /* 2248 */ 'd', 'i', 'v', 'w', 9, 0, - /* 2254 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0, - /* 2263 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0, - /* 2272 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0, - /* 2280 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0, - /* 2288 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, - /* 2319 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 2343 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, - /* 2368 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, - /* 2391 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, - /* 2414 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, - /* 2436 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 2449 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 2456 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 2466 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, - /* 2476 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 2491 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, - }; -#endif - - static const uint16_t OpInfo0[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // INLINEASM_BR - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 2457U, // DBG_VALUE - 2467U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 2450U, // BUNDLE - 2477U, // LIFETIME_START - 2437U, // LIFETIME_END - 0U, // STACKMAP - 2492U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 2369U, // PATCHABLE_FUNCTION_ENTER - 2289U, // PATCHABLE_RET - 2415U, // PATCHABLE_FUNCTION_EXIT - 2392U, // PATCHABLE_TAIL_CALL - 2344U, // PATCHABLE_EVENT_CALL - 2320U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_BUILD_VECTOR - 0U, // G_BUILD_VECTOR_TRUNC - 0U, // G_CONCAT_VECTORS - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_INTRINSIC_TRUNC - 0U, // G_INTRINSIC_ROUND - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDO - 0U, // G_UADDE - 0U, // G_USUBO - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SADDE - 0U, // G_SSUBO - 0U, // G_SSUBE - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FLOG10 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_FCANONICALIZE - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_CTTZ - 0U, // G_CTTZ_ZERO_UNDEF - 0U, // G_CTLZ - 0U, // G_CTLZ_ZERO_UNDEF - 0U, // G_CTPOP - 0U, // G_BSWAP - 0U, // G_FCEIL - 0U, // G_FCOS - 0U, // G_FSIN - 0U, // G_FSQRT - 0U, // G_FFLOOR - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 4U, // ADJCALLSTACKDOWN - 4U, // ADJCALLSTACKUP - 4U, // BuildPairF64Pseudo - 4U, // PseudoAtomicLoadNand32 - 4U, // PseudoAtomicLoadNand64 - 4U, // PseudoBR - 4U, // PseudoBRIND - 4687U, // PseudoCALL - 4U, // PseudoCALLIndirect - 4U, // PseudoCmpXchg32 - 4U, // PseudoCmpXchg64 - 20482U, // PseudoLA - 20967U, // PseudoLI - 20481U, // PseudoLLA - 4U, // PseudoMaskedAtomicLoadAdd32 - 4U, // PseudoMaskedAtomicLoadMax32 - 4U, // PseudoMaskedAtomicLoadMin32 - 4U, // PseudoMaskedAtomicLoadNand32 - 4U, // PseudoMaskedAtomicLoadSub32 - 4U, // PseudoMaskedAtomicLoadUMax32 - 4U, // PseudoMaskedAtomicLoadUMin32 - 4U, // PseudoMaskedAtomicSwap32 - 4U, // PseudoMaskedCmpXchg32 - 4U, // PseudoRET - 4680U, // PseudoTAIL - 4U, // PseudoTAILIndirect - 4U, // Select_FPR32_Using_CC_GPR - 4U, // Select_FPR64_Using_CC_GPR - 4U, // Select_GPR_Using_CC_GPR - 4U, // SplitF64Pseudo - 20854U, // ADD - 20946U, // ADDI - 22637U, // ADDIW - 22622U, // ADDW - 20592U, // AMOADD_D - 21817U, // AMOADD_D_AQ - 21367U, // AMOADD_D_AQ_RL - 21091U, // AMOADD_D_RL - 22489U, // AMOADD_W - 21954U, // AMOADD_W_AQ - 21526U, // AMOADD_W_AQ_RL - 21228U, // AMOADD_W_RL - 20602U, // AMOAND_D - 21830U, // AMOAND_D_AQ - 21382U, // AMOAND_D_AQ_RL - 21104U, // AMOAND_D_RL - 22499U, // AMOAND_W - 21967U, // AMOAND_W_AQ - 21541U, // AMOAND_W_AQ_RL - 21241U, // AMOAND_W_RL - 20786U, // AMOMAXU_D - 21918U, // AMOMAXU_D_AQ - 21484U, // AMOMAXU_D_AQ_RL - 21192U, // AMOMAXU_D_RL - 22576U, // AMOMAXU_W - 22055U, // AMOMAXU_W_AQ - 21643U, // AMOMAXU_W_AQ_RL - 21329U, // AMOMAXU_W_RL - 20832U, // AMOMAX_D - 21932U, // AMOMAX_D_AQ - 21500U, // AMOMAX_D_AQ_RL - 21206U, // AMOMAX_D_RL - 22596U, // AMOMAX_W - 22069U, // AMOMAX_W_AQ - 21659U, // AMOMAX_W_AQ_RL - 21343U, // AMOMAX_W_RL - 20764U, // AMOMINU_D - 21904U, // AMOMINU_D_AQ - 21468U, // AMOMINU_D_AQ_RL - 21178U, // AMOMINU_D_RL - 22565U, // AMOMINU_W - 22041U, // AMOMINU_W_AQ - 21627U, // AMOMINU_W_AQ_RL - 21315U, // AMOMINU_W_RL - 20654U, // AMOMIN_D - 21843U, // AMOMIN_D_AQ - 21397U, // AMOMIN_D_AQ_RL - 21117U, // AMOMIN_D_RL - 22509U, // AMOMIN_W - 21980U, // AMOMIN_W_AQ - 21556U, // AMOMIN_W_AQ_RL - 21254U, // AMOMIN_W_RL - 20698U, // AMOOR_D - 21879U, // AMOOR_D_AQ - 21439U, // AMOOR_D_AQ_RL - 21153U, // AMOOR_D_RL - 22536U, // AMOOR_W - 22016U, // AMOOR_W_AQ - 21598U, // AMOOR_W_AQ_RL - 21290U, // AMOOR_W_RL - 20674U, // AMOSWAP_D - 21856U, // AMOSWAP_D_AQ - 21412U, // AMOSWAP_D_AQ_RL - 21130U, // AMOSWAP_D_RL - 22519U, // AMOSWAP_W - 21993U, // AMOSWAP_W_AQ - 21571U, // AMOSWAP_W_AQ_RL - 21267U, // AMOSWAP_W_RL - 20707U, // AMOXOR_D - 21891U, // AMOXOR_D_AQ - 21453U, // AMOXOR_D_AQ_RL - 21165U, // AMOXOR_D_RL - 22545U, // AMOXOR_W - 22028U, // AMOXOR_W_AQ - 21612U, // AMOXOR_W_AQ_RL - 21302U, // AMOXOR_W_RL - 20874U, // AND - 20954U, // ANDI - 20518U, // AUIPC - 22082U, // BEQ - 20899U, // BGE - 22361U, // BGEU - 22346U, // BLT - 22417U, // BLTU - 20904U, // BNE - 20525U, // CSRRC - 20936U, // CSRRCI - 22321U, // CSRRS - 20993U, // CSRRSI - 22695U, // CSRRW - 21014U, // CSRRWI - 8564U, // C_ADD - 8656U, // C_ADDI - 9440U, // C_ADDI16SP - 21689U, // C_ADDI4SPN - 10347U, // C_ADDIW - 10332U, // C_ADDW - 8584U, // C_AND - 8664U, // C_ANDI - 22761U, // C_BEQZ - 22753U, // C_BNEZ - 547U, // C_EBREAK - 20865U, // C_FLD - 21748U, // C_FLDSP - 22664U, // C_FLW - 21782U, // C_FLWSP - 20885U, // C_FSD - 21765U, // C_FSDSP - 22708U, // C_FSW - 21799U, // C_FSWSP - 4638U, // C_J - 4673U, // C_JAL - 5709U, // C_JALR - 5703U, // C_JR - 20859U, // C_LD - 21740U, // C_LDSP - 20965U, // C_LI - 21007U, // C_LUI - 22658U, // C_LW - 21774U, // C_LWSP - 22467U, // C_MV - 1241U, // C_NOP - 9813U, // C_OR - 20879U, // C_SD - 21757U, // C_SDSP - 8683U, // C_SLLI - 8640U, // C_SRAI - 8691U, // C_SRLI - 8223U, // C_SUB - 10324U, // C_SUBW - 22702U, // C_SW - 21791U, // C_SWSP - 1232U, // C_UNIMP - 9819U, // C_XOR - 22462U, // DIV - 22429U, // DIVU - 22722U, // DIVUW - 22729U, // DIVW - 549U, // EBREAK - 590U, // ECALL - 20565U, // FADD_D - 22151U, // FADD_S - 20727U, // FCLASS_D - 22237U, // FCLASS_S - 21037U, // FCVT_D_L - 22381U, // FCVT_D_LU - 22141U, // FCVT_D_S - 22479U, // FCVT_D_W - 22435U, // FCVT_D_WU - 20753U, // FCVT_LU_D - 22263U, // FCVT_LU_S - 20628U, // FCVT_L_D - 22194U, // FCVT_L_S - 20717U, // FCVT_S_D - 21047U, // FCVT_S_L - 22392U, // FCVT_S_LU - 22555U, // FCVT_S_W - 22446U, // FCVT_S_WU - 20775U, // FCVT_WU_D - 22274U, // FCVT_WU_S - 20805U, // FCVT_W_D - 22293U, // FCVT_W_S - 20797U, // FDIV_D - 22285U, // FDIV_S - 12700U, // FENCE - 439U, // FENCE_I - 1221U, // FENCE_TSO - 20685U, // FEQ_D - 22230U, // FEQ_S - 20867U, // FLD - 20612U, // FLE_D - 22178U, // FLE_S - 20737U, // FLT_D - 22247U, // FLT_S - 22666U, // FLW - 20573U, // FMADD_D - 22159U, // FMADD_S - 20824U, // FMAX_D - 22303U, // FMAX_S - 20646U, // FMIN_D - 22212U, // FMIN_S - 20540U, // FMSUB_D - 22122U, // FMSUB_S - 20638U, // FMUL_D - 22204U, // FMUL_S - 22735U, // FMV_D_X - 22744U, // FMV_W_X - 20815U, // FMV_X_D - 22587U, // FMV_X_W - 20582U, // FNMADD_D - 22168U, // FNMADD_S - 20549U, // FNMSUB_D - 22131U, // FNMSUB_S - 20887U, // FSD - 20664U, // FSGNJN_D - 22220U, // FSGNJN_S - 20842U, // FSGNJX_D - 22311U, // FSGNJX_S - 20619U, // FSGNJ_D - 22185U, // FSGNJ_S - 20744U, // FSQRT_D - 22254U, // FSQRT_S - 20532U, // FSUB_D - 22114U, // FSUB_S - 22710U, // FSW - 21059U, // JAL - 22095U, // JALR - 20503U, // LB - 22356U, // LBU - 20861U, // LD - 20911U, // LH - 22369U, // LHU - 37076U, // LR_D - 38254U, // LR_D_AQ - 37812U, // LR_D_AQ_RL - 37528U, // LR_D_RL - 38914U, // LR_W - 38391U, // LR_W_AQ - 37971U, // LR_W_AQ_RL - 37665U, // LR_W_RL - 21009U, // LUI - 22660U, // LW - 22457U, // LWU - 1848U, // MRET - 21679U, // MUL - 20909U, // MULH - 22409U, // MULHSU - 22367U, // MULHU - 22683U, // MULW - 22103U, // OR - 20988U, // ORI - 21684U, // REM - 22403U, // REMU - 22715U, // REMUW - 22689U, // REMW - 20507U, // SB - 20559U, // SC_D - 21808U, // SC_D_AQ - 21356U, // SC_D_AQ_RL - 21082U, // SC_D_RL - 22473U, // SC_W - 21945U, // SC_W_AQ - 21515U, // SC_W_AQ_RL - 21219U, // SC_W_RL - 20881U, // SD - 20486U, // SFENCE_VMA - 20915U, // SH - 21077U, // SLL - 20973U, // SLLI - 22644U, // SLLIW - 22671U, // SLLW - 22351U, // SLT - 21001U, // SLTI - 22374U, // SLTIU - 22423U, // SLTU - 20498U, // SRA - 20930U, // SRAI - 22628U, // SRAIW - 22606U, // SRAW - 1854U, // SRET - 21674U, // SRL - 20981U, // SRLI - 22651U, // SRLIW - 22677U, // SRLW - 20513U, // SUB - 22614U, // SUBW - 22704U, // SW - 1234U, // UNIMP - 1860U, // URET - 480U, // WFI - 22109U, // XOR - 20987U, // XORI - }; - - static const uint8_t OpInfo1[] = { - 0U, // PHI - 0U, // INLINEASM - 0U, // INLINEASM_BR - 0U, // CFI_INSTRUCTION - 0U, // EH_LABEL - 0U, // GC_LABEL - 0U, // ANNOTATION_LABEL - 0U, // KILL - 0U, // EXTRACT_SUBREG - 0U, // INSERT_SUBREG - 0U, // IMPLICIT_DEF - 0U, // SUBREG_TO_REG - 0U, // COPY_TO_REGCLASS - 0U, // DBG_VALUE - 0U, // DBG_LABEL - 0U, // REG_SEQUENCE - 0U, // COPY - 0U, // BUNDLE - 0U, // LIFETIME_START - 0U, // LIFETIME_END - 0U, // STACKMAP - 0U, // FENTRY_CALL - 0U, // PATCHPOINT - 0U, // LOAD_STACK_GUARD - 0U, // STATEPOINT - 0U, // LOCAL_ESCAPE - 0U, // FAULTING_OP - 0U, // PATCHABLE_OP - 0U, // PATCHABLE_FUNCTION_ENTER - 0U, // PATCHABLE_RET - 0U, // PATCHABLE_FUNCTION_EXIT - 0U, // PATCHABLE_TAIL_CALL - 0U, // PATCHABLE_EVENT_CALL - 0U, // PATCHABLE_TYPED_EVENT_CALL - 0U, // ICALL_BRANCH_FUNNEL - 0U, // G_ADD - 0U, // G_SUB - 0U, // G_MUL - 0U, // G_SDIV - 0U, // G_UDIV - 0U, // G_SREM - 0U, // G_UREM - 0U, // G_AND - 0U, // G_OR - 0U, // G_XOR - 0U, // G_IMPLICIT_DEF - 0U, // G_PHI - 0U, // G_FRAME_INDEX - 0U, // G_GLOBAL_VALUE - 0U, // G_EXTRACT - 0U, // G_UNMERGE_VALUES - 0U, // G_INSERT - 0U, // G_MERGE_VALUES - 0U, // G_BUILD_VECTOR - 0U, // G_BUILD_VECTOR_TRUNC - 0U, // G_CONCAT_VECTORS - 0U, // G_PTRTOINT - 0U, // G_INTTOPTR - 0U, // G_BITCAST - 0U, // G_INTRINSIC_TRUNC - 0U, // G_INTRINSIC_ROUND - 0U, // G_LOAD - 0U, // G_SEXTLOAD - 0U, // G_ZEXTLOAD - 0U, // G_STORE - 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS - 0U, // G_ATOMIC_CMPXCHG - 0U, // G_ATOMICRMW_XCHG - 0U, // G_ATOMICRMW_ADD - 0U, // G_ATOMICRMW_SUB - 0U, // G_ATOMICRMW_AND - 0U, // G_ATOMICRMW_NAND - 0U, // G_ATOMICRMW_OR - 0U, // G_ATOMICRMW_XOR - 0U, // G_ATOMICRMW_MAX - 0U, // G_ATOMICRMW_MIN - 0U, // G_ATOMICRMW_UMAX - 0U, // G_ATOMICRMW_UMIN - 0U, // G_BRCOND - 0U, // G_BRINDIRECT - 0U, // G_INTRINSIC - 0U, // G_INTRINSIC_W_SIDE_EFFECTS - 0U, // G_ANYEXT - 0U, // G_TRUNC - 0U, // G_CONSTANT - 0U, // G_FCONSTANT - 0U, // G_VASTART - 0U, // G_VAARG - 0U, // G_SEXT - 0U, // G_ZEXT - 0U, // G_SHL - 0U, // G_LSHR - 0U, // G_ASHR - 0U, // G_ICMP - 0U, // G_FCMP - 0U, // G_SELECT - 0U, // G_UADDO - 0U, // G_UADDE - 0U, // G_USUBO - 0U, // G_USUBE - 0U, // G_SADDO - 0U, // G_SADDE - 0U, // G_SSUBO - 0U, // G_SSUBE - 0U, // G_UMULO - 0U, // G_SMULO - 0U, // G_UMULH - 0U, // G_SMULH - 0U, // G_FADD - 0U, // G_FSUB - 0U, // G_FMUL - 0U, // G_FMA - 0U, // G_FDIV - 0U, // G_FREM - 0U, // G_FPOW - 0U, // G_FEXP - 0U, // G_FEXP2 - 0U, // G_FLOG - 0U, // G_FLOG2 - 0U, // G_FLOG10 - 0U, // G_FNEG - 0U, // G_FPEXT - 0U, // G_FPTRUNC - 0U, // G_FPTOSI - 0U, // G_FPTOUI - 0U, // G_SITOFP - 0U, // G_UITOFP - 0U, // G_FABS - 0U, // G_FCANONICALIZE - 0U, // G_GEP - 0U, // G_PTR_MASK - 0U, // G_BR - 0U, // G_INSERT_VECTOR_ELT - 0U, // G_EXTRACT_VECTOR_ELT - 0U, // G_SHUFFLE_VECTOR - 0U, // G_CTTZ - 0U, // G_CTTZ_ZERO_UNDEF - 0U, // G_CTLZ - 0U, // G_CTLZ_ZERO_UNDEF - 0U, // G_CTPOP - 0U, // G_BSWAP - 0U, // G_FCEIL - 0U, // G_FCOS - 0U, // G_FSIN - 0U, // G_FSQRT - 0U, // G_FFLOOR - 0U, // G_ADDRSPACE_CAST - 0U, // G_BLOCK_ADDR - 0U, // ADJCALLSTACKDOWN - 0U, // ADJCALLSTACKUP - 0U, // BuildPairF64Pseudo - 0U, // PseudoAtomicLoadNand32 - 0U, // PseudoAtomicLoadNand64 - 0U, // PseudoBR - 0U, // PseudoBRIND - 0U, // PseudoCALL - 0U, // PseudoCALLIndirect - 0U, // PseudoCmpXchg32 - 0U, // PseudoCmpXchg64 - 0U, // PseudoLA - 0U, // PseudoLI - 0U, // PseudoLLA - 0U, // PseudoMaskedAtomicLoadAdd32 - 0U, // PseudoMaskedAtomicLoadMax32 - 0U, // PseudoMaskedAtomicLoadMin32 - 0U, // PseudoMaskedAtomicLoadNand32 - 0U, // PseudoMaskedAtomicLoadSub32 - 0U, // PseudoMaskedAtomicLoadUMax32 - 0U, // PseudoMaskedAtomicLoadUMin32 - 0U, // PseudoMaskedAtomicSwap32 - 0U, // PseudoMaskedCmpXchg32 - 0U, // PseudoRET - 0U, // PseudoTAIL - 0U, // PseudoTAILIndirect - 0U, // Select_FPR32_Using_CC_GPR - 0U, // Select_FPR64_Using_CC_GPR - 0U, // Select_GPR_Using_CC_GPR - 0U, // SplitF64Pseudo - 4U, // ADD - 4U, // ADDI - 4U, // ADDIW - 4U, // ADDW - 9U, // AMOADD_D - 9U, // AMOADD_D_AQ - 9U, // AMOADD_D_AQ_RL - 9U, // AMOADD_D_RL - 9U, // AMOADD_W - 9U, // AMOADD_W_AQ - 9U, // AMOADD_W_AQ_RL - 9U, // AMOADD_W_RL - 9U, // AMOAND_D - 9U, // AMOAND_D_AQ - 9U, // AMOAND_D_AQ_RL - 9U, // AMOAND_D_RL - 9U, // AMOAND_W - 9U, // AMOAND_W_AQ - 9U, // AMOAND_W_AQ_RL - 9U, // AMOAND_W_RL - 9U, // AMOMAXU_D - 9U, // AMOMAXU_D_AQ - 9U, // AMOMAXU_D_AQ_RL - 9U, // AMOMAXU_D_RL - 9U, // AMOMAXU_W - 9U, // AMOMAXU_W_AQ - 9U, // AMOMAXU_W_AQ_RL - 9U, // AMOMAXU_W_RL - 9U, // AMOMAX_D - 9U, // AMOMAX_D_AQ - 9U, // AMOMAX_D_AQ_RL - 9U, // AMOMAX_D_RL - 9U, // AMOMAX_W - 9U, // AMOMAX_W_AQ - 9U, // AMOMAX_W_AQ_RL - 9U, // AMOMAX_W_RL - 9U, // AMOMINU_D - 9U, // AMOMINU_D_AQ - 9U, // AMOMINU_D_AQ_RL - 9U, // AMOMINU_D_RL - 9U, // AMOMINU_W - 9U, // AMOMINU_W_AQ - 9U, // AMOMINU_W_AQ_RL - 9U, // AMOMINU_W_RL - 9U, // AMOMIN_D - 9U, // AMOMIN_D_AQ - 9U, // AMOMIN_D_AQ_RL - 9U, // AMOMIN_D_RL - 9U, // AMOMIN_W - 9U, // AMOMIN_W_AQ - 9U, // AMOMIN_W_AQ_RL - 9U, // AMOMIN_W_RL - 9U, // AMOOR_D - 9U, // AMOOR_D_AQ - 9U, // AMOOR_D_AQ_RL - 9U, // AMOOR_D_RL - 9U, // AMOOR_W - 9U, // AMOOR_W_AQ - 9U, // AMOOR_W_AQ_RL - 9U, // AMOOR_W_RL - 9U, // AMOSWAP_D - 9U, // AMOSWAP_D_AQ - 9U, // AMOSWAP_D_AQ_RL - 9U, // AMOSWAP_D_RL - 9U, // AMOSWAP_W - 9U, // AMOSWAP_W_AQ - 9U, // AMOSWAP_W_AQ_RL - 9U, // AMOSWAP_W_RL - 9U, // AMOXOR_D - 9U, // AMOXOR_D_AQ - 9U, // AMOXOR_D_AQ_RL - 9U, // AMOXOR_D_RL - 9U, // AMOXOR_W - 9U, // AMOXOR_W_AQ - 9U, // AMOXOR_W_AQ_RL - 9U, // AMOXOR_W_RL - 4U, // AND - 4U, // ANDI - 0U, // AUIPC - 4U, // BEQ - 4U, // BGE - 4U, // BGEU - 4U, // BLT - 4U, // BLTU - 4U, // BNE - 2U, // CSRRC - 2U, // CSRRCI - 2U, // CSRRS - 2U, // CSRRSI - 2U, // CSRRW - 2U, // CSRRWI - 0U, // C_ADD - 0U, // C_ADDI - 0U, // C_ADDI16SP - 4U, // C_ADDI4SPN - 0U, // C_ADDIW - 0U, // C_ADDW - 0U, // C_AND - 0U, // C_ANDI - 0U, // C_BEQZ - 0U, // C_BNEZ - 0U, // C_EBREAK - 13U, // C_FLD - 13U, // C_FLDSP - 13U, // C_FLW - 13U, // C_FLWSP - 13U, // C_FSD - 13U, // C_FSDSP - 13U, // C_FSW - 13U, // C_FSWSP - 0U, // C_J - 0U, // C_JAL - 0U, // C_JALR - 0U, // C_JR - 13U, // C_LD - 13U, // C_LDSP - 0U, // C_LI - 0U, // C_LUI - 13U, // C_LW - 13U, // C_LWSP - 0U, // C_MV - 0U, // C_NOP - 0U, // C_OR - 13U, // C_SD - 13U, // C_SDSP - 0U, // C_SLLI - 0U, // C_SRAI - 0U, // C_SRLI - 0U, // C_SUB - 0U, // C_SUBW - 13U, // C_SW - 13U, // C_SWSP - 0U, // C_UNIMP - 0U, // C_XOR - 4U, // DIV - 4U, // DIVU - 4U, // DIVUW - 4U, // DIVW - 0U, // EBREAK - 0U, // ECALL - 36U, // FADD_D - 36U, // FADD_S - 0U, // FCLASS_D - 0U, // FCLASS_S - 20U, // FCVT_D_L - 20U, // FCVT_D_LU - 0U, // FCVT_D_S - 0U, // FCVT_D_W - 0U, // FCVT_D_WU - 20U, // FCVT_LU_D - 20U, // FCVT_LU_S - 20U, // FCVT_L_D - 20U, // FCVT_L_S - 20U, // FCVT_S_D - 20U, // FCVT_S_L - 20U, // FCVT_S_LU - 20U, // FCVT_S_W - 20U, // FCVT_S_WU - 20U, // FCVT_WU_D - 20U, // FCVT_WU_S - 20U, // FCVT_W_D - 20U, // FCVT_W_S - 36U, // FDIV_D - 36U, // FDIV_S - 0U, // FENCE - 0U, // FENCE_I - 0U, // FENCE_TSO - 4U, // FEQ_D - 4U, // FEQ_S - 13U, // FLD - 4U, // FLE_D - 4U, // FLE_S - 4U, // FLT_D - 4U, // FLT_S - 13U, // FLW - 100U, // FMADD_D - 100U, // FMADD_S - 4U, // FMAX_D - 4U, // FMAX_S - 4U, // FMIN_D - 4U, // FMIN_S - 100U, // FMSUB_D - 100U, // FMSUB_S - 36U, // FMUL_D - 36U, // FMUL_S - 0U, // FMV_D_X - 0U, // FMV_W_X - 0U, // FMV_X_D - 0U, // FMV_X_W - 100U, // FNMADD_D - 100U, // FNMADD_S - 100U, // FNMSUB_D - 100U, // FNMSUB_S - 13U, // FSD - 4U, // FSGNJN_D - 4U, // FSGNJN_S - 4U, // FSGNJX_D - 4U, // FSGNJX_S - 4U, // FSGNJ_D - 4U, // FSGNJ_S - 20U, // FSQRT_D - 20U, // FSQRT_S - 36U, // FSUB_D - 36U, // FSUB_S - 13U, // FSW - 0U, // JAL - 4U, // JALR - 13U, // LB - 13U, // LBU - 13U, // LD - 13U, // LH - 13U, // LHU - 0U, // LR_D - 0U, // LR_D_AQ - 0U, // LR_D_AQ_RL - 0U, // LR_D_RL - 0U, // LR_W - 0U, // LR_W_AQ - 0U, // LR_W_AQ_RL - 0U, // LR_W_RL - 0U, // LUI - 13U, // LW - 13U, // LWU - 0U, // MRET - 4U, // MUL - 4U, // MULH - 4U, // MULHSU - 4U, // MULHU - 4U, // MULW - 4U, // OR - 4U, // ORI - 4U, // REM - 4U, // REMU - 4U, // REMUW - 4U, // REMW - 13U, // SB - 9U, // SC_D - 9U, // SC_D_AQ - 9U, // SC_D_AQ_RL - 9U, // SC_D_RL - 9U, // SC_W - 9U, // SC_W_AQ - 9U, // SC_W_AQ_RL - 9U, // SC_W_RL - 13U, // SD - 0U, // SFENCE_VMA - 13U, // SH - 4U, // SLL - 4U, // SLLI - 4U, // SLLIW - 4U, // SLLW - 4U, // SLT - 4U, // SLTI - 4U, // SLTIU - 4U, // SLTU - 4U, // SRA - 4U, // SRAI - 4U, // SRAIW - 4U, // SRAW - 0U, // SRET - 4U, // SRL - 4U, // SRLI - 4U, // SRLIW - 4U, // SRLW - 4U, // SUB - 4U, // SUBW - 13U, // SW - 0U, // UNIMP - 0U, // URET - 0U, // WFI - 4U, // XOR - 4U, // XORI - }; - - // Emit the opcode for the instruction. - uint32_t Bits = 0; - Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; - Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; - CS_ASSERT(Bits != 0 && "Cannot print this instruction."); -#ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 4095)-1); -#endif - - - // Fragment 0 encoded into 2 bits for 4 unique commands. - switch ((uint32_t)((Bits >> 12) & 3)) { - default: - CS_ASSERT(0 && "Invalid command number."); - return; - case 0: - // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... - return; - break; - case 1: - // PseudoCALL, PseudoLA, PseudoLI, PseudoLLA, PseudoTAIL, ADD, ADDI, ADDI... - printOperand(MI, 0, O); - break; - case 2: - // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDW, C_AND, C_ANDI, C_OR, C_SLL... - printOperand(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); - return; - break; - case 3: - // FENCE - printFenceArg(MI, 0, O); - SStream_concat0(O, ", "); - printFenceArg(MI, 1, O); - return; - break; - } - - - // Fragment 1 encoded into 2 bits for 3 unique commands. - switch ((uint32_t)((Bits >> 14) & 3)) { - default: - CS_ASSERT(0 && "Invalid command number."); - return; - case 0: - // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR - return; - break; - case 1: - // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AMOADD_D, AMOAD... - SStream_concat0(O, ", "); - break; - case 2: - // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL - SStream_concat0(O, ", ("); - printOperand(MI, 1, O); - SStream_concat0(O, ")"); - return; - break; - } - - - // Fragment 2 encoded into 2 bits for 3 unique commands. - switch ((uint32_t)((Bits >> 16) & 3)) { - default: - CS_ASSERT(0 && "Invalid command number."); - return; - case 0: - // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP... - printOperand(MI, 1, O); - break; - case 1: - // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... - printOperand(MI, 2, O); - break; - case 2: - // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI - printCSRSystemRegister(MI, 1, O); - SStream_concat0(O, ", "); - printOperand(MI, 2, O); - return; - break; - } - - - // Fragment 3 encoded into 2 bits for 4 unique commands. - switch ((uint32_t)((Bits >> 18) & 3)) { - default: - CS_ASSERT(0 && "Invalid command number."); - return; - case 0: - // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M... - return; - break; - case 1: - // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... - SStream_concat0(O, ", "); - break; - case 2: - // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... - SStream_concat0(O, ", ("); - printOperand(MI, 1, O); - SStream_concat0(O, ")"); - return; - break; - case 3: - // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ... - SStream_concat0(O, "("); - printOperand(MI, 1, O); - SStream_concat0(O, ")"); - return; - break; - } - - - // Fragment 4 encoded into 1 bits for 2 unique commands. - if ((Bits >> 20) & 1) { - // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_... - printFRMArg(MI, 2, O); - return; - } else { - // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... - printOperand(MI, 2, O); - } - - - // Fragment 5 encoded into 1 bits for 2 unique commands. - if ((Bits >> 21) & 1) { - // FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FM... - SStream_concat0(O, ", "); - } else { - // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... - return; - } - - - // Fragment 6 encoded into 1 bits for 2 unique commands. - if ((Bits >> 22) & 1) { - // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS... - printOperand(MI, 3, O); - SStream_concat0(O, ", "); - printFRMArg(MI, 4, O); - return; - } else { - // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S - printFRMArg(MI, 3, O); - return; - } - -} - - -/// getRegisterName - This method is automatically generated by tblgen -/// from the register set description. This returns the assembler name -/// for the specified register. -static const char * -getRegisterName(unsigned RegNo, unsigned AltIdx) -{ - CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!"); - -#ifndef CAPSTONE_DIET - static const char AsmStrsABIRegAltName[] = { - /* 0 */ 'f', 's', '1', '0', 0, - /* 5 */ 'f', 't', '1', '0', 0, - /* 10 */ 'f', 'a', '0', 0, - /* 14 */ 'f', 's', '0', 0, - /* 18 */ 'f', 't', '0', 0, - /* 22 */ 'f', 's', '1', '1', 0, - /* 27 */ 'f', 't', '1', '1', 0, - /* 32 */ 'f', 'a', '1', 0, - /* 36 */ 'f', 's', '1', 0, - /* 40 */ 'f', 't', '1', 0, - /* 44 */ 'f', 'a', '2', 0, - /* 48 */ 'f', 's', '2', 0, - /* 52 */ 'f', 't', '2', 0, - /* 56 */ 'f', 'a', '3', 0, - /* 60 */ 'f', 's', '3', 0, - /* 64 */ 'f', 't', '3', 0, - /* 68 */ 'f', 'a', '4', 0, - /* 72 */ 'f', 's', '4', 0, - /* 76 */ 'f', 't', '4', 0, - /* 80 */ 'f', 'a', '5', 0, - /* 84 */ 'f', 's', '5', 0, - /* 88 */ 'f', 't', '5', 0, - /* 92 */ 'f', 'a', '6', 0, - /* 96 */ 'f', 's', '6', 0, - /* 100 */ 'f', 't', '6', 0, - /* 104 */ 'f', 'a', '7', 0, - /* 108 */ 'f', 's', '7', 0, - /* 112 */ 'f', 't', '7', 0, - /* 116 */ 'f', 's', '8', 0, - /* 120 */ 'f', 't', '8', 0, - /* 124 */ 'f', 's', '9', 0, - /* 128 */ 'f', 't', '9', 0, - /* 132 */ 'r', 'a', 0, - /* 135 */ 'z', 'e', 'r', 'o', 0, - /* 140 */ 'g', 'p', 0, - /* 143 */ 's', 'p', 0, - /* 146 */ 't', 'p', 0, - }; - - static const uint8_t RegAsmOffsetABIRegAltName[] = { - 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, - 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, - 65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, - 88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, - 44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, - 60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, - 0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, - }; - - static const char AsmStrsNoRegAltName[] = { - /* 0 */ 'f', '1', '0', 0, - /* 4 */ 'x', '1', '0', 0, - /* 8 */ 'f', '2', '0', 0, - /* 12 */ 'x', '2', '0', 0, - /* 16 */ 'f', '3', '0', 0, - /* 20 */ 'x', '3', '0', 0, - /* 24 */ 'f', '0', 0, - /* 27 */ 'x', '0', 0, - /* 30 */ 'f', '1', '1', 0, - /* 34 */ 'x', '1', '1', 0, - /* 38 */ 'f', '2', '1', 0, - /* 42 */ 'x', '2', '1', 0, - /* 46 */ 'f', '3', '1', 0, - /* 50 */ 'x', '3', '1', 0, - /* 54 */ 'f', '1', 0, - /* 57 */ 'x', '1', 0, - /* 60 */ 'f', '1', '2', 0, - /* 64 */ 'x', '1', '2', 0, - /* 68 */ 'f', '2', '2', 0, - /* 72 */ 'x', '2', '2', 0, - /* 76 */ 'f', '2', 0, - /* 79 */ 'x', '2', 0, - /* 82 */ 'f', '1', '3', 0, - /* 86 */ 'x', '1', '3', 0, - /* 90 */ 'f', '2', '3', 0, - /* 94 */ 'x', '2', '3', 0, - /* 98 */ 'f', '3', 0, - /* 101 */ 'x', '3', 0, - /* 104 */ 'f', '1', '4', 0, - /* 108 */ 'x', '1', '4', 0, - /* 112 */ 'f', '2', '4', 0, - /* 116 */ 'x', '2', '4', 0, - /* 120 */ 'f', '4', 0, - /* 123 */ 'x', '4', 0, - /* 126 */ 'f', '1', '5', 0, - /* 130 */ 'x', '1', '5', 0, - /* 134 */ 'f', '2', '5', 0, - /* 138 */ 'x', '2', '5', 0, - /* 142 */ 'f', '5', 0, - /* 145 */ 'x', '5', 0, - /* 148 */ 'f', '1', '6', 0, - /* 152 */ 'x', '1', '6', 0, - /* 156 */ 'f', '2', '6', 0, - /* 160 */ 'x', '2', '6', 0, - /* 164 */ 'f', '6', 0, - /* 167 */ 'x', '6', 0, - /* 170 */ 'f', '1', '7', 0, - /* 174 */ 'x', '1', '7', 0, - /* 178 */ 'f', '2', '7', 0, - /* 182 */ 'x', '2', '7', 0, - /* 186 */ 'f', '7', 0, - /* 189 */ 'x', '7', 0, - /* 192 */ 'f', '1', '8', 0, - /* 196 */ 'x', '1', '8', 0, - /* 200 */ 'f', '2', '8', 0, - /* 204 */ 'x', '2', '8', 0, - /* 208 */ 'f', '8', 0, - /* 211 */ 'x', '8', 0, - /* 214 */ 'f', '1', '9', 0, - /* 218 */ 'x', '1', '9', 0, - /* 222 */ 'f', '2', '9', 0, - /* 226 */ 'x', '2', '9', 0, - /* 230 */ 'f', '9', 0, - /* 233 */ 'x', '9', 0, - }; - - static const uint8_t RegAsmOffsetNoRegAltName[] = { - 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, - 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, - 204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, - 142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, - 60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, - 214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, - 156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, - }; - - switch(AltIdx) { - default: - CS_ASSERT(0 && "Invalid register alt name index!"); - return 0; - case RISCV_ABIRegAltName: - CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && - "Invalid alt name index for register!"); - return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]; - case RISCV_NoRegAltName: - CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && - "Invalid alt name index for register!"); - return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; - } -#else - return NULL; -#endif -} - -#ifdef PRINT_ALIAS_INSTR -#undef PRINT_ALIAS_INSTR - -static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, - unsigned PredicateIndex); - -static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) -{ - MCRegisterInfo *MRI = (MCRegisterInfo *) info; - const char *AsmString; - unsigned I = 0; -#define ASMSTRING_CONTAIN_SIZE 64 - unsigned AsmStringLen = 0; - char tmpString_[ASMSTRING_CONTAIN_SIZE]; - char *tmpString = tmpString_; - switch (MCInst_getOpcode(MI)) { - default: return false; - case RISCV_ADDI: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (ADDI X0, X0, 0) - AsmString = "nop"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (ADDI GPR:$rd, GPR:$rs, 0) - AsmString = "mv $\x01, $\x02"; - break; - } - return false; - case RISCV_ADDIW: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (ADDIW GPR:$rd, GPR:$rs, 0) - AsmString = "sext.w $\x01, $\x02"; - break; - } - return false; - case RISCV_BEQ: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { - // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) - AsmString = "beqz $\x01, $\x03"; - break; - } - return false; - case RISCV_BGE: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { - // (BGE X0, GPR:$rs, simm13_lsb0:$offset) - AsmString = "blez $\x02, $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { - // (BGE GPR:$rs, X0, simm13_lsb0:$offset) - AsmString = "bgez $\x01, $\x03"; - break; - } - return false; - case RISCV_BLT: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { - // (BLT GPR:$rs, X0, simm13_lsb0:$offset) - AsmString = "bltz $\x01, $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { - // (BLT X0, GPR:$rs, simm13_lsb0:$offset) - AsmString = "bgtz $\x02, $\x03"; - break; - } - return false; - case RISCV_BNE: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { - // (BNE GPR:$rs, X0, simm13_lsb0:$offset) - AsmString = "bnez $\x01, $\x03"; - break; - } - return false; - case RISCV_CSRRC: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) - AsmString = "csrc $\xFF\x02\x01, $\x03"; - break; - } - return false; - case RISCV_CSRRCI: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { - // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm) - AsmString = "csrci $\xFF\x02\x01, $\x03"; - break; - } - return false; - case RISCV_CSRRS: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 3, X0) - AsmString = "frcsr $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 2, X0) - AsmString = "frrm $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 1, X0) - AsmString = "frflags $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3074 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 3074, X0) - AsmString = "rdinstret $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3072 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 3072, X0) - AsmString = "rdcycle $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3073 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 3073, X0) - AsmString = "rdtime $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3202 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 3202, X0) - AsmString = "rdinstreth $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3200 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 3200, X0) - AsmString = "rdcycleh $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3201 && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, 3201, X0) - AsmString = "rdtimeh $\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) - AsmString = "csrr $\x01, $\xFF\x02\x01"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) - AsmString = "csrs $\xFF\x02\x01, $\x03"; - break; - } - return false; - case RISCV_CSRRSI: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { - // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm) - AsmString = "csrsi $\xFF\x02\x01, $\x03"; - break; - } - return false; - case RISCV_CSRRW: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRW X0, 3, GPR:$rs) - AsmString = "fscsr $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRW X0, 2, GPR:$rs) - AsmString = "fsrm $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRW X0, 1, GPR:$rs) - AsmString = "fsflags $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) - AsmString = "csrw $\xFF\x02\x01, $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRW GPR:$rd, 3, GPR:$rs) - AsmString = "fscsr $\x01, $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRW GPR:$rd, 2, GPR:$rs) - AsmString = "fsrm $\x01, $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (CSRRW GPR:$rd, 1, GPR:$rs) - AsmString = "fsflags $\x01, $\x03"; - break; - } - return false; - case RISCV_CSRRWI: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { - // (CSRRWI X0, 2, uimm5:$imm) - AsmString = "fsrmi $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { - // (CSRRWI X0, 1, uimm5:$imm) - AsmString = "fsflagsi $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { - // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm) - AsmString = "csrwi $\xFF\x02\x01, $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { - // (CSRRWI GPR:$rd, 2, uimm5:$imm) - AsmString = "fsrmi $\x01, $\x03"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { - // (CSRRWI GPR:$rd, 1, uimm5:$imm) - AsmString = "fsflagsi $\x01, $\x03"; - break; - } - return false; - case RISCV_FADD_D: - if (MCInst_getNumOperands(MI) == 4 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isImm(MCInst_getOperand(MI, 3)) && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { - // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - AsmString = "fadd.d $\x01, $\x02, $\x03"; - break; - } - return false; - case RISCV_FADD_S: - if (MCInst_getNumOperands(MI) == 4 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isImm(MCInst_getOperand(MI, 3)) && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { - // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - AsmString = "fadd.s $\x01, $\x02, $\x03"; - break; - } - return false; - case RISCV_FCVT_D_L: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.d.l $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_D_LU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.d.lu $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_LU_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.lu.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_LU_S: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.lu.s $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_L_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.l.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_L_S: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.l.s $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_S_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.s.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_S_L: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.s.l $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_S_LU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.s.lu $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_S_W: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.s.w $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_S_WU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.s.wu $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_WU_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.wu.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_WU_S: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.wu.s $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_W_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.w.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FCVT_W_S: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - AsmString = "fcvt.w.s $\x01, $\x02"; - break; - } - return false; - case RISCV_FDIV_D: - if (MCInst_getNumOperands(MI) == 4 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isImm(MCInst_getOperand(MI, 3)) && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { - // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - AsmString = "fdiv.d $\x01, $\x02, $\x03"; - break; - } - return false; - case RISCV_FDIV_S: - if (MCInst_getNumOperands(MI) == 4 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isImm(MCInst_getOperand(MI, 3)) && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { - // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - AsmString = "fdiv.s $\x01, $\x02, $\x03"; - break; - } - return false; - case RISCV_FENCE: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_isImm(MCInst_getOperand(MI, 0)) && - MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && - MCOperand_isImm(MCInst_getOperand(MI, 1)) && - MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { - // (FENCE 15, 15) - AsmString = "fence"; - break; - } - return false; - case RISCV_FMADD_D: - if (MCInst_getNumOperands(MI) == 5 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && - MCOperand_isImm(MCInst_getOperand(MI, 4)) && - MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { - // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - AsmString = "fmadd.d $\x01, $\x02, $\x03, $\x04"; - break; - } - return false; - case RISCV_FMADD_S: - if (MCInst_getNumOperands(MI) == 5 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && - MCOperand_isImm(MCInst_getOperand(MI, 4)) && - MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { - // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - AsmString = "fmadd.s $\x01, $\x02, $\x03, $\x04"; - break; - } - return false; - case RISCV_FMSUB_D: - if (MCInst_getNumOperands(MI) == 5 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && - MCOperand_isImm(MCInst_getOperand(MI, 4)) && - MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { - // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - AsmString = "fmsub.d $\x01, $\x02, $\x03, $\x04"; - break; - } - return false; - case RISCV_FMSUB_S: - if (MCInst_getNumOperands(MI) == 5 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && - MCOperand_isImm(MCInst_getOperand(MI, 4)) && - MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { - // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - AsmString = "fmsub.s $\x01, $\x02, $\x03, $\x04"; - break; - } - return false; - case RISCV_FMUL_D: - if (MCInst_getNumOperands(MI) == 4 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isImm(MCInst_getOperand(MI, 3)) && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { - // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - AsmString = "fmul.d $\x01, $\x02, $\x03"; - break; - } - return false; - case RISCV_FMUL_S: - if (MCInst_getNumOperands(MI) == 4 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isImm(MCInst_getOperand(MI, 3)) && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { - // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - AsmString = "fmul.s $\x01, $\x02, $\x03"; - break; - } - return false; - case RISCV_FNMADD_D: - if (MCInst_getNumOperands(MI) == 5 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && - MCOperand_isImm(MCInst_getOperand(MI, 4)) && - MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { - // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - AsmString = "fnmadd.d $\x01, $\x02, $\x03, $\x04"; - break; - } - return false; - case RISCV_FNMADD_S: - if (MCInst_getNumOperands(MI) == 5 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && - MCOperand_isImm(MCInst_getOperand(MI, 4)) && - MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { - // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - AsmString = "fnmadd.s $\x01, $\x02, $\x03, $\x04"; - break; - } - return false; - case RISCV_FNMSUB_D: - if (MCInst_getNumOperands(MI) == 5 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && - MCOperand_isImm(MCInst_getOperand(MI, 4)) && - MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { - // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - AsmString = "fnmsub.d $\x01, $\x02, $\x03, $\x04"; - break; - } - return false; - case RISCV_FNMSUB_S: - if (MCInst_getNumOperands(MI) == 5 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isReg(MCInst_getOperand(MI, 3)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && - MCOperand_isImm(MCInst_getOperand(MI, 4)) && - MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { - // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - AsmString = "fnmsub.s $\x01, $\x02, $\x03, $\x04"; - break; - } - return false; - case RISCV_FSGNJN_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { - // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - AsmString = "fneg.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FSGNJN_S: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { - // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - AsmString = "fneg.s $\x01, $\x02"; - break; - } - return false; - case RISCV_FSGNJX_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { - // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - AsmString = "fabs.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FSGNJX_S: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { - // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - AsmString = "fabs.s $\x01, $\x02"; - break; - } - return false; - case RISCV_FSGNJ_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { - // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - AsmString = "fmv.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FSGNJ_S: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { - // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - AsmString = "fmv.s $\x01, $\x02"; - break; - } - return false; - case RISCV_FSQRT_D: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) - AsmString = "fsqrt.d $\x01, $\x02"; - break; - } - return false; - case RISCV_FSQRT_S: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { - // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) - AsmString = "fsqrt.s $\x01, $\x02"; - break; - } - return false; - case RISCV_FSUB_D: - if (MCInst_getNumOperands(MI) == 4 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isImm(MCInst_getOperand(MI, 3)) && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { - // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - AsmString = "fsub.d $\x01, $\x02, $\x03"; - break; - } - return false; - case RISCV_FSUB_S: - if (MCInst_getNumOperands(MI) == 4 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && - MCOperand_isImm(MCInst_getOperand(MI, 3)) && - MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { - // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - AsmString = "fsub.s $\x01, $\x02, $\x03"; - break; - } - return false; - case RISCV_JAL: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { - // (JAL X0, simm21_lsb0_jal:$offset) - AsmString = "j $\x02"; - break; - } - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && - RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { - // (JAL X1, simm21_lsb0_jal:$offset) - AsmString = "jal $\x02"; - break; - } - return false; - case RISCV_JALR: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X1 && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (JALR X0, X1, 0) - AsmString = "ret"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (JALR X0, GPR:$rs, 0) - AsmString = "jr $\x02"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (JALR X1, GPR:$rs, 0) - AsmString = "jalr $\x02"; - break; - } - return false; - case RISCV_SFENCE_VMA: - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { - // (SFENCE_VMA X0, X0) - AsmString = "sfence.vma"; - break; - } - if (MCInst_getNumOperands(MI) == 2 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { - // (SFENCE_VMA GPR:$rs, X0) - AsmString = "sfence.vma $\x01"; - break; - } - return false; - case RISCV_SLT: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { - // (SLT GPR:$rd, GPR:$rs, X0) - AsmString = "sltz $\x01, $\x02"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (SLT GPR:$rd, X0, GPR:$rs) - AsmString = "sgtz $\x01, $\x03"; - break; - } - return false; - case RISCV_SLTIU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { - // (SLTIU GPR:$rd, GPR:$rs, 1) - AsmString = "seqz $\x01, $\x02"; - break; - } - return false; - case RISCV_SLTU: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (SLTU GPR:$rd, X0, GPR:$rs) - AsmString = "snez $\x01, $\x03"; - break; - } - return false; - case RISCV_SUB: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (SUB GPR:$rd, X0, GPR:$rs) - AsmString = "neg $\x01, $\x03"; - break; - } - return false; - case RISCV_SUBW: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { - // (SUBW GPR:$rd, X0, GPR:$rs) - AsmString = "negw $\x01, $\x03"; - break; - } - return false; - case RISCV_XORI: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && - MCOperand_isReg(MCInst_getOperand(MI, 1)) && - MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) { - // (XORI GPR:$rd, GPR:$rs, -1) - AsmString = "not $\x01, $\x02"; - break; - } - return false; - } - - AsmStringLen = strlen(AsmString); - if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) - tmpString = cs_strdup(AsmString); - else - tmpString = memcpy(tmpString, AsmString, 1 + AsmStringLen); - - while (AsmString[I] != ' ' && AsmString[I] != '\t' && - AsmString[I] != '$' && AsmString[I] != '\0') - ++I; - tmpString[I] = 0; - SStream_concat0(OS, tmpString); - if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) - /* Free the possible cs_strdup() memory. PR#1424. */ - cs_mem_free(tmpString); -#undef ASMSTRING_CONTAIN_SIZE - - if (AsmString[I] != '\0') { - if (AsmString[I] == ' ' || AsmString[I] == '\t') { - SStream_concat0(OS, " "); - ++I; - } - do { - if (AsmString[I] == '$') { - ++I; - if (AsmString[I] == (char)0xff) { - ++I; - int OpIdx = AsmString[I++] - 1; - int PrintMethodIdx = AsmString[I++] - 1; - printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); - } else - printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); - } else { - SStream_concat1(OS, AsmString[I++]); - } - } while (AsmString[I] != '\0'); - } - - return true; -} - -static void printCustomAliasOperand( - MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, - SStream *OS) { - switch (PrintMethodIdx) { - default: - CS_ASSERT(0 && "Unknown PrintMethod kind"); - break; - case 0: - printCSRSystemRegister(MI, OpIdx, OS); - break; - } -} - -static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, - unsigned PredicateIndex) { - // TODO: need some constant untils operate the MCOperand, - // but current CAPSTONE doesn't have. - // So, We just return true - return true; - -#if 0 - switch (PredicateIndex) { - default: - llvm_unreachable("Unknown MCOperandPredicate kind"); - break; - case 1: { - - int64_t Imm; - if (MCOp.evaluateAsConstantImm(Imm)) - return isShiftedInt<12, 1>(Imm); - return MCOp.isBareSymbolRef(); - - } - case 2: { - - int64_t Imm; - if (MCOp.evaluateAsConstantImm(Imm)) - return isShiftedInt<20, 1>(Imm); - return MCOp.isBareSymbolRef(); - - } - } -#endif -} - -#endif // PRINT_ALIAS_INSTR diff --git a/arch/RISCV/RISCVGenDisassemblerTables.inc b/arch/RISCV/RISCVGenDisassemblerTables.inc deleted file mode 100644 index c06f18d655..0000000000 --- a/arch/RISCV/RISCVGenDisassemblerTables.inc +++ /dev/null @@ -1,1777 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * RISCV Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - -#include "../../MCInst.h" -#include "../../LEB128.h" -#include "../../cs_priv.h" - -// Helper functions for extracting fields from encoded instructions. -// InsnType must either be integral or an APInt-like object that must: -// * Have a static const max_size_in_bits equal to the number of bits in the -// encoding. -// * be default-constructible and copy-constructible -// * be constructible from a uint64_t -// * be constructible from an APInt (this can be private) -// * Support getBitsSet(loBit, hiBit) -// * be convertible to uint64_t -// * Support the ~, &, ==, !=, and |= operators with other objects of the same type -// * Support shift (<<, >>) with signed and unsigned integers on the RHS -// * Support put (<<) to raw_ostream& -#define FieldFromInstruction(fname, InsnType) \ -static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ -{ \ - InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ - fieldMask = (InsnType)(-1LL); \ - else \ - fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ - return (insn & fieldMask) >> startBit; \ -} - -static const uint8_t DecoderTable16[] = { -/* 0 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 3 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 85 -/* 8 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 11 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 41 -/* 16 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 32 -/* 21 */ MCD_OPC_CheckField, 2, 11, 0, 4, 0, 0, // Skip to: 32 -/* 28 */ MCD_OPC_Decode, 182, 2, 0, // Opcode: C_UNIMP -/* 32 */ MCD_OPC_CheckPredicate, 0, 116, 2, 0, // Skip to: 665 -/* 37 */ MCD_OPC_Decode, 144, 2, 1, // Opcode: C_ADDI4SPN -/* 41 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 71 -/* 46 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 62 -/* 51 */ MCD_OPC_CheckField, 7, 6, 0, 4, 0, 0, // Skip to: 62 -/* 58 */ MCD_OPC_Decode, 171, 2, 0, // Opcode: C_NOP -/* 62 */ MCD_OPC_CheckPredicate, 0, 86, 2, 0, // Skip to: 665 -/* 67 */ MCD_OPC_Decode, 142, 2, 2, // Opcode: C_ADDI -/* 71 */ MCD_OPC_FilterValue, 2, 77, 2, 0, // Skip to: 665 -/* 76 */ MCD_OPC_CheckPredicate, 0, 72, 2, 0, // Skip to: 665 -/* 81 */ MCD_OPC_Decode, 175, 2, 3, // Opcode: C_SLLI -/* 85 */ MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 135 -/* 90 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 93 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 107 -/* 98 */ MCD_OPC_CheckPredicate, 1, 50, 2, 0, // Skip to: 665 -/* 103 */ MCD_OPC_Decode, 152, 2, 4, // Opcode: C_FLD -/* 107 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 121 -/* 112 */ MCD_OPC_CheckPredicate, 2, 36, 2, 0, // Skip to: 665 -/* 117 */ MCD_OPC_Decode, 145, 2, 2, // Opcode: C_ADDIW -/* 121 */ MCD_OPC_FilterValue, 2, 27, 2, 0, // Skip to: 665 -/* 126 */ MCD_OPC_CheckPredicate, 1, 22, 2, 0, // Skip to: 665 -/* 131 */ MCD_OPC_Decode, 153, 2, 5, // Opcode: C_FLDSP -/* 135 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 185 -/* 140 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 143 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 157 -/* 148 */ MCD_OPC_CheckPredicate, 0, 0, 2, 0, // Skip to: 665 -/* 153 */ MCD_OPC_Decode, 168, 2, 6, // Opcode: C_LW -/* 157 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 171 -/* 162 */ MCD_OPC_CheckPredicate, 0, 242, 1, 0, // Skip to: 665 -/* 167 */ MCD_OPC_Decode, 166, 2, 7, // Opcode: C_LI -/* 171 */ MCD_OPC_FilterValue, 2, 233, 1, 0, // Skip to: 665 -/* 176 */ MCD_OPC_CheckPredicate, 0, 228, 1, 0, // Skip to: 665 -/* 181 */ MCD_OPC_Decode, 169, 2, 8, // Opcode: C_LWSP -/* 185 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 251 -/* 190 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 193 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 207 -/* 198 */ MCD_OPC_CheckPredicate, 2, 206, 1, 0, // Skip to: 665 -/* 203 */ MCD_OPC_Decode, 164, 2, 9, // Opcode: C_LD -/* 207 */ MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 237 -/* 212 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 228 -/* 217 */ MCD_OPC_CheckField, 7, 5, 2, 4, 0, 0, // Skip to: 228 -/* 224 */ MCD_OPC_Decode, 143, 2, 10, // Opcode: C_ADDI16SP -/* 228 */ MCD_OPC_CheckPredicate, 0, 176, 1, 0, // Skip to: 665 -/* 233 */ MCD_OPC_Decode, 167, 2, 11, // Opcode: C_LUI -/* 237 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 665 -/* 242 */ MCD_OPC_CheckPredicate, 2, 162, 1, 0, // Skip to: 665 -/* 247 */ MCD_OPC_Decode, 165, 2, 12, // Opcode: C_LDSP -/* 251 */ MCD_OPC_FilterValue, 4, 3, 1, 0, // Skip to: 515 -/* 256 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 259 */ MCD_OPC_FilterValue, 1, 167, 0, 0, // Skip to: 431 -/* 264 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281 -/* 272 */ MCD_OPC_CheckPredicate, 0, 132, 1, 0, // Skip to: 665 -/* 277 */ MCD_OPC_Decode, 177, 2, 13, // Opcode: C_SRLI -/* 281 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 295 -/* 286 */ MCD_OPC_CheckPredicate, 0, 118, 1, 0, // Skip to: 665 -/* 291 */ MCD_OPC_Decode, 176, 2, 13, // Opcode: C_SRAI -/* 295 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 309 -/* 300 */ MCD_OPC_CheckPredicate, 0, 104, 1, 0, // Skip to: 665 -/* 305 */ MCD_OPC_Decode, 148, 2, 14, // Opcode: C_ANDI -/* 309 */ MCD_OPC_FilterValue, 3, 95, 1, 0, // Skip to: 665 -/* 314 */ MCD_OPC_ExtractField, 5, 2, // Inst{6-5} ... -/* 317 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 353 -/* 322 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 325 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 339 -/* 330 */ MCD_OPC_CheckPredicate, 0, 74, 1, 0, // Skip to: 665 -/* 335 */ MCD_OPC_Decode, 178, 2, 15, // Opcode: C_SUB -/* 339 */ MCD_OPC_FilterValue, 1, 65, 1, 0, // Skip to: 665 -/* 344 */ MCD_OPC_CheckPredicate, 2, 60, 1, 0, // Skip to: 665 -/* 349 */ MCD_OPC_Decode, 179, 2, 15, // Opcode: C_SUBW -/* 353 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 389 -/* 358 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 361 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 375 -/* 366 */ MCD_OPC_CheckPredicate, 0, 38, 1, 0, // Skip to: 665 -/* 371 */ MCD_OPC_Decode, 183, 2, 15, // Opcode: C_XOR -/* 375 */ MCD_OPC_FilterValue, 1, 29, 1, 0, // Skip to: 665 -/* 380 */ MCD_OPC_CheckPredicate, 2, 24, 1, 0, // Skip to: 665 -/* 385 */ MCD_OPC_Decode, 146, 2, 15, // Opcode: C_ADDW -/* 389 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 410 -/* 394 */ MCD_OPC_CheckPredicate, 0, 10, 1, 0, // Skip to: 665 -/* 399 */ MCD_OPC_CheckField, 12, 1, 0, 3, 1, 0, // Skip to: 665 -/* 406 */ MCD_OPC_Decode, 172, 2, 15, // Opcode: C_OR -/* 410 */ MCD_OPC_FilterValue, 3, 250, 0, 0, // Skip to: 665 -/* 415 */ MCD_OPC_CheckPredicate, 0, 245, 0, 0, // Skip to: 665 -/* 420 */ MCD_OPC_CheckField, 12, 1, 0, 238, 0, 0, // Skip to: 665 -/* 427 */ MCD_OPC_Decode, 147, 2, 15, // Opcode: C_AND -/* 431 */ MCD_OPC_FilterValue, 2, 229, 0, 0, // Skip to: 665 -/* 436 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 439 */ MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 469 -/* 444 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 460 -/* 449 */ MCD_OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 460 -/* 456 */ MCD_OPC_Decode, 163, 2, 16, // Opcode: C_JR -/* 460 */ MCD_OPC_CheckPredicate, 0, 200, 0, 0, // Skip to: 665 -/* 465 */ MCD_OPC_Decode, 170, 2, 17, // Opcode: C_MV -/* 469 */ MCD_OPC_FilterValue, 1, 191, 0, 0, // Skip to: 665 -/* 474 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 490 -/* 479 */ MCD_OPC_CheckField, 2, 10, 0, 4, 0, 0, // Skip to: 490 -/* 486 */ MCD_OPC_Decode, 151, 2, 0, // Opcode: C_EBREAK -/* 490 */ MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 506 -/* 495 */ MCD_OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 506 -/* 502 */ MCD_OPC_Decode, 162, 2, 16, // Opcode: C_JALR -/* 506 */ MCD_OPC_CheckPredicate, 0, 154, 0, 0, // Skip to: 665 -/* 511 */ MCD_OPC_Decode, 141, 2, 18, // Opcode: C_ADD -/* 515 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 565 -/* 520 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 537 -/* 528 */ MCD_OPC_CheckPredicate, 1, 132, 0, 0, // Skip to: 665 -/* 533 */ MCD_OPC_Decode, 156, 2, 4, // Opcode: C_FSD -/* 537 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 551 -/* 542 */ MCD_OPC_CheckPredicate, 0, 118, 0, 0, // Skip to: 665 -/* 547 */ MCD_OPC_Decode, 160, 2, 19, // Opcode: C_J -/* 551 */ MCD_OPC_FilterValue, 2, 109, 0, 0, // Skip to: 665 -/* 556 */ MCD_OPC_CheckPredicate, 1, 104, 0, 0, // Skip to: 665 -/* 561 */ MCD_OPC_Decode, 157, 2, 20, // Opcode: C_FSDSP -/* 565 */ MCD_OPC_FilterValue, 6, 45, 0, 0, // Skip to: 615 -/* 570 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 573 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 587 -/* 578 */ MCD_OPC_CheckPredicate, 0, 82, 0, 0, // Skip to: 665 -/* 583 */ MCD_OPC_Decode, 180, 2, 6, // Opcode: C_SW -/* 587 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 601 -/* 592 */ MCD_OPC_CheckPredicate, 0, 68, 0, 0, // Skip to: 665 -/* 597 */ MCD_OPC_Decode, 149, 2, 21, // Opcode: C_BEQZ -/* 601 */ MCD_OPC_FilterValue, 2, 59, 0, 0, // Skip to: 665 -/* 606 */ MCD_OPC_CheckPredicate, 0, 54, 0, 0, // Skip to: 665 -/* 611 */ MCD_OPC_Decode, 181, 2, 22, // Opcode: C_SWSP -/* 615 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 665 -/* 620 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 623 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 637 -/* 628 */ MCD_OPC_CheckPredicate, 2, 32, 0, 0, // Skip to: 665 -/* 633 */ MCD_OPC_Decode, 173, 2, 9, // Opcode: C_SD -/* 637 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 651 -/* 642 */ MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 665 -/* 647 */ MCD_OPC_Decode, 150, 2, 21, // Opcode: C_BNEZ -/* 651 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 665 -/* 656 */ MCD_OPC_CheckPredicate, 2, 4, 0, 0, // Skip to: 665 -/* 661 */ MCD_OPC_Decode, 174, 2, 23, // Opcode: C_SDSP -/* 665 */ MCD_OPC_Fail, - 0 -}; - -static const uint8_t DecoderTable32[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 7, // Inst{6-0} ... -/* 3 */ MCD_OPC_FilterValue, 3, 76, 0, 0, // Skip to: 84 -/* 8 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 11 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 20 -/* 16 */ MCD_OPC_Decode, 129, 3, 24, // Opcode: LB -/* 20 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 29 -/* 25 */ MCD_OPC_Decode, 132, 3, 24, // Opcode: LH -/* 29 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 38 -/* 34 */ MCD_OPC_Decode, 143, 3, 24, // Opcode: LW -/* 38 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 52 -/* 43 */ MCD_OPC_CheckPredicate, 3, 55, 15, 0, // Skip to: 3943 -/* 48 */ MCD_OPC_Decode, 131, 3, 24, // Opcode: LD -/* 52 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 61 -/* 57 */ MCD_OPC_Decode, 130, 3, 24, // Opcode: LBU -/* 61 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 70 -/* 66 */ MCD_OPC_Decode, 133, 3, 24, // Opcode: LHU -/* 70 */ MCD_OPC_FilterValue, 6, 28, 15, 0, // Skip to: 3943 -/* 75 */ MCD_OPC_CheckPredicate, 3, 23, 15, 0, // Skip to: 3943 -/* 80 */ MCD_OPC_Decode, 144, 3, 24, // Opcode: LWU -/* 84 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 120 -/* 89 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 92 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 106 -/* 97 */ MCD_OPC_CheckPredicate, 4, 1, 15, 0, // Skip to: 3943 -/* 102 */ MCD_OPC_Decode, 224, 2, 25, // Opcode: FLW -/* 106 */ MCD_OPC_FilterValue, 3, 248, 14, 0, // Skip to: 3943 -/* 111 */ MCD_OPC_CheckPredicate, 5, 243, 14, 0, // Skip to: 3943 -/* 116 */ MCD_OPC_Decode, 219, 2, 26, // Opcode: FLD -/* 120 */ MCD_OPC_FilterValue, 15, 52, 0, 0, // Skip to: 177 -/* 125 */ MCD_OPC_ExtractField, 7, 13, // Inst{19-7} ... -/* 128 */ MCD_OPC_FilterValue, 0, 28, 0, 0, // Skip to: 161 -/* 133 */ MCD_OPC_ExtractField, 28, 4, // Inst{31-28} ... -/* 136 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 145 -/* 141 */ MCD_OPC_Decode, 214, 2, 27, // Opcode: FENCE -/* 145 */ MCD_OPC_FilterValue, 8, 209, 14, 0, // Skip to: 3943 -/* 150 */ MCD_OPC_CheckField, 20, 8, 51, 202, 14, 0, // Skip to: 3943 -/* 157 */ MCD_OPC_Decode, 216, 2, 0, // Opcode: FENCE_TSO -/* 161 */ MCD_OPC_FilterValue, 32, 193, 14, 0, // Skip to: 3943 -/* 166 */ MCD_OPC_CheckField, 20, 12, 0, 186, 14, 0, // Skip to: 3943 -/* 173 */ MCD_OPC_Decode, 215, 2, 0, // Opcode: FENCE_I -/* 177 */ MCD_OPC_FilterValue, 19, 99, 0, 0, // Skip to: 281 -/* 182 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 185 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 194 -/* 190 */ MCD_OPC_Decode, 179, 1, 24, // Opcode: ADDI -/* 194 */ MCD_OPC_FilterValue, 1, 11, 0, 0, // Skip to: 210 -/* 199 */ MCD_OPC_CheckField, 26, 6, 0, 153, 14, 0, // Skip to: 3943 -/* 206 */ MCD_OPC_Decode, 170, 3, 28, // Opcode: SLLI -/* 210 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 219 -/* 215 */ MCD_OPC_Decode, 174, 3, 24, // Opcode: SLTI -/* 219 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 228 -/* 224 */ MCD_OPC_Decode, 175, 3, 24, // Opcode: SLTIU -/* 228 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 237 -/* 233 */ MCD_OPC_Decode, 193, 3, 24, // Opcode: XORI -/* 237 */ MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 263 -/* 242 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ... -/* 245 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 254 -/* 250 */ MCD_OPC_Decode, 183, 3, 28, // Opcode: SRLI -/* 254 */ MCD_OPC_FilterValue, 16, 100, 14, 0, // Skip to: 3943 -/* 259 */ MCD_OPC_Decode, 178, 3, 28, // Opcode: SRAI -/* 263 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 272 -/* 268 */ MCD_OPC_Decode, 152, 3, 24, // Opcode: ORI -/* 272 */ MCD_OPC_FilterValue, 7, 82, 14, 0, // Skip to: 3943 -/* 277 */ MCD_OPC_Decode, 255, 1, 24, // Opcode: ANDI -/* 281 */ MCD_OPC_FilterValue, 23, 4, 0, 0, // Skip to: 290 -/* 286 */ MCD_OPC_Decode, 128, 2, 29, // Opcode: AUIPC -/* 290 */ MCD_OPC_FilterValue, 27, 74, 0, 0, // Skip to: 369 -/* 295 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 298 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 312 -/* 303 */ MCD_OPC_CheckPredicate, 3, 51, 14, 0, // Skip to: 3943 -/* 308 */ MCD_OPC_Decode, 180, 1, 24, // Opcode: ADDIW -/* 312 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 333 -/* 317 */ MCD_OPC_CheckPredicate, 3, 37, 14, 0, // Skip to: 3943 -/* 322 */ MCD_OPC_CheckField, 25, 7, 0, 30, 14, 0, // Skip to: 3943 -/* 329 */ MCD_OPC_Decode, 171, 3, 30, // Opcode: SLLIW -/* 333 */ MCD_OPC_FilterValue, 5, 21, 14, 0, // Skip to: 3943 -/* 338 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 341 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 355 -/* 346 */ MCD_OPC_CheckPredicate, 3, 8, 14, 0, // Skip to: 3943 -/* 351 */ MCD_OPC_Decode, 184, 3, 30, // Opcode: SRLIW -/* 355 */ MCD_OPC_FilterValue, 32, 255, 13, 0, // Skip to: 3943 -/* 360 */ MCD_OPC_CheckPredicate, 3, 250, 13, 0, // Skip to: 3943 -/* 365 */ MCD_OPC_Decode, 179, 3, 30, // Opcode: SRAIW -/* 369 */ MCD_OPC_FilterValue, 35, 44, 0, 0, // Skip to: 418 -/* 374 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 377 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 386 -/* 382 */ MCD_OPC_Decode, 157, 3, 31, // Opcode: SB -/* 386 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 395 -/* 391 */ MCD_OPC_Decode, 168, 3, 31, // Opcode: SH -/* 395 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 404 -/* 400 */ MCD_OPC_Decode, 188, 3, 31, // Opcode: SW -/* 404 */ MCD_OPC_FilterValue, 3, 206, 13, 0, // Skip to: 3943 -/* 409 */ MCD_OPC_CheckPredicate, 3, 201, 13, 0, // Skip to: 3943 -/* 414 */ MCD_OPC_Decode, 166, 3, 31, // Opcode: SD -/* 418 */ MCD_OPC_FilterValue, 39, 31, 0, 0, // Skip to: 454 -/* 423 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 426 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 440 -/* 431 */ MCD_OPC_CheckPredicate, 4, 179, 13, 0, // Skip to: 3943 -/* 436 */ MCD_OPC_Decode, 254, 2, 32, // Opcode: FSW -/* 440 */ MCD_OPC_FilterValue, 3, 170, 13, 0, // Skip to: 3943 -/* 445 */ MCD_OPC_CheckPredicate, 5, 165, 13, 0, // Skip to: 3943 -/* 450 */ MCD_OPC_Decode, 243, 2, 33, // Opcode: FSD -/* 454 */ MCD_OPC_FilterValue, 47, 107, 6, 0, // Skip to: 2102 -/* 459 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 462 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 498 -/* 467 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 470 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 484 -/* 475 */ MCD_OPC_CheckPredicate, 6, 135, 13, 0, // Skip to: 3943 -/* 480 */ MCD_OPC_Decode, 186, 1, 34, // Opcode: AMOADD_W -/* 484 */ MCD_OPC_FilterValue, 3, 126, 13, 0, // Skip to: 3943 -/* 489 */ MCD_OPC_CheckPredicate, 7, 121, 13, 0, // Skip to: 3943 -/* 494 */ MCD_OPC_Decode, 182, 1, 34, // Opcode: AMOADD_D -/* 498 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 534 -/* 503 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 506 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 520 -/* 511 */ MCD_OPC_CheckPredicate, 6, 99, 13, 0, // Skip to: 3943 -/* 516 */ MCD_OPC_Decode, 189, 1, 34, // Opcode: AMOADD_W_RL -/* 520 */ MCD_OPC_FilterValue, 3, 90, 13, 0, // Skip to: 3943 -/* 525 */ MCD_OPC_CheckPredicate, 7, 85, 13, 0, // Skip to: 3943 -/* 530 */ MCD_OPC_Decode, 185, 1, 34, // Opcode: AMOADD_D_RL -/* 534 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 570 -/* 539 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 542 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 556 -/* 547 */ MCD_OPC_CheckPredicate, 6, 63, 13, 0, // Skip to: 3943 -/* 552 */ MCD_OPC_Decode, 187, 1, 34, // Opcode: AMOADD_W_AQ -/* 556 */ MCD_OPC_FilterValue, 3, 54, 13, 0, // Skip to: 3943 -/* 561 */ MCD_OPC_CheckPredicate, 7, 49, 13, 0, // Skip to: 3943 -/* 566 */ MCD_OPC_Decode, 183, 1, 34, // Opcode: AMOADD_D_AQ -/* 570 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 606 -/* 575 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 578 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 592 -/* 583 */ MCD_OPC_CheckPredicate, 6, 27, 13, 0, // Skip to: 3943 -/* 588 */ MCD_OPC_Decode, 188, 1, 34, // Opcode: AMOADD_W_AQ_RL -/* 592 */ MCD_OPC_FilterValue, 3, 18, 13, 0, // Skip to: 3943 -/* 597 */ MCD_OPC_CheckPredicate, 7, 13, 13, 0, // Skip to: 3943 -/* 602 */ MCD_OPC_Decode, 184, 1, 34, // Opcode: AMOADD_D_AQ_RL -/* 606 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 642 -/* 611 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 614 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 628 -/* 619 */ MCD_OPC_CheckPredicate, 6, 247, 12, 0, // Skip to: 3943 -/* 624 */ MCD_OPC_Decode, 242, 1, 34, // Opcode: AMOSWAP_W -/* 628 */ MCD_OPC_FilterValue, 3, 238, 12, 0, // Skip to: 3943 -/* 633 */ MCD_OPC_CheckPredicate, 7, 233, 12, 0, // Skip to: 3943 -/* 638 */ MCD_OPC_Decode, 238, 1, 34, // Opcode: AMOSWAP_D -/* 642 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 678 -/* 647 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 650 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 664 -/* 655 */ MCD_OPC_CheckPredicate, 6, 211, 12, 0, // Skip to: 3943 -/* 660 */ MCD_OPC_Decode, 245, 1, 34, // Opcode: AMOSWAP_W_RL -/* 664 */ MCD_OPC_FilterValue, 3, 202, 12, 0, // Skip to: 3943 -/* 669 */ MCD_OPC_CheckPredicate, 7, 197, 12, 0, // Skip to: 3943 -/* 674 */ MCD_OPC_Decode, 241, 1, 34, // Opcode: AMOSWAP_D_RL -/* 678 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 714 -/* 683 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 686 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 700 -/* 691 */ MCD_OPC_CheckPredicate, 6, 175, 12, 0, // Skip to: 3943 -/* 696 */ MCD_OPC_Decode, 243, 1, 34, // Opcode: AMOSWAP_W_AQ -/* 700 */ MCD_OPC_FilterValue, 3, 166, 12, 0, // Skip to: 3943 -/* 705 */ MCD_OPC_CheckPredicate, 7, 161, 12, 0, // Skip to: 3943 -/* 710 */ MCD_OPC_Decode, 239, 1, 34, // Opcode: AMOSWAP_D_AQ -/* 714 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 750 -/* 719 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 722 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 736 -/* 727 */ MCD_OPC_CheckPredicate, 6, 139, 12, 0, // Skip to: 3943 -/* 732 */ MCD_OPC_Decode, 244, 1, 34, // Opcode: AMOSWAP_W_AQ_RL -/* 736 */ MCD_OPC_FilterValue, 3, 130, 12, 0, // Skip to: 3943 -/* 741 */ MCD_OPC_CheckPredicate, 7, 125, 12, 0, // Skip to: 3943 -/* 746 */ MCD_OPC_Decode, 240, 1, 34, // Opcode: AMOSWAP_D_AQ_RL -/* 750 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 800 -/* 755 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 758 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 779 -/* 763 */ MCD_OPC_CheckPredicate, 6, 103, 12, 0, // Skip to: 3943 -/* 768 */ MCD_OPC_CheckField, 20, 5, 0, 96, 12, 0, // Skip to: 3943 -/* 775 */ MCD_OPC_Decode, 138, 3, 35, // Opcode: LR_W -/* 779 */ MCD_OPC_FilterValue, 3, 87, 12, 0, // Skip to: 3943 -/* 784 */ MCD_OPC_CheckPredicate, 7, 82, 12, 0, // Skip to: 3943 -/* 789 */ MCD_OPC_CheckField, 20, 5, 0, 75, 12, 0, // Skip to: 3943 -/* 796 */ MCD_OPC_Decode, 134, 3, 35, // Opcode: LR_D -/* 800 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 850 -/* 805 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 808 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 829 -/* 813 */ MCD_OPC_CheckPredicate, 6, 53, 12, 0, // Skip to: 3943 -/* 818 */ MCD_OPC_CheckField, 20, 5, 0, 46, 12, 0, // Skip to: 3943 -/* 825 */ MCD_OPC_Decode, 141, 3, 35, // Opcode: LR_W_RL -/* 829 */ MCD_OPC_FilterValue, 3, 37, 12, 0, // Skip to: 3943 -/* 834 */ MCD_OPC_CheckPredicate, 7, 32, 12, 0, // Skip to: 3943 -/* 839 */ MCD_OPC_CheckField, 20, 5, 0, 25, 12, 0, // Skip to: 3943 -/* 846 */ MCD_OPC_Decode, 137, 3, 35, // Opcode: LR_D_RL -/* 850 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 900 -/* 855 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 858 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 879 -/* 863 */ MCD_OPC_CheckPredicate, 6, 3, 12, 0, // Skip to: 3943 -/* 868 */ MCD_OPC_CheckField, 20, 5, 0, 252, 11, 0, // Skip to: 3943 -/* 875 */ MCD_OPC_Decode, 139, 3, 35, // Opcode: LR_W_AQ -/* 879 */ MCD_OPC_FilterValue, 3, 243, 11, 0, // Skip to: 3943 -/* 884 */ MCD_OPC_CheckPredicate, 7, 238, 11, 0, // Skip to: 3943 -/* 889 */ MCD_OPC_CheckField, 20, 5, 0, 231, 11, 0, // Skip to: 3943 -/* 896 */ MCD_OPC_Decode, 135, 3, 35, // Opcode: LR_D_AQ -/* 900 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 950 -/* 905 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 908 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 929 -/* 913 */ MCD_OPC_CheckPredicate, 6, 209, 11, 0, // Skip to: 3943 -/* 918 */ MCD_OPC_CheckField, 20, 5, 0, 202, 11, 0, // Skip to: 3943 -/* 925 */ MCD_OPC_Decode, 140, 3, 35, // Opcode: LR_W_AQ_RL -/* 929 */ MCD_OPC_FilterValue, 3, 193, 11, 0, // Skip to: 3943 -/* 934 */ MCD_OPC_CheckPredicate, 7, 188, 11, 0, // Skip to: 3943 -/* 939 */ MCD_OPC_CheckField, 20, 5, 0, 181, 11, 0, // Skip to: 3943 -/* 946 */ MCD_OPC_Decode, 136, 3, 35, // Opcode: LR_D_AQ_RL -/* 950 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 986 -/* 955 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 958 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 972 -/* 963 */ MCD_OPC_CheckPredicate, 6, 159, 11, 0, // Skip to: 3943 -/* 968 */ MCD_OPC_Decode, 162, 3, 34, // Opcode: SC_W -/* 972 */ MCD_OPC_FilterValue, 3, 150, 11, 0, // Skip to: 3943 -/* 977 */ MCD_OPC_CheckPredicate, 7, 145, 11, 0, // Skip to: 3943 -/* 982 */ MCD_OPC_Decode, 158, 3, 34, // Opcode: SC_D -/* 986 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1022 -/* 991 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 994 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1008 -/* 999 */ MCD_OPC_CheckPredicate, 6, 123, 11, 0, // Skip to: 3943 -/* 1004 */ MCD_OPC_Decode, 165, 3, 34, // Opcode: SC_W_RL -/* 1008 */ MCD_OPC_FilterValue, 3, 114, 11, 0, // Skip to: 3943 -/* 1013 */ MCD_OPC_CheckPredicate, 7, 109, 11, 0, // Skip to: 3943 -/* 1018 */ MCD_OPC_Decode, 161, 3, 34, // Opcode: SC_D_RL -/* 1022 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 1058 -/* 1027 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1030 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1044 -/* 1035 */ MCD_OPC_CheckPredicate, 6, 87, 11, 0, // Skip to: 3943 -/* 1040 */ MCD_OPC_Decode, 163, 3, 34, // Opcode: SC_W_AQ -/* 1044 */ MCD_OPC_FilterValue, 3, 78, 11, 0, // Skip to: 3943 -/* 1049 */ MCD_OPC_CheckPredicate, 7, 73, 11, 0, // Skip to: 3943 -/* 1054 */ MCD_OPC_Decode, 159, 3, 34, // Opcode: SC_D_AQ -/* 1058 */ MCD_OPC_FilterValue, 15, 31, 0, 0, // Skip to: 1094 -/* 1063 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1066 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1080 -/* 1071 */ MCD_OPC_CheckPredicate, 6, 51, 11, 0, // Skip to: 3943 -/* 1076 */ MCD_OPC_Decode, 164, 3, 34, // Opcode: SC_W_AQ_RL -/* 1080 */ MCD_OPC_FilterValue, 3, 42, 11, 0, // Skip to: 3943 -/* 1085 */ MCD_OPC_CheckPredicate, 7, 37, 11, 0, // Skip to: 3943 -/* 1090 */ MCD_OPC_Decode, 160, 3, 34, // Opcode: SC_D_AQ_RL -/* 1094 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 1130 -/* 1099 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1102 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1116 -/* 1107 */ MCD_OPC_CheckPredicate, 6, 15, 11, 0, // Skip to: 3943 -/* 1112 */ MCD_OPC_Decode, 250, 1, 34, // Opcode: AMOXOR_W -/* 1116 */ MCD_OPC_FilterValue, 3, 6, 11, 0, // Skip to: 3943 -/* 1121 */ MCD_OPC_CheckPredicate, 7, 1, 11, 0, // Skip to: 3943 -/* 1126 */ MCD_OPC_Decode, 246, 1, 34, // Opcode: AMOXOR_D -/* 1130 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 1166 -/* 1135 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1138 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1152 -/* 1143 */ MCD_OPC_CheckPredicate, 6, 235, 10, 0, // Skip to: 3943 -/* 1148 */ MCD_OPC_Decode, 253, 1, 34, // Opcode: AMOXOR_W_RL -/* 1152 */ MCD_OPC_FilterValue, 3, 226, 10, 0, // Skip to: 3943 -/* 1157 */ MCD_OPC_CheckPredicate, 7, 221, 10, 0, // Skip to: 3943 -/* 1162 */ MCD_OPC_Decode, 249, 1, 34, // Opcode: AMOXOR_D_RL -/* 1166 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 1202 -/* 1171 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1174 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1188 -/* 1179 */ MCD_OPC_CheckPredicate, 6, 199, 10, 0, // Skip to: 3943 -/* 1184 */ MCD_OPC_Decode, 251, 1, 34, // Opcode: AMOXOR_W_AQ -/* 1188 */ MCD_OPC_FilterValue, 3, 190, 10, 0, // Skip to: 3943 -/* 1193 */ MCD_OPC_CheckPredicate, 7, 185, 10, 0, // Skip to: 3943 -/* 1198 */ MCD_OPC_Decode, 247, 1, 34, // Opcode: AMOXOR_D_AQ -/* 1202 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 1238 -/* 1207 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1210 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1224 -/* 1215 */ MCD_OPC_CheckPredicate, 6, 163, 10, 0, // Skip to: 3943 -/* 1220 */ MCD_OPC_Decode, 252, 1, 34, // Opcode: AMOXOR_W_AQ_RL -/* 1224 */ MCD_OPC_FilterValue, 3, 154, 10, 0, // Skip to: 3943 -/* 1229 */ MCD_OPC_CheckPredicate, 7, 149, 10, 0, // Skip to: 3943 -/* 1234 */ MCD_OPC_Decode, 248, 1, 34, // Opcode: AMOXOR_D_AQ_RL -/* 1238 */ MCD_OPC_FilterValue, 32, 31, 0, 0, // Skip to: 1274 -/* 1243 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1246 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1260 -/* 1251 */ MCD_OPC_CheckPredicate, 6, 127, 10, 0, // Skip to: 3943 -/* 1256 */ MCD_OPC_Decode, 234, 1, 34, // Opcode: AMOOR_W -/* 1260 */ MCD_OPC_FilterValue, 3, 118, 10, 0, // Skip to: 3943 -/* 1265 */ MCD_OPC_CheckPredicate, 7, 113, 10, 0, // Skip to: 3943 -/* 1270 */ MCD_OPC_Decode, 230, 1, 34, // Opcode: AMOOR_D -/* 1274 */ MCD_OPC_FilterValue, 33, 31, 0, 0, // Skip to: 1310 -/* 1279 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1282 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1296 -/* 1287 */ MCD_OPC_CheckPredicate, 6, 91, 10, 0, // Skip to: 3943 -/* 1292 */ MCD_OPC_Decode, 237, 1, 34, // Opcode: AMOOR_W_RL -/* 1296 */ MCD_OPC_FilterValue, 3, 82, 10, 0, // Skip to: 3943 -/* 1301 */ MCD_OPC_CheckPredicate, 7, 77, 10, 0, // Skip to: 3943 -/* 1306 */ MCD_OPC_Decode, 233, 1, 34, // Opcode: AMOOR_D_RL -/* 1310 */ MCD_OPC_FilterValue, 34, 31, 0, 0, // Skip to: 1346 -/* 1315 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1318 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1332 -/* 1323 */ MCD_OPC_CheckPredicate, 6, 55, 10, 0, // Skip to: 3943 -/* 1328 */ MCD_OPC_Decode, 235, 1, 34, // Opcode: AMOOR_W_AQ -/* 1332 */ MCD_OPC_FilterValue, 3, 46, 10, 0, // Skip to: 3943 -/* 1337 */ MCD_OPC_CheckPredicate, 7, 41, 10, 0, // Skip to: 3943 -/* 1342 */ MCD_OPC_Decode, 231, 1, 34, // Opcode: AMOOR_D_AQ -/* 1346 */ MCD_OPC_FilterValue, 35, 31, 0, 0, // Skip to: 1382 -/* 1351 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1354 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1368 -/* 1359 */ MCD_OPC_CheckPredicate, 6, 19, 10, 0, // Skip to: 3943 -/* 1364 */ MCD_OPC_Decode, 236, 1, 34, // Opcode: AMOOR_W_AQ_RL -/* 1368 */ MCD_OPC_FilterValue, 3, 10, 10, 0, // Skip to: 3943 -/* 1373 */ MCD_OPC_CheckPredicate, 7, 5, 10, 0, // Skip to: 3943 -/* 1378 */ MCD_OPC_Decode, 232, 1, 34, // Opcode: AMOOR_D_AQ_RL -/* 1382 */ MCD_OPC_FilterValue, 48, 31, 0, 0, // Skip to: 1418 -/* 1387 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1390 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1404 -/* 1395 */ MCD_OPC_CheckPredicate, 6, 239, 9, 0, // Skip to: 3943 -/* 1400 */ MCD_OPC_Decode, 194, 1, 34, // Opcode: AMOAND_W -/* 1404 */ MCD_OPC_FilterValue, 3, 230, 9, 0, // Skip to: 3943 -/* 1409 */ MCD_OPC_CheckPredicate, 7, 225, 9, 0, // Skip to: 3943 -/* 1414 */ MCD_OPC_Decode, 190, 1, 34, // Opcode: AMOAND_D -/* 1418 */ MCD_OPC_FilterValue, 49, 31, 0, 0, // Skip to: 1454 -/* 1423 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1426 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1440 -/* 1431 */ MCD_OPC_CheckPredicate, 6, 203, 9, 0, // Skip to: 3943 -/* 1436 */ MCD_OPC_Decode, 197, 1, 34, // Opcode: AMOAND_W_RL -/* 1440 */ MCD_OPC_FilterValue, 3, 194, 9, 0, // Skip to: 3943 -/* 1445 */ MCD_OPC_CheckPredicate, 7, 189, 9, 0, // Skip to: 3943 -/* 1450 */ MCD_OPC_Decode, 193, 1, 34, // Opcode: AMOAND_D_RL -/* 1454 */ MCD_OPC_FilterValue, 50, 31, 0, 0, // Skip to: 1490 -/* 1459 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1462 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1476 -/* 1467 */ MCD_OPC_CheckPredicate, 6, 167, 9, 0, // Skip to: 3943 -/* 1472 */ MCD_OPC_Decode, 195, 1, 34, // Opcode: AMOAND_W_AQ -/* 1476 */ MCD_OPC_FilterValue, 3, 158, 9, 0, // Skip to: 3943 -/* 1481 */ MCD_OPC_CheckPredicate, 7, 153, 9, 0, // Skip to: 3943 -/* 1486 */ MCD_OPC_Decode, 191, 1, 34, // Opcode: AMOAND_D_AQ -/* 1490 */ MCD_OPC_FilterValue, 51, 31, 0, 0, // Skip to: 1526 -/* 1495 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1498 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1512 -/* 1503 */ MCD_OPC_CheckPredicate, 6, 131, 9, 0, // Skip to: 3943 -/* 1508 */ MCD_OPC_Decode, 196, 1, 34, // Opcode: AMOAND_W_AQ_RL -/* 1512 */ MCD_OPC_FilterValue, 3, 122, 9, 0, // Skip to: 3943 -/* 1517 */ MCD_OPC_CheckPredicate, 7, 117, 9, 0, // Skip to: 3943 -/* 1522 */ MCD_OPC_Decode, 192, 1, 34, // Opcode: AMOAND_D_AQ_RL -/* 1526 */ MCD_OPC_FilterValue, 64, 31, 0, 0, // Skip to: 1562 -/* 1531 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1534 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1548 -/* 1539 */ MCD_OPC_CheckPredicate, 6, 95, 9, 0, // Skip to: 3943 -/* 1544 */ MCD_OPC_Decode, 226, 1, 34, // Opcode: AMOMIN_W -/* 1548 */ MCD_OPC_FilterValue, 3, 86, 9, 0, // Skip to: 3943 -/* 1553 */ MCD_OPC_CheckPredicate, 7, 81, 9, 0, // Skip to: 3943 -/* 1558 */ MCD_OPC_Decode, 222, 1, 34, // Opcode: AMOMIN_D -/* 1562 */ MCD_OPC_FilterValue, 65, 31, 0, 0, // Skip to: 1598 -/* 1567 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1570 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1584 -/* 1575 */ MCD_OPC_CheckPredicate, 6, 59, 9, 0, // Skip to: 3943 -/* 1580 */ MCD_OPC_Decode, 229, 1, 34, // Opcode: AMOMIN_W_RL -/* 1584 */ MCD_OPC_FilterValue, 3, 50, 9, 0, // Skip to: 3943 -/* 1589 */ MCD_OPC_CheckPredicate, 7, 45, 9, 0, // Skip to: 3943 -/* 1594 */ MCD_OPC_Decode, 225, 1, 34, // Opcode: AMOMIN_D_RL -/* 1598 */ MCD_OPC_FilterValue, 66, 31, 0, 0, // Skip to: 1634 -/* 1603 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1606 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1620 -/* 1611 */ MCD_OPC_CheckPredicate, 6, 23, 9, 0, // Skip to: 3943 -/* 1616 */ MCD_OPC_Decode, 227, 1, 34, // Opcode: AMOMIN_W_AQ -/* 1620 */ MCD_OPC_FilterValue, 3, 14, 9, 0, // Skip to: 3943 -/* 1625 */ MCD_OPC_CheckPredicate, 7, 9, 9, 0, // Skip to: 3943 -/* 1630 */ MCD_OPC_Decode, 223, 1, 34, // Opcode: AMOMIN_D_AQ -/* 1634 */ MCD_OPC_FilterValue, 67, 31, 0, 0, // Skip to: 1670 -/* 1639 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1642 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1656 -/* 1647 */ MCD_OPC_CheckPredicate, 6, 243, 8, 0, // Skip to: 3943 -/* 1652 */ MCD_OPC_Decode, 228, 1, 34, // Opcode: AMOMIN_W_AQ_RL -/* 1656 */ MCD_OPC_FilterValue, 3, 234, 8, 0, // Skip to: 3943 -/* 1661 */ MCD_OPC_CheckPredicate, 7, 229, 8, 0, // Skip to: 3943 -/* 1666 */ MCD_OPC_Decode, 224, 1, 34, // Opcode: AMOMIN_D_AQ_RL -/* 1670 */ MCD_OPC_FilterValue, 80, 31, 0, 0, // Skip to: 1706 -/* 1675 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1678 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1692 -/* 1683 */ MCD_OPC_CheckPredicate, 6, 207, 8, 0, // Skip to: 3943 -/* 1688 */ MCD_OPC_Decode, 210, 1, 34, // Opcode: AMOMAX_W -/* 1692 */ MCD_OPC_FilterValue, 3, 198, 8, 0, // Skip to: 3943 -/* 1697 */ MCD_OPC_CheckPredicate, 7, 193, 8, 0, // Skip to: 3943 -/* 1702 */ MCD_OPC_Decode, 206, 1, 34, // Opcode: AMOMAX_D -/* 1706 */ MCD_OPC_FilterValue, 81, 31, 0, 0, // Skip to: 1742 -/* 1711 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1714 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1728 -/* 1719 */ MCD_OPC_CheckPredicate, 6, 171, 8, 0, // Skip to: 3943 -/* 1724 */ MCD_OPC_Decode, 213, 1, 34, // Opcode: AMOMAX_W_RL -/* 1728 */ MCD_OPC_FilterValue, 3, 162, 8, 0, // Skip to: 3943 -/* 1733 */ MCD_OPC_CheckPredicate, 7, 157, 8, 0, // Skip to: 3943 -/* 1738 */ MCD_OPC_Decode, 209, 1, 34, // Opcode: AMOMAX_D_RL -/* 1742 */ MCD_OPC_FilterValue, 82, 31, 0, 0, // Skip to: 1778 -/* 1747 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1750 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1764 -/* 1755 */ MCD_OPC_CheckPredicate, 6, 135, 8, 0, // Skip to: 3943 -/* 1760 */ MCD_OPC_Decode, 211, 1, 34, // Opcode: AMOMAX_W_AQ -/* 1764 */ MCD_OPC_FilterValue, 3, 126, 8, 0, // Skip to: 3943 -/* 1769 */ MCD_OPC_CheckPredicate, 7, 121, 8, 0, // Skip to: 3943 -/* 1774 */ MCD_OPC_Decode, 207, 1, 34, // Opcode: AMOMAX_D_AQ -/* 1778 */ MCD_OPC_FilterValue, 83, 31, 0, 0, // Skip to: 1814 -/* 1783 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1786 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1800 -/* 1791 */ MCD_OPC_CheckPredicate, 6, 99, 8, 0, // Skip to: 3943 -/* 1796 */ MCD_OPC_Decode, 212, 1, 34, // Opcode: AMOMAX_W_AQ_RL -/* 1800 */ MCD_OPC_FilterValue, 3, 90, 8, 0, // Skip to: 3943 -/* 1805 */ MCD_OPC_CheckPredicate, 7, 85, 8, 0, // Skip to: 3943 -/* 1810 */ MCD_OPC_Decode, 208, 1, 34, // Opcode: AMOMAX_D_AQ_RL -/* 1814 */ MCD_OPC_FilterValue, 96, 31, 0, 0, // Skip to: 1850 -/* 1819 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1822 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1836 -/* 1827 */ MCD_OPC_CheckPredicate, 6, 63, 8, 0, // Skip to: 3943 -/* 1832 */ MCD_OPC_Decode, 218, 1, 34, // Opcode: AMOMINU_W -/* 1836 */ MCD_OPC_FilterValue, 3, 54, 8, 0, // Skip to: 3943 -/* 1841 */ MCD_OPC_CheckPredicate, 7, 49, 8, 0, // Skip to: 3943 -/* 1846 */ MCD_OPC_Decode, 214, 1, 34, // Opcode: AMOMINU_D -/* 1850 */ MCD_OPC_FilterValue, 97, 31, 0, 0, // Skip to: 1886 -/* 1855 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1858 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1872 -/* 1863 */ MCD_OPC_CheckPredicate, 6, 27, 8, 0, // Skip to: 3943 -/* 1868 */ MCD_OPC_Decode, 221, 1, 34, // Opcode: AMOMINU_W_RL -/* 1872 */ MCD_OPC_FilterValue, 3, 18, 8, 0, // Skip to: 3943 -/* 1877 */ MCD_OPC_CheckPredicate, 7, 13, 8, 0, // Skip to: 3943 -/* 1882 */ MCD_OPC_Decode, 217, 1, 34, // Opcode: AMOMINU_D_RL -/* 1886 */ MCD_OPC_FilterValue, 98, 31, 0, 0, // Skip to: 1922 -/* 1891 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1894 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1908 -/* 1899 */ MCD_OPC_CheckPredicate, 6, 247, 7, 0, // Skip to: 3943 -/* 1904 */ MCD_OPC_Decode, 219, 1, 34, // Opcode: AMOMINU_W_AQ -/* 1908 */ MCD_OPC_FilterValue, 3, 238, 7, 0, // Skip to: 3943 -/* 1913 */ MCD_OPC_CheckPredicate, 7, 233, 7, 0, // Skip to: 3943 -/* 1918 */ MCD_OPC_Decode, 215, 1, 34, // Opcode: AMOMINU_D_AQ -/* 1922 */ MCD_OPC_FilterValue, 99, 31, 0, 0, // Skip to: 1958 -/* 1927 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1930 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1944 -/* 1935 */ MCD_OPC_CheckPredicate, 6, 211, 7, 0, // Skip to: 3943 -/* 1940 */ MCD_OPC_Decode, 220, 1, 34, // Opcode: AMOMINU_W_AQ_RL -/* 1944 */ MCD_OPC_FilterValue, 3, 202, 7, 0, // Skip to: 3943 -/* 1949 */ MCD_OPC_CheckPredicate, 7, 197, 7, 0, // Skip to: 3943 -/* 1954 */ MCD_OPC_Decode, 216, 1, 34, // Opcode: AMOMINU_D_AQ_RL -/* 1958 */ MCD_OPC_FilterValue, 112, 31, 0, 0, // Skip to: 1994 -/* 1963 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 1966 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1980 -/* 1971 */ MCD_OPC_CheckPredicate, 6, 175, 7, 0, // Skip to: 3943 -/* 1976 */ MCD_OPC_Decode, 202, 1, 34, // Opcode: AMOMAXU_W -/* 1980 */ MCD_OPC_FilterValue, 3, 166, 7, 0, // Skip to: 3943 -/* 1985 */ MCD_OPC_CheckPredicate, 7, 161, 7, 0, // Skip to: 3943 -/* 1990 */ MCD_OPC_Decode, 198, 1, 34, // Opcode: AMOMAXU_D -/* 1994 */ MCD_OPC_FilterValue, 113, 31, 0, 0, // Skip to: 2030 -/* 1999 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2002 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2016 -/* 2007 */ MCD_OPC_CheckPredicate, 6, 139, 7, 0, // Skip to: 3943 -/* 2012 */ MCD_OPC_Decode, 205, 1, 34, // Opcode: AMOMAXU_W_RL -/* 2016 */ MCD_OPC_FilterValue, 3, 130, 7, 0, // Skip to: 3943 -/* 2021 */ MCD_OPC_CheckPredicate, 7, 125, 7, 0, // Skip to: 3943 -/* 2026 */ MCD_OPC_Decode, 201, 1, 34, // Opcode: AMOMAXU_D_RL -/* 2030 */ MCD_OPC_FilterValue, 114, 31, 0, 0, // Skip to: 2066 -/* 2035 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2038 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2052 -/* 2043 */ MCD_OPC_CheckPredicate, 6, 103, 7, 0, // Skip to: 3943 -/* 2048 */ MCD_OPC_Decode, 203, 1, 34, // Opcode: AMOMAXU_W_AQ -/* 2052 */ MCD_OPC_FilterValue, 3, 94, 7, 0, // Skip to: 3943 -/* 2057 */ MCD_OPC_CheckPredicate, 7, 89, 7, 0, // Skip to: 3943 -/* 2062 */ MCD_OPC_Decode, 199, 1, 34, // Opcode: AMOMAXU_D_AQ -/* 2066 */ MCD_OPC_FilterValue, 115, 80, 7, 0, // Skip to: 3943 -/* 2071 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2074 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2088 -/* 2079 */ MCD_OPC_CheckPredicate, 6, 67, 7, 0, // Skip to: 3943 -/* 2084 */ MCD_OPC_Decode, 204, 1, 34, // Opcode: AMOMAXU_W_AQ_RL -/* 2088 */ MCD_OPC_FilterValue, 3, 58, 7, 0, // Skip to: 3943 -/* 2093 */ MCD_OPC_CheckPredicate, 7, 53, 7, 0, // Skip to: 3943 -/* 2098 */ MCD_OPC_Decode, 200, 1, 34, // Opcode: AMOMAXU_D_AQ_RL -/* 2102 */ MCD_OPC_FilterValue, 51, 13, 1, 0, // Skip to: 2376 -/* 2107 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2110 */ MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2150 -/* 2115 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2118 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2127 -/* 2123 */ MCD_OPC_Decode, 178, 1, 34, // Opcode: ADD -/* 2127 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2141 -/* 2132 */ MCD_OPC_CheckPredicate, 8, 14, 7, 0, // Skip to: 3943 -/* 2137 */ MCD_OPC_Decode, 146, 3, 34, // Opcode: MUL -/* 2141 */ MCD_OPC_FilterValue, 32, 5, 7, 0, // Skip to: 3943 -/* 2146 */ MCD_OPC_Decode, 186, 3, 34, // Opcode: SUB -/* 2150 */ MCD_OPC_FilterValue, 1, 26, 0, 0, // Skip to: 2181 -/* 2155 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2158 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2167 -/* 2163 */ MCD_OPC_Decode, 169, 3, 34, // Opcode: SLL -/* 2167 */ MCD_OPC_FilterValue, 1, 235, 6, 0, // Skip to: 3943 -/* 2172 */ MCD_OPC_CheckPredicate, 8, 230, 6, 0, // Skip to: 3943 -/* 2177 */ MCD_OPC_Decode, 147, 3, 34, // Opcode: MULH -/* 2181 */ MCD_OPC_FilterValue, 2, 26, 0, 0, // Skip to: 2212 -/* 2186 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2189 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2198 -/* 2194 */ MCD_OPC_Decode, 173, 3, 34, // Opcode: SLT -/* 2198 */ MCD_OPC_FilterValue, 1, 204, 6, 0, // Skip to: 3943 -/* 2203 */ MCD_OPC_CheckPredicate, 8, 199, 6, 0, // Skip to: 3943 -/* 2208 */ MCD_OPC_Decode, 148, 3, 34, // Opcode: MULHSU -/* 2212 */ MCD_OPC_FilterValue, 3, 26, 0, 0, // Skip to: 2243 -/* 2217 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2220 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2229 -/* 2225 */ MCD_OPC_Decode, 176, 3, 34, // Opcode: SLTU -/* 2229 */ MCD_OPC_FilterValue, 1, 173, 6, 0, // Skip to: 3943 -/* 2234 */ MCD_OPC_CheckPredicate, 8, 168, 6, 0, // Skip to: 3943 -/* 2239 */ MCD_OPC_Decode, 149, 3, 34, // Opcode: MULHU -/* 2243 */ MCD_OPC_FilterValue, 4, 26, 0, 0, // Skip to: 2274 -/* 2248 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2251 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2260 -/* 2256 */ MCD_OPC_Decode, 192, 3, 34, // Opcode: XOR -/* 2260 */ MCD_OPC_FilterValue, 1, 142, 6, 0, // Skip to: 3943 -/* 2265 */ MCD_OPC_CheckPredicate, 8, 137, 6, 0, // Skip to: 3943 -/* 2270 */ MCD_OPC_Decode, 184, 2, 34, // Opcode: DIV -/* 2274 */ MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 2314 -/* 2279 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2282 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2291 -/* 2287 */ MCD_OPC_Decode, 182, 3, 34, // Opcode: SRL -/* 2291 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2305 -/* 2296 */ MCD_OPC_CheckPredicate, 8, 106, 6, 0, // Skip to: 3943 -/* 2301 */ MCD_OPC_Decode, 185, 2, 34, // Opcode: DIVU -/* 2305 */ MCD_OPC_FilterValue, 32, 97, 6, 0, // Skip to: 3943 -/* 2310 */ MCD_OPC_Decode, 177, 3, 34, // Opcode: SRA -/* 2314 */ MCD_OPC_FilterValue, 6, 26, 0, 0, // Skip to: 2345 -/* 2319 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2322 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2331 -/* 2327 */ MCD_OPC_Decode, 151, 3, 34, // Opcode: OR -/* 2331 */ MCD_OPC_FilterValue, 1, 71, 6, 0, // Skip to: 3943 -/* 2336 */ MCD_OPC_CheckPredicate, 8, 66, 6, 0, // Skip to: 3943 -/* 2341 */ MCD_OPC_Decode, 153, 3, 34, // Opcode: REM -/* 2345 */ MCD_OPC_FilterValue, 7, 57, 6, 0, // Skip to: 3943 -/* 2350 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2353 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2362 -/* 2358 */ MCD_OPC_Decode, 254, 1, 34, // Opcode: AND -/* 2362 */ MCD_OPC_FilterValue, 1, 40, 6, 0, // Skip to: 3943 -/* 2367 */ MCD_OPC_CheckPredicate, 8, 35, 6, 0, // Skip to: 3943 -/* 2372 */ MCD_OPC_Decode, 154, 3, 34, // Opcode: REMU -/* 2376 */ MCD_OPC_FilterValue, 55, 4, 0, 0, // Skip to: 2385 -/* 2381 */ MCD_OPC_Decode, 142, 3, 29, // Opcode: LUI -/* 2385 */ MCD_OPC_FilterValue, 59, 187, 0, 0, // Skip to: 2577 -/* 2390 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2393 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2443 -/* 2398 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2401 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2415 -/* 2406 */ MCD_OPC_CheckPredicate, 3, 252, 5, 0, // Skip to: 3943 -/* 2411 */ MCD_OPC_Decode, 181, 1, 34, // Opcode: ADDW -/* 2415 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2429 -/* 2420 */ MCD_OPC_CheckPredicate, 9, 238, 5, 0, // Skip to: 3943 -/* 2425 */ MCD_OPC_Decode, 150, 3, 34, // Opcode: MULW -/* 2429 */ MCD_OPC_FilterValue, 32, 229, 5, 0, // Skip to: 3943 -/* 2434 */ MCD_OPC_CheckPredicate, 3, 224, 5, 0, // Skip to: 3943 -/* 2439 */ MCD_OPC_Decode, 187, 3, 34, // Opcode: SUBW -/* 2443 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2464 -/* 2448 */ MCD_OPC_CheckPredicate, 3, 210, 5, 0, // Skip to: 3943 -/* 2453 */ MCD_OPC_CheckField, 25, 7, 0, 203, 5, 0, // Skip to: 3943 -/* 2460 */ MCD_OPC_Decode, 172, 3, 34, // Opcode: SLLW -/* 2464 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2485 -/* 2469 */ MCD_OPC_CheckPredicate, 9, 189, 5, 0, // Skip to: 3943 -/* 2474 */ MCD_OPC_CheckField, 25, 7, 1, 182, 5, 0, // Skip to: 3943 -/* 2481 */ MCD_OPC_Decode, 187, 2, 34, // Opcode: DIVW -/* 2485 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 2535 -/* 2490 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2493 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2507 -/* 2498 */ MCD_OPC_CheckPredicate, 3, 160, 5, 0, // Skip to: 3943 -/* 2503 */ MCD_OPC_Decode, 185, 3, 34, // Opcode: SRLW -/* 2507 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2521 -/* 2512 */ MCD_OPC_CheckPredicate, 9, 146, 5, 0, // Skip to: 3943 -/* 2517 */ MCD_OPC_Decode, 186, 2, 34, // Opcode: DIVUW -/* 2521 */ MCD_OPC_FilterValue, 32, 137, 5, 0, // Skip to: 3943 -/* 2526 */ MCD_OPC_CheckPredicate, 3, 132, 5, 0, // Skip to: 3943 -/* 2531 */ MCD_OPC_Decode, 180, 3, 34, // Opcode: SRAW -/* 2535 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2556 -/* 2540 */ MCD_OPC_CheckPredicate, 9, 118, 5, 0, // Skip to: 3943 -/* 2545 */ MCD_OPC_CheckField, 25, 7, 1, 111, 5, 0, // Skip to: 3943 -/* 2552 */ MCD_OPC_Decode, 156, 3, 34, // Opcode: REMW -/* 2556 */ MCD_OPC_FilterValue, 7, 102, 5, 0, // Skip to: 3943 -/* 2561 */ MCD_OPC_CheckPredicate, 9, 97, 5, 0, // Skip to: 3943 -/* 2566 */ MCD_OPC_CheckField, 25, 7, 1, 90, 5, 0, // Skip to: 3943 -/* 2573 */ MCD_OPC_Decode, 155, 3, 34, // Opcode: REMUW -/* 2577 */ MCD_OPC_FilterValue, 67, 31, 0, 0, // Skip to: 2613 -/* 2582 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... -/* 2585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2599 -/* 2590 */ MCD_OPC_CheckPredicate, 4, 68, 5, 0, // Skip to: 3943 -/* 2595 */ MCD_OPC_Decode, 226, 2, 36, // Opcode: FMADD_S -/* 2599 */ MCD_OPC_FilterValue, 1, 59, 5, 0, // Skip to: 3943 -/* 2604 */ MCD_OPC_CheckPredicate, 5, 54, 5, 0, // Skip to: 3943 -/* 2609 */ MCD_OPC_Decode, 225, 2, 37, // Opcode: FMADD_D -/* 2613 */ MCD_OPC_FilterValue, 71, 31, 0, 0, // Skip to: 2649 -/* 2618 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... -/* 2621 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2635 -/* 2626 */ MCD_OPC_CheckPredicate, 4, 32, 5, 0, // Skip to: 3943 -/* 2631 */ MCD_OPC_Decode, 232, 2, 36, // Opcode: FMSUB_S -/* 2635 */ MCD_OPC_FilterValue, 1, 23, 5, 0, // Skip to: 3943 -/* 2640 */ MCD_OPC_CheckPredicate, 5, 18, 5, 0, // Skip to: 3943 -/* 2645 */ MCD_OPC_Decode, 231, 2, 37, // Opcode: FMSUB_D -/* 2649 */ MCD_OPC_FilterValue, 75, 31, 0, 0, // Skip to: 2685 -/* 2654 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... -/* 2657 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2671 -/* 2662 */ MCD_OPC_CheckPredicate, 4, 252, 4, 0, // Skip to: 3943 -/* 2667 */ MCD_OPC_Decode, 242, 2, 36, // Opcode: FNMSUB_S -/* 2671 */ MCD_OPC_FilterValue, 1, 243, 4, 0, // Skip to: 3943 -/* 2676 */ MCD_OPC_CheckPredicate, 5, 238, 4, 0, // Skip to: 3943 -/* 2681 */ MCD_OPC_Decode, 241, 2, 37, // Opcode: FNMSUB_D -/* 2685 */ MCD_OPC_FilterValue, 79, 31, 0, 0, // Skip to: 2721 -/* 2690 */ MCD_OPC_ExtractField, 25, 2, // Inst{26-25} ... -/* 2693 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2707 -/* 2698 */ MCD_OPC_CheckPredicate, 4, 216, 4, 0, // Skip to: 3943 -/* 2703 */ MCD_OPC_Decode, 240, 2, 36, // Opcode: FNMADD_S -/* 2707 */ MCD_OPC_FilterValue, 1, 207, 4, 0, // Skip to: 3943 -/* 2712 */ MCD_OPC_CheckPredicate, 5, 202, 4, 0, // Skip to: 3943 -/* 2717 */ MCD_OPC_Decode, 239, 2, 37, // Opcode: FNMADD_D -/* 2721 */ MCD_OPC_FilterValue, 83, 136, 3, 0, // Skip to: 3630 -/* 2726 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 2729 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2743 -/* 2734 */ MCD_OPC_CheckPredicate, 4, 180, 4, 0, // Skip to: 3943 -/* 2739 */ MCD_OPC_Decode, 191, 2, 38, // Opcode: FADD_S -/* 2743 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2757 -/* 2748 */ MCD_OPC_CheckPredicate, 5, 166, 4, 0, // Skip to: 3943 -/* 2753 */ MCD_OPC_Decode, 190, 2, 39, // Opcode: FADD_D -/* 2757 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2771 -/* 2762 */ MCD_OPC_CheckPredicate, 4, 152, 4, 0, // Skip to: 3943 -/* 2767 */ MCD_OPC_Decode, 253, 2, 38, // Opcode: FSUB_S -/* 2771 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2785 -/* 2776 */ MCD_OPC_CheckPredicate, 5, 138, 4, 0, // Skip to: 3943 -/* 2781 */ MCD_OPC_Decode, 252, 2, 39, // Opcode: FSUB_D -/* 2785 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2799 -/* 2790 */ MCD_OPC_CheckPredicate, 4, 124, 4, 0, // Skip to: 3943 -/* 2795 */ MCD_OPC_Decode, 234, 2, 38, // Opcode: FMUL_S -/* 2799 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2813 -/* 2804 */ MCD_OPC_CheckPredicate, 5, 110, 4, 0, // Skip to: 3943 -/* 2809 */ MCD_OPC_Decode, 233, 2, 39, // Opcode: FMUL_D -/* 2813 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2827 -/* 2818 */ MCD_OPC_CheckPredicate, 4, 96, 4, 0, // Skip to: 3943 -/* 2823 */ MCD_OPC_Decode, 213, 2, 38, // Opcode: FDIV_S -/* 2827 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2841 -/* 2832 */ MCD_OPC_CheckPredicate, 5, 82, 4, 0, // Skip to: 3943 -/* 2837 */ MCD_OPC_Decode, 212, 2, 39, // Opcode: FDIV_D -/* 2841 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 2891 -/* 2846 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2849 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2863 -/* 2854 */ MCD_OPC_CheckPredicate, 4, 60, 4, 0, // Skip to: 3943 -/* 2859 */ MCD_OPC_Decode, 249, 2, 40, // Opcode: FSGNJ_S -/* 2863 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2877 -/* 2868 */ MCD_OPC_CheckPredicate, 4, 46, 4, 0, // Skip to: 3943 -/* 2873 */ MCD_OPC_Decode, 245, 2, 40, // Opcode: FSGNJN_S -/* 2877 */ MCD_OPC_FilterValue, 2, 37, 4, 0, // Skip to: 3943 -/* 2882 */ MCD_OPC_CheckPredicate, 4, 32, 4, 0, // Skip to: 3943 -/* 2887 */ MCD_OPC_Decode, 247, 2, 40, // Opcode: FSGNJX_S -/* 2891 */ MCD_OPC_FilterValue, 17, 45, 0, 0, // Skip to: 2941 -/* 2896 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2899 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2913 -/* 2904 */ MCD_OPC_CheckPredicate, 5, 10, 4, 0, // Skip to: 3943 -/* 2909 */ MCD_OPC_Decode, 248, 2, 41, // Opcode: FSGNJ_D -/* 2913 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2927 -/* 2918 */ MCD_OPC_CheckPredicate, 5, 252, 3, 0, // Skip to: 3943 -/* 2923 */ MCD_OPC_Decode, 244, 2, 41, // Opcode: FSGNJN_D -/* 2927 */ MCD_OPC_FilterValue, 2, 243, 3, 0, // Skip to: 3943 -/* 2932 */ MCD_OPC_CheckPredicate, 5, 238, 3, 0, // Skip to: 3943 -/* 2937 */ MCD_OPC_Decode, 246, 2, 41, // Opcode: FSGNJX_D -/* 2941 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 2977 -/* 2946 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2949 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2963 -/* 2954 */ MCD_OPC_CheckPredicate, 4, 216, 3, 0, // Skip to: 3943 -/* 2959 */ MCD_OPC_Decode, 230, 2, 40, // Opcode: FMIN_S -/* 2963 */ MCD_OPC_FilterValue, 1, 207, 3, 0, // Skip to: 3943 -/* 2968 */ MCD_OPC_CheckPredicate, 4, 202, 3, 0, // Skip to: 3943 -/* 2973 */ MCD_OPC_Decode, 228, 2, 40, // Opcode: FMAX_S -/* 2977 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 3013 -/* 2982 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 2985 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2999 -/* 2990 */ MCD_OPC_CheckPredicate, 5, 180, 3, 0, // Skip to: 3943 -/* 2995 */ MCD_OPC_Decode, 229, 2, 41, // Opcode: FMIN_D -/* 2999 */ MCD_OPC_FilterValue, 1, 171, 3, 0, // Skip to: 3943 -/* 3004 */ MCD_OPC_CheckPredicate, 5, 166, 3, 0, // Skip to: 3943 -/* 3009 */ MCD_OPC_Decode, 227, 2, 41, // Opcode: FMAX_D -/* 3013 */ MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 3034 -/* 3018 */ MCD_OPC_CheckPredicate, 5, 152, 3, 0, // Skip to: 3943 -/* 3023 */ MCD_OPC_CheckField, 20, 5, 1, 145, 3, 0, // Skip to: 3943 -/* 3030 */ MCD_OPC_Decode, 203, 2, 42, // Opcode: FCVT_S_D -/* 3034 */ MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 3062 -/* 3039 */ MCD_OPC_CheckPredicate, 5, 131, 3, 0, // Skip to: 3943 -/* 3044 */ MCD_OPC_CheckField, 20, 5, 0, 124, 3, 0, // Skip to: 3943 -/* 3051 */ MCD_OPC_CheckField, 12, 3, 0, 117, 3, 0, // Skip to: 3943 -/* 3058 */ MCD_OPC_Decode, 196, 2, 43, // Opcode: FCVT_D_S -/* 3062 */ MCD_OPC_FilterValue, 44, 16, 0, 0, // Skip to: 3083 -/* 3067 */ MCD_OPC_CheckPredicate, 4, 103, 3, 0, // Skip to: 3943 -/* 3072 */ MCD_OPC_CheckField, 20, 5, 0, 96, 3, 0, // Skip to: 3943 -/* 3079 */ MCD_OPC_Decode, 251, 2, 44, // Opcode: FSQRT_S -/* 3083 */ MCD_OPC_FilterValue, 45, 16, 0, 0, // Skip to: 3104 -/* 3088 */ MCD_OPC_CheckPredicate, 5, 82, 3, 0, // Skip to: 3943 -/* 3093 */ MCD_OPC_CheckField, 20, 5, 0, 75, 3, 0, // Skip to: 3943 -/* 3100 */ MCD_OPC_Decode, 250, 2, 45, // Opcode: FSQRT_D -/* 3104 */ MCD_OPC_FilterValue, 80, 45, 0, 0, // Skip to: 3154 -/* 3109 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3112 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3126 -/* 3117 */ MCD_OPC_CheckPredicate, 4, 53, 3, 0, // Skip to: 3943 -/* 3122 */ MCD_OPC_Decode, 221, 2, 46, // Opcode: FLE_S -/* 3126 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3140 -/* 3131 */ MCD_OPC_CheckPredicate, 4, 39, 3, 0, // Skip to: 3943 -/* 3136 */ MCD_OPC_Decode, 223, 2, 46, // Opcode: FLT_S -/* 3140 */ MCD_OPC_FilterValue, 2, 30, 3, 0, // Skip to: 3943 -/* 3145 */ MCD_OPC_CheckPredicate, 4, 25, 3, 0, // Skip to: 3943 -/* 3150 */ MCD_OPC_Decode, 218, 2, 46, // Opcode: FEQ_S -/* 3154 */ MCD_OPC_FilterValue, 81, 45, 0, 0, // Skip to: 3204 -/* 3159 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3176 -/* 3167 */ MCD_OPC_CheckPredicate, 5, 3, 3, 0, // Skip to: 3943 -/* 3172 */ MCD_OPC_Decode, 220, 2, 47, // Opcode: FLE_D -/* 3176 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3190 -/* 3181 */ MCD_OPC_CheckPredicate, 5, 245, 2, 0, // Skip to: 3943 -/* 3186 */ MCD_OPC_Decode, 222, 2, 47, // Opcode: FLT_D -/* 3190 */ MCD_OPC_FilterValue, 2, 236, 2, 0, // Skip to: 3943 -/* 3195 */ MCD_OPC_CheckPredicate, 5, 231, 2, 0, // Skip to: 3943 -/* 3200 */ MCD_OPC_Decode, 217, 2, 47, // Opcode: FEQ_D -/* 3204 */ MCD_OPC_FilterValue, 96, 59, 0, 0, // Skip to: 3268 -/* 3209 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 3212 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3226 -/* 3217 */ MCD_OPC_CheckPredicate, 4, 209, 2, 0, // Skip to: 3943 -/* 3222 */ MCD_OPC_Decode, 211, 2, 48, // Opcode: FCVT_W_S -/* 3226 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3240 -/* 3231 */ MCD_OPC_CheckPredicate, 4, 195, 2, 0, // Skip to: 3943 -/* 3236 */ MCD_OPC_Decode, 209, 2, 48, // Opcode: FCVT_WU_S -/* 3240 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3254 -/* 3245 */ MCD_OPC_CheckPredicate, 10, 181, 2, 0, // Skip to: 3943 -/* 3250 */ MCD_OPC_Decode, 202, 2, 48, // Opcode: FCVT_L_S -/* 3254 */ MCD_OPC_FilterValue, 3, 172, 2, 0, // Skip to: 3943 -/* 3259 */ MCD_OPC_CheckPredicate, 10, 167, 2, 0, // Skip to: 3943 -/* 3264 */ MCD_OPC_Decode, 200, 2, 48, // Opcode: FCVT_LU_S -/* 3268 */ MCD_OPC_FilterValue, 97, 59, 0, 0, // Skip to: 3332 -/* 3273 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 3276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3290 -/* 3281 */ MCD_OPC_CheckPredicate, 5, 145, 2, 0, // Skip to: 3943 -/* 3286 */ MCD_OPC_Decode, 210, 2, 49, // Opcode: FCVT_W_D -/* 3290 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3304 -/* 3295 */ MCD_OPC_CheckPredicate, 5, 131, 2, 0, // Skip to: 3943 -/* 3300 */ MCD_OPC_Decode, 208, 2, 49, // Opcode: FCVT_WU_D -/* 3304 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3318 -/* 3309 */ MCD_OPC_CheckPredicate, 11, 117, 2, 0, // Skip to: 3943 -/* 3314 */ MCD_OPC_Decode, 201, 2, 49, // Opcode: FCVT_L_D -/* 3318 */ MCD_OPC_FilterValue, 3, 108, 2, 0, // Skip to: 3943 -/* 3323 */ MCD_OPC_CheckPredicate, 11, 103, 2, 0, // Skip to: 3943 -/* 3328 */ MCD_OPC_Decode, 199, 2, 49, // Opcode: FCVT_LU_D -/* 3332 */ MCD_OPC_FilterValue, 104, 59, 0, 0, // Skip to: 3396 -/* 3337 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 3340 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3354 -/* 3345 */ MCD_OPC_CheckPredicate, 4, 81, 2, 0, // Skip to: 3943 -/* 3350 */ MCD_OPC_Decode, 206, 2, 50, // Opcode: FCVT_S_W -/* 3354 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3368 -/* 3359 */ MCD_OPC_CheckPredicate, 4, 67, 2, 0, // Skip to: 3943 -/* 3364 */ MCD_OPC_Decode, 207, 2, 50, // Opcode: FCVT_S_WU -/* 3368 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3382 -/* 3373 */ MCD_OPC_CheckPredicate, 10, 53, 2, 0, // Skip to: 3943 -/* 3378 */ MCD_OPC_Decode, 204, 2, 50, // Opcode: FCVT_S_L -/* 3382 */ MCD_OPC_FilterValue, 3, 44, 2, 0, // Skip to: 3943 -/* 3387 */ MCD_OPC_CheckPredicate, 10, 39, 2, 0, // Skip to: 3943 -/* 3392 */ MCD_OPC_Decode, 205, 2, 50, // Opcode: FCVT_S_LU -/* 3396 */ MCD_OPC_FilterValue, 105, 73, 0, 0, // Skip to: 3474 -/* 3401 */ MCD_OPC_ExtractField, 20, 5, // Inst{24-20} ... -/* 3404 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3425 -/* 3409 */ MCD_OPC_CheckPredicate, 5, 17, 2, 0, // Skip to: 3943 -/* 3414 */ MCD_OPC_CheckField, 12, 3, 0, 10, 2, 0, // Skip to: 3943 -/* 3421 */ MCD_OPC_Decode, 197, 2, 51, // Opcode: FCVT_D_W -/* 3425 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3446 -/* 3430 */ MCD_OPC_CheckPredicate, 5, 252, 1, 0, // Skip to: 3943 -/* 3435 */ MCD_OPC_CheckField, 12, 3, 0, 245, 1, 0, // Skip to: 3943 -/* 3442 */ MCD_OPC_Decode, 198, 2, 51, // Opcode: FCVT_D_WU -/* 3446 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3460 -/* 3451 */ MCD_OPC_CheckPredicate, 11, 231, 1, 0, // Skip to: 3943 -/* 3456 */ MCD_OPC_Decode, 194, 2, 52, // Opcode: FCVT_D_L -/* 3460 */ MCD_OPC_FilterValue, 3, 222, 1, 0, // Skip to: 3943 -/* 3465 */ MCD_OPC_CheckPredicate, 11, 217, 1, 0, // Skip to: 3943 -/* 3470 */ MCD_OPC_Decode, 195, 2, 52, // Opcode: FCVT_D_LU -/* 3474 */ MCD_OPC_FilterValue, 112, 45, 0, 0, // Skip to: 3524 -/* 3479 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3482 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3503 -/* 3487 */ MCD_OPC_CheckPredicate, 4, 195, 1, 0, // Skip to: 3943 -/* 3492 */ MCD_OPC_CheckField, 20, 5, 0, 188, 1, 0, // Skip to: 3943 -/* 3499 */ MCD_OPC_Decode, 238, 2, 53, // Opcode: FMV_X_W -/* 3503 */ MCD_OPC_FilterValue, 1, 179, 1, 0, // Skip to: 3943 -/* 3508 */ MCD_OPC_CheckPredicate, 4, 174, 1, 0, // Skip to: 3943 -/* 3513 */ MCD_OPC_CheckField, 20, 5, 0, 167, 1, 0, // Skip to: 3943 -/* 3520 */ MCD_OPC_Decode, 193, 2, 53, // Opcode: FCLASS_S -/* 3524 */ MCD_OPC_FilterValue, 113, 45, 0, 0, // Skip to: 3574 -/* 3529 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3532 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3553 -/* 3537 */ MCD_OPC_CheckPredicate, 11, 145, 1, 0, // Skip to: 3943 -/* 3542 */ MCD_OPC_CheckField, 20, 5, 0, 138, 1, 0, // Skip to: 3943 -/* 3549 */ MCD_OPC_Decode, 237, 2, 54, // Opcode: FMV_X_D -/* 3553 */ MCD_OPC_FilterValue, 1, 129, 1, 0, // Skip to: 3943 -/* 3558 */ MCD_OPC_CheckPredicate, 5, 124, 1, 0, // Skip to: 3943 -/* 3563 */ MCD_OPC_CheckField, 20, 5, 0, 117, 1, 0, // Skip to: 3943 -/* 3570 */ MCD_OPC_Decode, 192, 2, 54, // Opcode: FCLASS_D -/* 3574 */ MCD_OPC_FilterValue, 120, 23, 0, 0, // Skip to: 3602 -/* 3579 */ MCD_OPC_CheckPredicate, 4, 103, 1, 0, // Skip to: 3943 -/* 3584 */ MCD_OPC_CheckField, 20, 5, 0, 96, 1, 0, // Skip to: 3943 -/* 3591 */ MCD_OPC_CheckField, 12, 3, 0, 89, 1, 0, // Skip to: 3943 -/* 3598 */ MCD_OPC_Decode, 236, 2, 55, // Opcode: FMV_W_X -/* 3602 */ MCD_OPC_FilterValue, 121, 80, 1, 0, // Skip to: 3943 -/* 3607 */ MCD_OPC_CheckPredicate, 11, 75, 1, 0, // Skip to: 3943 -/* 3612 */ MCD_OPC_CheckField, 20, 5, 0, 68, 1, 0, // Skip to: 3943 -/* 3619 */ MCD_OPC_CheckField, 12, 3, 0, 61, 1, 0, // Skip to: 3943 -/* 3626 */ MCD_OPC_Decode, 235, 2, 51, // Opcode: FMV_D_X -/* 3630 */ MCD_OPC_FilterValue, 99, 57, 0, 0, // Skip to: 3692 -/* 3635 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3638 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3647 -/* 3643 */ MCD_OPC_Decode, 129, 2, 56, // Opcode: BEQ -/* 3647 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 3656 -/* 3652 */ MCD_OPC_Decode, 134, 2, 56, // Opcode: BNE -/* 3656 */ MCD_OPC_FilterValue, 4, 4, 0, 0, // Skip to: 3665 -/* 3661 */ MCD_OPC_Decode, 132, 2, 56, // Opcode: BLT -/* 3665 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 3674 -/* 3670 */ MCD_OPC_Decode, 130, 2, 56, // Opcode: BGE -/* 3674 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 3683 -/* 3679 */ MCD_OPC_Decode, 133, 2, 56, // Opcode: BLTU -/* 3683 */ MCD_OPC_FilterValue, 7, 255, 0, 0, // Skip to: 3943 -/* 3688 */ MCD_OPC_Decode, 131, 2, 56, // Opcode: BGEU -/* 3692 */ MCD_OPC_FilterValue, 103, 11, 0, 0, // Skip to: 3708 -/* 3697 */ MCD_OPC_CheckField, 12, 3, 0, 239, 0, 0, // Skip to: 3943 -/* 3704 */ MCD_OPC_Decode, 128, 3, 24, // Opcode: JALR -/* 3708 */ MCD_OPC_FilterValue, 111, 4, 0, 0, // Skip to: 3717 -/* 3713 */ MCD_OPC_Decode, 255, 2, 57, // Opcode: JAL -/* 3717 */ MCD_OPC_FilterValue, 115, 221, 0, 0, // Skip to: 3943 -/* 3722 */ MCD_OPC_ExtractField, 12, 3, // Inst{14-12} ... -/* 3725 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 3869 -/* 3730 */ MCD_OPC_ExtractField, 25, 7, // Inst{31-25} ... -/* 3733 */ MCD_OPC_FilterValue, 0, 51, 0, 0, // Skip to: 3789 -/* 3738 */ MCD_OPC_ExtractField, 15, 10, // Inst{24-15} ... -/* 3741 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3757 -/* 3746 */ MCD_OPC_CheckField, 7, 5, 0, 190, 0, 0, // Skip to: 3943 -/* 3753 */ MCD_OPC_Decode, 189, 2, 0, // Opcode: ECALL -/* 3757 */ MCD_OPC_FilterValue, 32, 11, 0, 0, // Skip to: 3773 -/* 3762 */ MCD_OPC_CheckField, 7, 5, 0, 174, 0, 0, // Skip to: 3943 -/* 3769 */ MCD_OPC_Decode, 188, 2, 0, // Opcode: EBREAK -/* 3773 */ MCD_OPC_FilterValue, 64, 165, 0, 0, // Skip to: 3943 -/* 3778 */ MCD_OPC_CheckField, 7, 5, 0, 158, 0, 0, // Skip to: 3943 -/* 3785 */ MCD_OPC_Decode, 190, 3, 0, // Opcode: URET -/* 3789 */ MCD_OPC_FilterValue, 8, 36, 0, 0, // Skip to: 3830 -/* 3794 */ MCD_OPC_ExtractField, 15, 10, // Inst{24-15} ... -/* 3797 */ MCD_OPC_FilterValue, 64, 11, 0, 0, // Skip to: 3813 -/* 3802 */ MCD_OPC_CheckField, 7, 5, 0, 134, 0, 0, // Skip to: 3943 -/* 3809 */ MCD_OPC_Decode, 181, 3, 0, // Opcode: SRET -/* 3813 */ MCD_OPC_FilterValue, 160, 1, 124, 0, 0, // Skip to: 3943 -/* 3819 */ MCD_OPC_CheckField, 7, 5, 0, 117, 0, 0, // Skip to: 3943 -/* 3826 */ MCD_OPC_Decode, 191, 3, 0, // Opcode: WFI -/* 3830 */ MCD_OPC_FilterValue, 9, 11, 0, 0, // Skip to: 3846 -/* 3835 */ MCD_OPC_CheckField, 7, 5, 0, 101, 0, 0, // Skip to: 3943 -/* 3842 */ MCD_OPC_Decode, 167, 3, 58, // Opcode: SFENCE_VMA -/* 3846 */ MCD_OPC_FilterValue, 24, 92, 0, 0, // Skip to: 3943 -/* 3851 */ MCD_OPC_CheckField, 15, 10, 64, 85, 0, 0, // Skip to: 3943 -/* 3858 */ MCD_OPC_CheckField, 7, 5, 0, 78, 0, 0, // Skip to: 3943 -/* 3865 */ MCD_OPC_Decode, 145, 3, 0, // Opcode: MRET -/* 3869 */ MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3898 -/* 3874 */ MCD_OPC_CheckField, 15, 17, 128, 128, 6, 11, 0, 0, // Skip to: 3894 -/* 3883 */ MCD_OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 3894 -/* 3890 */ MCD_OPC_Decode, 189, 3, 0, // Opcode: UNIMP -/* 3894 */ MCD_OPC_Decode, 139, 2, 59, // Opcode: CSRRW -/* 3898 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 3907 -/* 3903 */ MCD_OPC_Decode, 137, 2, 59, // Opcode: CSRRS -/* 3907 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 3916 -/* 3912 */ MCD_OPC_Decode, 135, 2, 59, // Opcode: CSRRC -/* 3916 */ MCD_OPC_FilterValue, 5, 4, 0, 0, // Skip to: 3925 -/* 3921 */ MCD_OPC_Decode, 140, 2, 60, // Opcode: CSRRWI -/* 3925 */ MCD_OPC_FilterValue, 6, 4, 0, 0, // Skip to: 3934 -/* 3930 */ MCD_OPC_Decode, 138, 2, 60, // Opcode: CSRRSI -/* 3934 */ MCD_OPC_FilterValue, 7, 4, 0, 0, // Skip to: 3943 -/* 3939 */ MCD_OPC_Decode, 136, 2, 60, // Opcode: CSRRCI -/* 3943 */ MCD_OPC_Fail, - 0 -}; - -static const uint8_t DecoderTableRISCV32Only_16[] = { -/* 0 */ MCD_OPC_ExtractField, 0, 2, // Inst{1-0} ... -/* 3 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 39 -/* 8 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 11 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25 -/* 16 */ MCD_OPC_CheckPredicate, 12, 75, 0, 0, // Skip to: 96 -/* 21 */ MCD_OPC_Decode, 154, 2, 61, // Opcode: C_FLW -/* 25 */ MCD_OPC_FilterValue, 7, 66, 0, 0, // Skip to: 96 -/* 30 */ MCD_OPC_CheckPredicate, 12, 61, 0, 0, // Skip to: 96 -/* 35 */ MCD_OPC_Decode, 158, 2, 61, // Opcode: C_FSW -/* 39 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 60 -/* 44 */ MCD_OPC_CheckPredicate, 13, 47, 0, 0, // Skip to: 96 -/* 49 */ MCD_OPC_CheckField, 13, 3, 1, 40, 0, 0, // Skip to: 96 -/* 56 */ MCD_OPC_Decode, 161, 2, 19, // Opcode: C_JAL -/* 60 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 96 -/* 65 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 68 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 82 -/* 73 */ MCD_OPC_CheckPredicate, 12, 18, 0, 0, // Skip to: 96 -/* 78 */ MCD_OPC_Decode, 155, 2, 62, // Opcode: C_FLWSP -/* 82 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 96 -/* 87 */ MCD_OPC_CheckPredicate, 12, 4, 0, 0, // Skip to: 96 -/* 92 */ MCD_OPC_Decode, 159, 2, 63, // Opcode: C_FSWSP -/* 96 */ MCD_OPC_Fail, - 0 -}; - -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) -{ - switch (Idx) { - default: CS_ASSERT(0 && "Invalid index!"); - case 0: - return (Bits & RISCV_FeatureStdExtC); - case 1: - return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_FeatureStdExtD); - case 2: - return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_Feature64Bit); - case 3: - return (Bits & RISCV_Feature64Bit); - case 4: - return (Bits & RISCV_FeatureStdExtF); - case 5: - return (Bits & RISCV_FeatureStdExtD); - case 6: - return (Bits & RISCV_FeatureStdExtA); - case 7: - return (Bits & RISCV_FeatureStdExtA) && (Bits & RISCV_Feature64Bit); - case 8: - return (Bits & RISCV_FeatureStdExtM); - case 9: - return (Bits & RISCV_FeatureStdExtM) && (Bits & RISCV_Feature64Bit); - case 10: - return (Bits & RISCV_FeatureStdExtF) && (Bits & RISCV_Feature64Bit); - case 11: - return (Bits & RISCV_FeatureStdExtD) && (Bits & RISCV_Feature64Bit); - case 12: - return (Bits & RISCV_FeatureStdExtC) && (Bits & RISCV_FeatureStdExtF) && !(Bits & RISCV_Feature64Bit); - case 13: - return (Bits & RISCV_FeatureStdExtC) && !(Bits & RISCV_Feature64Bit); - } -} - -#define DecodeToMCInst(fname, fieldname, InsnType) \ -static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, const void *Decoder,\ - bool *DecodeComplete) {\ - *DecodeComplete = true;\ - InsnType tmp; \ - switch (Idx) { \ - default: CS_ASSERT(0 && "Invalid index!");\ - case 0: \ - return S; \ - case 1: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 3; \ - tmp |= fieldname(insn, 6, 1) << 2; \ - tmp |= fieldname(insn, 7, 4) << 6; \ - tmp |= fieldname(insn, 11, 2) << 4; \ - if (decodeUImmNonZeroOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 2: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 3: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 4: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeFPR64CRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 2) << 6; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 5: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 3) << 6; \ - tmp |= fieldname(insn, 5, 2) << 3; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 6: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 6; \ - tmp |= fieldname(insn, 6, 1) << 2; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 7: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 8: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 2) << 6; \ - tmp |= fieldname(insn, 4, 3) << 2; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 9: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 2) << 6; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 10: \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 5; \ - tmp |= fieldname(insn, 3, 2) << 7; \ - tmp |= fieldname(insn, 5, 1) << 6; \ - tmp |= fieldname(insn, 6, 1) << 4; \ - tmp |= fieldname(insn, 12, 1) << 9; \ - if (decodeSImmNonZeroOperand(MI, tmp, Address, Decoder, 10) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 11: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0X2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeCLUIImmOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 12: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 3) << 6; \ - tmp |= fieldname(insn, 5, 2) << 3; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 13: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 14: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 5) << 0; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 15: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 16: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 17: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 18: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 19: \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 4; \ - tmp |= fieldname(insn, 3, 3) << 0; \ - tmp |= fieldname(insn, 6, 1) << 6; \ - tmp |= fieldname(insn, 7, 1) << 5; \ - tmp |= fieldname(insn, 8, 1) << 9; \ - tmp |= fieldname(insn, 9, 2) << 7; \ - tmp |= fieldname(insn, 11, 1) << 3; \ - tmp |= fieldname(insn, 12, 1) << 10; \ - if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 20: \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 3) << 6; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 21: \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 1) << 4; \ - tmp |= fieldname(insn, 3, 2) << 0; \ - tmp |= fieldname(insn, 5, 2) << 5; \ - tmp |= fieldname(insn, 10, 2) << 2; \ - tmp |= fieldname(insn, 12, 1) << 7; \ - if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 22: \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 2) << 6; \ - tmp |= fieldname(insn, 9, 4) << 2; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 23: \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 3) << 6; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 9) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 24: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 25: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 26: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 27: \ - tmp = fieldname(insn, 24, 4); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 4); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 4) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 28: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 6); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 6) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 29: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 20); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 20) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 30: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 31: \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - tmp |= fieldname(insn, 25, 7) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 32: \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - tmp |= fieldname(insn, 25, 7) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 33: \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 5) << 0; \ - tmp |= fieldname(insn, 25, 7) << 5; \ - if (decodeSImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 34: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 35: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 36: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 27, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 37: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 27, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 38: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 39: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 40: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 41: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 42: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 43: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 44: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 45: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 46: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 47: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 48: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 49: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 50: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 51: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 52: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 53: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 54: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 55: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 56: \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 1) << 10; \ - tmp |= fieldname(insn, 8, 4) << 0; \ - tmp |= fieldname(insn, 25, 6) << 4; \ - tmp |= fieldname(insn, 31, 1) << 11; \ - if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 13) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 57: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 8) << 11; \ - tmp |= fieldname(insn, 20, 1) << 10; \ - tmp |= fieldname(insn, 21, 10) << 0; \ - tmp |= fieldname(insn, 31, 1) << 19; \ - if (decodeSImmOperandAndLsl1(MI, tmp, Address, Decoder, 21) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 58: \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 59: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 60: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 12); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 12) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 15, 5); \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 5) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 61: \ - tmp = fieldname(insn, 2, 3); \ - if (DecodeFPR32CRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 7, 3); \ - if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 5, 1) << 6; \ - tmp |= fieldname(insn, 6, 1) << 2; \ - tmp |= fieldname(insn, 10, 3) << 3; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 7) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 62: \ - tmp = fieldname(insn, 7, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 2, 2) << 6; \ - tmp |= fieldname(insn, 4, 3) << 2; \ - tmp |= fieldname(insn, 12, 1) << 5; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - case 63: \ - tmp = fieldname(insn, 2, 5); \ - if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 7, 2) << 6; \ - tmp |= fieldname(insn, 9, 4) << 2; \ - if (decodeUImmOperand(MI, tmp, Address, Decoder, 8) == MCDisassembler_Fail) return MCDisassembler_Fail; \ - return S; \ - } \ -} - -#define DecodeInstruction(fname, fieldname, decoder, InsnType) \ -static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI,\ - InsnType insn, uint64_t Address,\ - const void *DisAsm, int feature) {\ - uint64_t Bits = getFeatureBits(feature);\ -\ - const uint8_t *Ptr = DecodeTable;\ - uint32_t CurFieldValue = 0;\ - DecodeStatus S = MCDisassembler_Success;\ - while (true) {\ - switch (*Ptr) {\ - default:\ - return MCDisassembler_Fail;\ - case MCD_OPC_ExtractField: {\ - unsigned Start = *++Ptr;\ - unsigned Len = *++Ptr;\ - ++Ptr;\ - CurFieldValue = fieldname(insn, Start, Len);\ - break;\ - }\ - case MCD_OPC_FilterValue: {\ - unsigned Len;\ - InsnType Val = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned NumToSkip = *Ptr++;\ - NumToSkip |= (*Ptr++) << 8;\ - NumToSkip |= (*Ptr++) << 16;\ -\ - if (Val != CurFieldValue)\ - Ptr += NumToSkip;\ - break;\ - }\ - case MCD_OPC_CheckField: {\ - unsigned Start = *++Ptr;\ - unsigned Len = *++Ptr;\ - InsnType FieldValue = fieldname(insn, Start, Len);\ - uint32_t ExpectedValue = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned NumToSkip = *Ptr++;\ - NumToSkip |= (*Ptr++) << 8;\ - NumToSkip |= (*Ptr++) << 16;\ -\ - if (ExpectedValue != FieldValue)\ - Ptr += NumToSkip;\ - break;\ - }\ - case MCD_OPC_CheckPredicate: {\ - unsigned Len;\ - unsigned PIdx = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned NumToSkip = *Ptr++;\ - NumToSkip |= (*Ptr++) << 8;\ - NumToSkip |= (*Ptr++) << 16;\ - bool Pred;\ - if (!(Pred = checkDecoderPredicate(PIdx, Bits)))\ - Ptr += NumToSkip;\ - (void)Pred;\ - break;\ - }\ - case MCD_OPC_Decode: {\ - unsigned Len;\ - unsigned Opc = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned DecodeIdx = decodeULEB128(Ptr, &Len);\ - Ptr += Len;\ -\ - MCInst_clear(MI);\ - MCInst_setOpcode(MI, Opc);\ - bool DecodeComplete = false;\ - S = decoder(S, DecodeIdx, insn, MI, Address, DisAsm, &DecodeComplete);\ - CS_ASSERT(DecodeComplete);\ -\ - return S;\ - }\ - case MCD_OPC_TryDecode: {\ - unsigned Len;\ - unsigned Opc = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - unsigned DecodeIdx = decodeULEB128(Ptr, &Len);\ - Ptr += Len;\ - unsigned NumToSkip = *Ptr++;\ - NumToSkip |= (*Ptr++) << 8;\ - NumToSkip |= (*Ptr++) << 16;\ -\ - MCInst TmpMI = { 0 }; \ - MCInst_Init(&TmpMI, CS_ARCH_RISCV); \ - MCInst_setOpcode(&TmpMI, Opc);\ - bool DecodeComplete = false;\ - S = decoder(S, DecodeIdx, insn, &TmpMI, Address, DisAsm, &DecodeComplete);\ -\ - if (DecodeComplete) {\ - *MI = TmpMI;\ - return S;\ - } else {\ - CS_ASSERT(S == MCDisassembler_Fail);\ - Ptr += NumToSkip;\ - S = MCDisassembler_Success;\ - }\ - break;\ - }\ - case MCD_OPC_SoftFail: {\ - unsigned Len;\ - InsnType PositiveMask = decodeULEB128(++Ptr, &Len);\ - Ptr += Len;\ - InsnType NegativeMask = decodeULEB128(Ptr, &Len);\ - Ptr += Len;\ - bool Fail = (insn & PositiveMask) || (~insn & NegativeMask);\ - if (Fail)\ - S = MCDisassembler_SoftFail;\ - break;\ - }\ - case MCD_OPC_Fail: {\ - return MCDisassembler_Fail;\ - }\ - }\ - }\ - CS_ASSERT(0 && "bogosity detected in disassembler state machine!");\ -} - -// For RISCV instruction is 32 bits. -FieldFromInstruction(fieldFromInstruction, uint32_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) diff --git a/arch/RISCV/RISCVGenInsnNameMaps.inc b/arch/RISCV/RISCVGenInsnNameMaps.inc deleted file mode 100644 index 17d42bf9cc..0000000000 --- a/arch/RISCV/RISCVGenInsnNameMaps.inc +++ /dev/null @@ -1,275 +0,0 @@ -// This is auto-gen data for Capstone engine (www.capstone-engine.org) -// By Nguyen Anh Quynh - - { RISCV_INS_ADD, "add" }, - { RISCV_INS_ADDI, "addi" }, - { RISCV_INS_ADDIW, "addiw" }, - { RISCV_INS_ADDW, "addw" }, - { RISCV_INS_AMOADD_D, "amoadd.d" }, - { RISCV_INS_AMOADD_D_AQ, "amoadd.d.aq" }, - { RISCV_INS_AMOADD_D_AQ_RL, "amoadd.d.aqrl" }, - { RISCV_INS_AMOADD_D_RL, "amoadd.d.rl" }, - { RISCV_INS_AMOADD_W, "amoadd.w" }, - { RISCV_INS_AMOADD_W_AQ, "amoadd.w.aq" }, - { RISCV_INS_AMOADD_W_AQ_RL, "amoadd.w.aqrl" }, - { RISCV_INS_AMOADD_W_RL, "amoadd.w.rl" }, - { RISCV_INS_AMOAND_D, "amoand.d" }, - { RISCV_INS_AMOAND_D_AQ, "amoand.d.aq" }, - { RISCV_INS_AMOAND_D_AQ_RL, "amoand.d.aqrl" }, - { RISCV_INS_AMOAND_D_RL, "amoand.d.rl" }, - { RISCV_INS_AMOAND_W, "amoand.w" }, - { RISCV_INS_AMOAND_W_AQ, "amoand.w.aq" }, - { RISCV_INS_AMOAND_W_AQ_RL, "amoand.w.aqrl" }, - { RISCV_INS_AMOAND_W_RL, "amoand.w.rl" }, - { RISCV_INS_AMOMAXU_D, "amomaxu.d" }, - { RISCV_INS_AMOMAXU_D_AQ, "amomaxu.d.aq" }, - { RISCV_INS_AMOMAXU_D_AQ_RL, "amomaxu.d.aqrl" }, - { RISCV_INS_AMOMAXU_D_RL, "amomaxu.d.rl" }, - { RISCV_INS_AMOMAXU_W, "amomaxu.w" }, - { RISCV_INS_AMOMAXU_W_AQ, "amomaxu.w.aq" }, - { RISCV_INS_AMOMAXU_W_AQ_RL, "amomaxu.w.aqrl" }, - { RISCV_INS_AMOMAXU_W_RL, "amomaxu.w.rl" }, - { RISCV_INS_AMOMAX_D, "amomax.d" }, - { RISCV_INS_AMOMAX_D_AQ, "amomax.d.aq" }, - { RISCV_INS_AMOMAX_D_AQ_RL, "amomax.d.aqrl" }, - { RISCV_INS_AMOMAX_D_RL, "amomax.d.rl" }, - { RISCV_INS_AMOMAX_W, "amomax.w" }, - { RISCV_INS_AMOMAX_W_AQ, "amomax.w.aq" }, - { RISCV_INS_AMOMAX_W_AQ_RL, "amomax.w.aqrl" }, - { RISCV_INS_AMOMAX_W_RL, "amomax.w.rl" }, - { RISCV_INS_AMOMINU_D, "amominu.d" }, - { RISCV_INS_AMOMINU_D_AQ, "amominu.d.aq" }, - { RISCV_INS_AMOMINU_D_AQ_RL, "amominu.d.aqrl" }, - { RISCV_INS_AMOMINU_D_RL, "amominu.d.rl" }, - { RISCV_INS_AMOMINU_W, "amominu.w" }, - { RISCV_INS_AMOMINU_W_AQ, "amominu.w.aq" }, - { RISCV_INS_AMOMINU_W_AQ_RL, "amominu.w.aqrl" }, - { RISCV_INS_AMOMINU_W_RL, "amominu.w.rl" }, - { RISCV_INS_AMOMIN_D, "amomin.d" }, - { RISCV_INS_AMOMIN_D_AQ, "amomin.d.aq" }, - { RISCV_INS_AMOMIN_D_AQ_RL, "amomin.d.aqrl" }, - { RISCV_INS_AMOMIN_D_RL, "amomin.d.rl" }, - { RISCV_INS_AMOMIN_W, "amomin.w" }, - { RISCV_INS_AMOMIN_W_AQ, "amomin.w.aq" }, - { RISCV_INS_AMOMIN_W_AQ_RL, "amomin.w.aqrl" }, - { RISCV_INS_AMOMIN_W_RL, "amomin.w.rl" }, - { RISCV_INS_AMOOR_D, "amoor.d" }, - { RISCV_INS_AMOOR_D_AQ, "amoor.d.aq" }, - { RISCV_INS_AMOOR_D_AQ_RL, "amoor.d.aqrl" }, - { RISCV_INS_AMOOR_D_RL, "amoor.d.rl" }, - { RISCV_INS_AMOOR_W, "amoor.w" }, - { RISCV_INS_AMOOR_W_AQ, "amoor.w.aq" }, - { RISCV_INS_AMOOR_W_AQ_RL, "amoor.w.aqrl" }, - { RISCV_INS_AMOOR_W_RL, "amoor.w.rl" }, - { RISCV_INS_AMOSWAP_D, "amoswap.d" }, - { RISCV_INS_AMOSWAP_D_AQ, "amoswap.d.aq" }, - { RISCV_INS_AMOSWAP_D_AQ_RL, "amoswap.d.aqrl" }, - { RISCV_INS_AMOSWAP_D_RL, "amoswap.d.rl" }, - { RISCV_INS_AMOSWAP_W, "amoswap.w" }, - { RISCV_INS_AMOSWAP_W_AQ, "amoswap.w.aq" }, - { RISCV_INS_AMOSWAP_W_AQ_RL, "amoswap.w.aqrl" }, - { RISCV_INS_AMOSWAP_W_RL, "amoswap.w.rl" }, - { RISCV_INS_AMOXOR_D, "amoxor.d" }, - { RISCV_INS_AMOXOR_D_AQ, "amoxor.d.aq" }, - { RISCV_INS_AMOXOR_D_AQ_RL, "amoxor.d.aqrl" }, - { RISCV_INS_AMOXOR_D_RL, "amoxor.d.rl" }, - { RISCV_INS_AMOXOR_W, "amoxor.w" }, - { RISCV_INS_AMOXOR_W_AQ, "amoxor.w.aq" }, - { RISCV_INS_AMOXOR_W_AQ_RL, "amoxor.w.aqrl" }, - { RISCV_INS_AMOXOR_W_RL, "amoxor.w.rl" }, - { RISCV_INS_AND, "and" }, - { RISCV_INS_ANDI, "andi" }, - { RISCV_INS_AUIPC, "auipc" }, - { RISCV_INS_BEQ, "beq" }, - { RISCV_INS_BGE, "bge" }, - { RISCV_INS_BGEU, "bgeu" }, - { RISCV_INS_BLT, "blt" }, - { RISCV_INS_BLTU, "bltu" }, - { RISCV_INS_BNE, "bne" }, - { RISCV_INS_CSRRC, "csrrc" }, - { RISCV_INS_CSRRCI, "csrrci" }, - { RISCV_INS_CSRRS, "csrrs" }, - { RISCV_INS_CSRRSI, "csrrsi" }, - { RISCV_INS_CSRRW, "csrrw" }, - { RISCV_INS_CSRRWI, "csrrwi" }, - { RISCV_INS_C_ADD, "c.add" }, - { RISCV_INS_C_ADDI, "c.addi" }, - { RISCV_INS_C_ADDI16SP, "c.addi16sp" }, - { RISCV_INS_C_ADDI4SPN, "c.addi4spn" }, - { RISCV_INS_C_ADDIW, "c.addiw" }, - { RISCV_INS_C_ADDW, "c.addw" }, - { RISCV_INS_C_AND, "c.and" }, - { RISCV_INS_C_ANDI, "c.andi" }, - { RISCV_INS_C_BEQZ, "c.beqz" }, - { RISCV_INS_C_BNEZ, "c.bnez" }, - { RISCV_INS_C_EBREAK, "c.ebreak" }, - { RISCV_INS_C_FLD, "c.fld" }, - { RISCV_INS_C_FLDSP, "c.fldsp" }, - { RISCV_INS_C_FLW, "c.flw" }, - { RISCV_INS_C_FLWSP, "c.flwsp" }, - { RISCV_INS_C_FSD, "c.fsd" }, - { RISCV_INS_C_FSDSP, "c.fsdsp" }, - { RISCV_INS_C_FSW, "c.fsw" }, - { RISCV_INS_C_FSWSP, "c.fswsp" }, - { RISCV_INS_C_J, "c.j" }, - { RISCV_INS_C_JAL, "c.jal" }, - { RISCV_INS_C_JALR, "c.jalr" }, - { RISCV_INS_C_JR, "c.jr" }, - { RISCV_INS_C_LD, "c.ld" }, - { RISCV_INS_C_LDSP, "c.ldsp" }, - { RISCV_INS_C_LI, "c.li" }, - { RISCV_INS_C_LUI, "c.lui" }, - { RISCV_INS_C_LW, "c.lw" }, - { RISCV_INS_C_LWSP, "c.lwsp" }, - { RISCV_INS_C_MV, "c.mv" }, - { RISCV_INS_C_NOP, "c.nop" }, - { RISCV_INS_C_OR, "c.or" }, - { RISCV_INS_C_SD, "c.sd" }, - { RISCV_INS_C_SDSP, "c.sdsp" }, - { RISCV_INS_C_SLLI, "c.slli" }, - { RISCV_INS_C_SRAI, "c.srai" }, - { RISCV_INS_C_SRLI, "c.srli" }, - { RISCV_INS_C_SUB, "c.sub" }, - { RISCV_INS_C_SUBW, "c.subw" }, - { RISCV_INS_C_SW, "c.sw" }, - { RISCV_INS_C_SWSP, "c.swsp" }, - { RISCV_INS_C_UNIMP, "c.unimp" }, - { RISCV_INS_C_XOR, "c.xor" }, - { RISCV_INS_DIV, "div" }, - { RISCV_INS_DIVU, "divu" }, - { RISCV_INS_DIVUW, "divuw" }, - { RISCV_INS_DIVW, "divw" }, - { RISCV_INS_EBREAK, "ebreak" }, - { RISCV_INS_ECALL, "ecall" }, - { RISCV_INS_FADD_D, "fadd.d" }, - { RISCV_INS_FADD_S, "fadd.s" }, - { RISCV_INS_FCLASS_D, "fclass.d" }, - { RISCV_INS_FCLASS_S, "fclass.s" }, - { RISCV_INS_FCVT_D_L, "fcvt.d.l" }, - { RISCV_INS_FCVT_D_LU, "fcvt.d.lu" }, - { RISCV_INS_FCVT_D_S, "fcvt.d.s" }, - { RISCV_INS_FCVT_D_W, "fcvt.d.w" }, - { RISCV_INS_FCVT_D_WU, "fcvt.d.wu" }, - { RISCV_INS_FCVT_LU_D, "fcvt.lu.d" }, - { RISCV_INS_FCVT_LU_S, "fcvt.lu.s" }, - { RISCV_INS_FCVT_L_D, "fcvt.l.d" }, - { RISCV_INS_FCVT_L_S, "fcvt.l.s" }, - { RISCV_INS_FCVT_S_D, "fcvt.s.d" }, - { RISCV_INS_FCVT_S_L, "fcvt.s.l" }, - { RISCV_INS_FCVT_S_LU, "fcvt.s.lu" }, - { RISCV_INS_FCVT_S_W, "fcvt.s.w" }, - { RISCV_INS_FCVT_S_WU, "fcvt.s.wu" }, - { RISCV_INS_FCVT_WU_D, "fcvt.wu.d" }, - { RISCV_INS_FCVT_WU_S, "fcvt.wu.s" }, - { RISCV_INS_FCVT_W_D, "fcvt.w.d" }, - { RISCV_INS_FCVT_W_S, "fcvt.w.s" }, - { RISCV_INS_FDIV_D, "fdiv.d" }, - { RISCV_INS_FDIV_S, "fdiv.s" }, - { RISCV_INS_FENCE, "fence" }, - { RISCV_INS_FENCE_I, "fence.i" }, - { RISCV_INS_FENCE_TSO, "fence.tso" }, - { RISCV_INS_FEQ_D, "feq.d" }, - { RISCV_INS_FEQ_S, "feq.s" }, - { RISCV_INS_FLD, "fld" }, - { RISCV_INS_FLE_D, "fle.d" }, - { RISCV_INS_FLE_S, "fle.s" }, - { RISCV_INS_FLT_D, "flt.d" }, - { RISCV_INS_FLT_S, "flt.s" }, - { RISCV_INS_FLW, "flw" }, - { RISCV_INS_FMADD_D, "fmadd.d" }, - { RISCV_INS_FMADD_S, "fmadd.s" }, - { RISCV_INS_FMAX_D, "fmax.d" }, - { RISCV_INS_FMAX_S, "fmax.s" }, - { RISCV_INS_FMIN_D, "fmin.d" }, - { RISCV_INS_FMIN_S, "fmin.s" }, - { RISCV_INS_FMSUB_D, "fmsub.d" }, - { RISCV_INS_FMSUB_S, "fmsub.s" }, - { RISCV_INS_FMUL_D, "fmul.d" }, - { RISCV_INS_FMUL_S, "fmul.s" }, - { RISCV_INS_FMV_D_X, "fmv.d.x" }, - { RISCV_INS_FMV_W_X, "fmv.w.x" }, - { RISCV_INS_FMV_X_D, "fmv.x.d" }, - { RISCV_INS_FMV_X_W, "fmv.x.w" }, - { RISCV_INS_FNMADD_D, "fnmadd.d" }, - { RISCV_INS_FNMADD_S, "fnmadd.s" }, - { RISCV_INS_FNMSUB_D, "fnmsub.d" }, - { RISCV_INS_FNMSUB_S, "fnmsub.s" }, - { RISCV_INS_FSD, "fsd" }, - { RISCV_INS_FSGNJN_D, "fsgnjn.d" }, - { RISCV_INS_FSGNJN_S, "fsgnjn.s" }, - { RISCV_INS_FSGNJX_D, "fsgnjx.d" }, - { RISCV_INS_FSGNJX_S, "fsgnjx.s" }, - { RISCV_INS_FSGNJ_D, "fsgnj.d" }, - { RISCV_INS_FSGNJ_S, "fsgnj.s" }, - { RISCV_INS_FSQRT_D, "fsqrt.d" }, - { RISCV_INS_FSQRT_S, "fsqrt.s" }, - { RISCV_INS_FSUB_D, "fsub.d" }, - { RISCV_INS_FSUB_S, "fsub.s" }, - { RISCV_INS_FSW, "fsw" }, - { RISCV_INS_JAL, "jal" }, - { RISCV_INS_JALR, "jalr" }, - { RISCV_INS_LB, "lb" }, - { RISCV_INS_LBU, "lbu" }, - { RISCV_INS_LD, "ld" }, - { RISCV_INS_LH, "lh" }, - { RISCV_INS_LHU, "lhu" }, - { RISCV_INS_LR_D, "lr.d" }, - { RISCV_INS_LR_D_AQ, "lr.d.aq" }, - { RISCV_INS_LR_D_AQ_RL, "lr.d.aqrl" }, - { RISCV_INS_LR_D_RL, "lr.d.rl" }, - { RISCV_INS_LR_W, "lr.w" }, - { RISCV_INS_LR_W_AQ, "lr.w.aq" }, - { RISCV_INS_LR_W_AQ_RL, "lr.w.aqrl" }, - { RISCV_INS_LR_W_RL, "lr.w.rl" }, - { RISCV_INS_LUI, "lui" }, - { RISCV_INS_LW, "lw" }, - { RISCV_INS_LWU, "lwu" }, - { RISCV_INS_MRET, "mret" }, - { RISCV_INS_MUL, "mul" }, - { RISCV_INS_MULH, "mulh" }, - { RISCV_INS_MULHSU, "mulhsu" }, - { RISCV_INS_MULHU, "mulhu" }, - { RISCV_INS_MULW, "mulw" }, - { RISCV_INS_OR, "or" }, - { RISCV_INS_ORI, "ori" }, - { RISCV_INS_REM, "rem" }, - { RISCV_INS_REMU, "remu" }, - { RISCV_INS_REMUW, "remuw" }, - { RISCV_INS_REMW, "remw" }, - { RISCV_INS_SB, "sb" }, - { RISCV_INS_SC_D, "sc.d" }, - { RISCV_INS_SC_D_AQ, "sc.d.aq" }, - { RISCV_INS_SC_D_AQ_RL, "sc.d.aqrl" }, - { RISCV_INS_SC_D_RL, "sc.d.rl" }, - { RISCV_INS_SC_W, "sc.w" }, - { RISCV_INS_SC_W_AQ, "sc.w.aq" }, - { RISCV_INS_SC_W_AQ_RL, "sc.w.aqrl" }, - { RISCV_INS_SC_W_RL, "sc.w.rl" }, - { RISCV_INS_SD, "sd" }, - { RISCV_INS_SFENCE_VMA, "sfence.vma" }, - { RISCV_INS_SH, "sh" }, - { RISCV_INS_SLL, "sll" }, - { RISCV_INS_SLLI, "slli" }, - { RISCV_INS_SLLIW, "slliw" }, - { RISCV_INS_SLLW, "sllw" }, - { RISCV_INS_SLT, "slt" }, - { RISCV_INS_SLTI, "slti" }, - { RISCV_INS_SLTIU, "sltiu" }, - { RISCV_INS_SLTU, "sltu" }, - { RISCV_INS_SRA, "sra" }, - { RISCV_INS_SRAI, "srai" }, - { RISCV_INS_SRAIW, "sraiw" }, - { RISCV_INS_SRAW, "sraw" }, - { RISCV_INS_SRET, "sret" }, - { RISCV_INS_SRL, "srl" }, - { RISCV_INS_SRLI, "srli" }, - { RISCV_INS_SRLIW, "srliw" }, - { RISCV_INS_SRLW, "srlw" }, - { RISCV_INS_SUB, "sub" }, - { RISCV_INS_SUBW, "subw" }, - { RISCV_INS_SW, "sw" }, - { RISCV_INS_UNIMP, "unimp" }, - { RISCV_INS_URET, "uret" }, - { RISCV_INS_WFI, "wfi" }, - { RISCV_INS_XOR, "xor" }, - { RISCV_INS_XORI, "xori" }, diff --git a/arch/RISCV/RISCVGenInstrInfo.inc b/arch/RISCV/RISCVGenInstrInfo.inc deleted file mode 100644 index 069892e176..0000000000 --- a/arch/RISCV/RISCVGenInstrInfo.inc +++ /dev/null @@ -1,470 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* Target Instruction Enum Values and Descriptors *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - -#ifdef GET_INSTRINFO_ENUM -#undef GET_INSTRINFO_ENUM - -enum { - RISCV_PHI = 0, - RISCV_INLINEASM = 1, - RISCV_INLINEASM_BR = 2, - RISCV_CFI_INSTRUCTION = 3, - RISCV_EH_LABEL = 4, - RISCV_GC_LABEL = 5, - RISCV_ANNOTATION_LABEL = 6, - RISCV_KILL = 7, - RISCV_EXTRACT_SUBREG = 8, - RISCV_INSERT_SUBREG = 9, - RISCV_IMPLICIT_DEF = 10, - RISCV_SUBREG_TO_REG = 11, - RISCV_COPY_TO_REGCLASS = 12, - RISCV_DBG_VALUE = 13, - RISCV_DBG_LABEL = 14, - RISCV_REG_SEQUENCE = 15, - RISCV_COPY = 16, - RISCV_BUNDLE = 17, - RISCV_LIFETIME_START = 18, - RISCV_LIFETIME_END = 19, - RISCV_STACKMAP = 20, - RISCV_FENTRY_CALL = 21, - RISCV_PATCHPOINT = 22, - RISCV_LOAD_STACK_GUARD = 23, - RISCV_STATEPOINT = 24, - RISCV_LOCAL_ESCAPE = 25, - RISCV_FAULTING_OP = 26, - RISCV_PATCHABLE_OP = 27, - RISCV_PATCHABLE_FUNCTION_ENTER = 28, - RISCV_PATCHABLE_RET = 29, - RISCV_PATCHABLE_FUNCTION_EXIT = 30, - RISCV_PATCHABLE_TAIL_CALL = 31, - RISCV_PATCHABLE_EVENT_CALL = 32, - RISCV_PATCHABLE_TYPED_EVENT_CALL = 33, - RISCV_ICALL_BRANCH_FUNNEL = 34, - RISCV_G_ADD = 35, - RISCV_G_SUB = 36, - RISCV_G_MUL = 37, - RISCV_G_SDIV = 38, - RISCV_G_UDIV = 39, - RISCV_G_SREM = 40, - RISCV_G_UREM = 41, - RISCV_G_AND = 42, - RISCV_G_OR = 43, - RISCV_G_XOR = 44, - RISCV_G_IMPLICIT_DEF = 45, - RISCV_G_PHI = 46, - RISCV_G_FRAME_INDEX = 47, - RISCV_G_GLOBAL_VALUE = 48, - RISCV_G_EXTRACT = 49, - RISCV_G_UNMERGE_VALUES = 50, - RISCV_G_INSERT = 51, - RISCV_G_MERGE_VALUES = 52, - RISCV_G_BUILD_VECTOR = 53, - RISCV_G_BUILD_VECTOR_TRUNC = 54, - RISCV_G_CONCAT_VECTORS = 55, - RISCV_G_PTRTOINT = 56, - RISCV_G_INTTOPTR = 57, - RISCV_G_BITCAST = 58, - RISCV_G_INTRINSIC_TRUNC = 59, - RISCV_G_INTRINSIC_ROUND = 60, - RISCV_G_LOAD = 61, - RISCV_G_SEXTLOAD = 62, - RISCV_G_ZEXTLOAD = 63, - RISCV_G_STORE = 64, - RISCV_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65, - RISCV_G_ATOMIC_CMPXCHG = 66, - RISCV_G_ATOMICRMW_XCHG = 67, - RISCV_G_ATOMICRMW_ADD = 68, - RISCV_G_ATOMICRMW_SUB = 69, - RISCV_G_ATOMICRMW_AND = 70, - RISCV_G_ATOMICRMW_NAND = 71, - RISCV_G_ATOMICRMW_OR = 72, - RISCV_G_ATOMICRMW_XOR = 73, - RISCV_G_ATOMICRMW_MAX = 74, - RISCV_G_ATOMICRMW_MIN = 75, - RISCV_G_ATOMICRMW_UMAX = 76, - RISCV_G_ATOMICRMW_UMIN = 77, - RISCV_G_BRCOND = 78, - RISCV_G_BRINDIRECT = 79, - RISCV_G_INTRINSIC = 80, - RISCV_G_INTRINSIC_W_SIDE_EFFECTS = 81, - RISCV_G_ANYEXT = 82, - RISCV_G_TRUNC = 83, - RISCV_G_CONSTANT = 84, - RISCV_G_FCONSTANT = 85, - RISCV_G_VASTART = 86, - RISCV_G_VAARG = 87, - RISCV_G_SEXT = 88, - RISCV_G_ZEXT = 89, - RISCV_G_SHL = 90, - RISCV_G_LSHR = 91, - RISCV_G_ASHR = 92, - RISCV_G_ICMP = 93, - RISCV_G_FCMP = 94, - RISCV_G_SELECT = 95, - RISCV_G_UADDO = 96, - RISCV_G_UADDE = 97, - RISCV_G_USUBO = 98, - RISCV_G_USUBE = 99, - RISCV_G_SADDO = 100, - RISCV_G_SADDE = 101, - RISCV_G_SSUBO = 102, - RISCV_G_SSUBE = 103, - RISCV_G_UMULO = 104, - RISCV_G_SMULO = 105, - RISCV_G_UMULH = 106, - RISCV_G_SMULH = 107, - RISCV_G_FADD = 108, - RISCV_G_FSUB = 109, - RISCV_G_FMUL = 110, - RISCV_G_FMA = 111, - RISCV_G_FDIV = 112, - RISCV_G_FREM = 113, - RISCV_G_FPOW = 114, - RISCV_G_FEXP = 115, - RISCV_G_FEXP2 = 116, - RISCV_G_FLOG = 117, - RISCV_G_FLOG2 = 118, - RISCV_G_FLOG10 = 119, - RISCV_G_FNEG = 120, - RISCV_G_FPEXT = 121, - RISCV_G_FPTRUNC = 122, - RISCV_G_FPTOSI = 123, - RISCV_G_FPTOUI = 124, - RISCV_G_SITOFP = 125, - RISCV_G_UITOFP = 126, - RISCV_G_FABS = 127, - RISCV_G_FCANONICALIZE = 128, - RISCV_G_GEP = 129, - RISCV_G_PTR_MASK = 130, - RISCV_G_BR = 131, - RISCV_G_INSERT_VECTOR_ELT = 132, - RISCV_G_EXTRACT_VECTOR_ELT = 133, - RISCV_G_SHUFFLE_VECTOR = 134, - RISCV_G_CTTZ = 135, - RISCV_G_CTTZ_ZERO_UNDEF = 136, - RISCV_G_CTLZ = 137, - RISCV_G_CTLZ_ZERO_UNDEF = 138, - RISCV_G_CTPOP = 139, - RISCV_G_BSWAP = 140, - RISCV_G_FCEIL = 141, - RISCV_G_FCOS = 142, - RISCV_G_FSIN = 143, - RISCV_G_FSQRT = 144, - RISCV_G_FFLOOR = 145, - RISCV_G_ADDRSPACE_CAST = 146, - RISCV_G_BLOCK_ADDR = 147, - RISCV_ADJCALLSTACKDOWN = 148, - RISCV_ADJCALLSTACKUP = 149, - RISCV_BuildPairF64Pseudo = 150, - RISCV_PseudoAtomicLoadNand32 = 151, - RISCV_PseudoAtomicLoadNand64 = 152, - RISCV_PseudoBR = 153, - RISCV_PseudoBRIND = 154, - RISCV_PseudoCALL = 155, - RISCV_PseudoCALLIndirect = 156, - RISCV_PseudoCmpXchg32 = 157, - RISCV_PseudoCmpXchg64 = 158, - RISCV_PseudoLA = 159, - RISCV_PseudoLI = 160, - RISCV_PseudoLLA = 161, - RISCV_PseudoMaskedAtomicLoadAdd32 = 162, - RISCV_PseudoMaskedAtomicLoadMax32 = 163, - RISCV_PseudoMaskedAtomicLoadMin32 = 164, - RISCV_PseudoMaskedAtomicLoadNand32 = 165, - RISCV_PseudoMaskedAtomicLoadSub32 = 166, - RISCV_PseudoMaskedAtomicLoadUMax32 = 167, - RISCV_PseudoMaskedAtomicLoadUMin32 = 168, - RISCV_PseudoMaskedAtomicSwap32 = 169, - RISCV_PseudoMaskedCmpXchg32 = 170, - RISCV_PseudoRET = 171, - RISCV_PseudoTAIL = 172, - RISCV_PseudoTAILIndirect = 173, - RISCV_Select_FPR32_Using_CC_GPR = 174, - RISCV_Select_FPR64_Using_CC_GPR = 175, - RISCV_Select_GPR_Using_CC_GPR = 176, - RISCV_SplitF64Pseudo = 177, - RISCV_ADD = 178, - RISCV_ADDI = 179, - RISCV_ADDIW = 180, - RISCV_ADDW = 181, - RISCV_AMOADD_D = 182, - RISCV_AMOADD_D_AQ = 183, - RISCV_AMOADD_D_AQ_RL = 184, - RISCV_AMOADD_D_RL = 185, - RISCV_AMOADD_W = 186, - RISCV_AMOADD_W_AQ = 187, - RISCV_AMOADD_W_AQ_RL = 188, - RISCV_AMOADD_W_RL = 189, - RISCV_AMOAND_D = 190, - RISCV_AMOAND_D_AQ = 191, - RISCV_AMOAND_D_AQ_RL = 192, - RISCV_AMOAND_D_RL = 193, - RISCV_AMOAND_W = 194, - RISCV_AMOAND_W_AQ = 195, - RISCV_AMOAND_W_AQ_RL = 196, - RISCV_AMOAND_W_RL = 197, - RISCV_AMOMAXU_D = 198, - RISCV_AMOMAXU_D_AQ = 199, - RISCV_AMOMAXU_D_AQ_RL = 200, - RISCV_AMOMAXU_D_RL = 201, - RISCV_AMOMAXU_W = 202, - RISCV_AMOMAXU_W_AQ = 203, - RISCV_AMOMAXU_W_AQ_RL = 204, - RISCV_AMOMAXU_W_RL = 205, - RISCV_AMOMAX_D = 206, - RISCV_AMOMAX_D_AQ = 207, - RISCV_AMOMAX_D_AQ_RL = 208, - RISCV_AMOMAX_D_RL = 209, - RISCV_AMOMAX_W = 210, - RISCV_AMOMAX_W_AQ = 211, - RISCV_AMOMAX_W_AQ_RL = 212, - RISCV_AMOMAX_W_RL = 213, - RISCV_AMOMINU_D = 214, - RISCV_AMOMINU_D_AQ = 215, - RISCV_AMOMINU_D_AQ_RL = 216, - RISCV_AMOMINU_D_RL = 217, - RISCV_AMOMINU_W = 218, - RISCV_AMOMINU_W_AQ = 219, - RISCV_AMOMINU_W_AQ_RL = 220, - RISCV_AMOMINU_W_RL = 221, - RISCV_AMOMIN_D = 222, - RISCV_AMOMIN_D_AQ = 223, - RISCV_AMOMIN_D_AQ_RL = 224, - RISCV_AMOMIN_D_RL = 225, - RISCV_AMOMIN_W = 226, - RISCV_AMOMIN_W_AQ = 227, - RISCV_AMOMIN_W_AQ_RL = 228, - RISCV_AMOMIN_W_RL = 229, - RISCV_AMOOR_D = 230, - RISCV_AMOOR_D_AQ = 231, - RISCV_AMOOR_D_AQ_RL = 232, - RISCV_AMOOR_D_RL = 233, - RISCV_AMOOR_W = 234, - RISCV_AMOOR_W_AQ = 235, - RISCV_AMOOR_W_AQ_RL = 236, - RISCV_AMOOR_W_RL = 237, - RISCV_AMOSWAP_D = 238, - RISCV_AMOSWAP_D_AQ = 239, - RISCV_AMOSWAP_D_AQ_RL = 240, - RISCV_AMOSWAP_D_RL = 241, - RISCV_AMOSWAP_W = 242, - RISCV_AMOSWAP_W_AQ = 243, - RISCV_AMOSWAP_W_AQ_RL = 244, - RISCV_AMOSWAP_W_RL = 245, - RISCV_AMOXOR_D = 246, - RISCV_AMOXOR_D_AQ = 247, - RISCV_AMOXOR_D_AQ_RL = 248, - RISCV_AMOXOR_D_RL = 249, - RISCV_AMOXOR_W = 250, - RISCV_AMOXOR_W_AQ = 251, - RISCV_AMOXOR_W_AQ_RL = 252, - RISCV_AMOXOR_W_RL = 253, - RISCV_AND = 254, - RISCV_ANDI = 255, - RISCV_AUIPC = 256, - RISCV_BEQ = 257, - RISCV_BGE = 258, - RISCV_BGEU = 259, - RISCV_BLT = 260, - RISCV_BLTU = 261, - RISCV_BNE = 262, - RISCV_CSRRC = 263, - RISCV_CSRRCI = 264, - RISCV_CSRRS = 265, - RISCV_CSRRSI = 266, - RISCV_CSRRW = 267, - RISCV_CSRRWI = 268, - RISCV_C_ADD = 269, - RISCV_C_ADDI = 270, - RISCV_C_ADDI16SP = 271, - RISCV_C_ADDI4SPN = 272, - RISCV_C_ADDIW = 273, - RISCV_C_ADDW = 274, - RISCV_C_AND = 275, - RISCV_C_ANDI = 276, - RISCV_C_BEQZ = 277, - RISCV_C_BNEZ = 278, - RISCV_C_EBREAK = 279, - RISCV_C_FLD = 280, - RISCV_C_FLDSP = 281, - RISCV_C_FLW = 282, - RISCV_C_FLWSP = 283, - RISCV_C_FSD = 284, - RISCV_C_FSDSP = 285, - RISCV_C_FSW = 286, - RISCV_C_FSWSP = 287, - RISCV_C_J = 288, - RISCV_C_JAL = 289, - RISCV_C_JALR = 290, - RISCV_C_JR = 291, - RISCV_C_LD = 292, - RISCV_C_LDSP = 293, - RISCV_C_LI = 294, - RISCV_C_LUI = 295, - RISCV_C_LW = 296, - RISCV_C_LWSP = 297, - RISCV_C_MV = 298, - RISCV_C_NOP = 299, - RISCV_C_OR = 300, - RISCV_C_SD = 301, - RISCV_C_SDSP = 302, - RISCV_C_SLLI = 303, - RISCV_C_SRAI = 304, - RISCV_C_SRLI = 305, - RISCV_C_SUB = 306, - RISCV_C_SUBW = 307, - RISCV_C_SW = 308, - RISCV_C_SWSP = 309, - RISCV_C_UNIMP = 310, - RISCV_C_XOR = 311, - RISCV_DIV = 312, - RISCV_DIVU = 313, - RISCV_DIVUW = 314, - RISCV_DIVW = 315, - RISCV_EBREAK = 316, - RISCV_ECALL = 317, - RISCV_FADD_D = 318, - RISCV_FADD_S = 319, - RISCV_FCLASS_D = 320, - RISCV_FCLASS_S = 321, - RISCV_FCVT_D_L = 322, - RISCV_FCVT_D_LU = 323, - RISCV_FCVT_D_S = 324, - RISCV_FCVT_D_W = 325, - RISCV_FCVT_D_WU = 326, - RISCV_FCVT_LU_D = 327, - RISCV_FCVT_LU_S = 328, - RISCV_FCVT_L_D = 329, - RISCV_FCVT_L_S = 330, - RISCV_FCVT_S_D = 331, - RISCV_FCVT_S_L = 332, - RISCV_FCVT_S_LU = 333, - RISCV_FCVT_S_W = 334, - RISCV_FCVT_S_WU = 335, - RISCV_FCVT_WU_D = 336, - RISCV_FCVT_WU_S = 337, - RISCV_FCVT_W_D = 338, - RISCV_FCVT_W_S = 339, - RISCV_FDIV_D = 340, - RISCV_FDIV_S = 341, - RISCV_FENCE = 342, - RISCV_FENCE_I = 343, - RISCV_FENCE_TSO = 344, - RISCV_FEQ_D = 345, - RISCV_FEQ_S = 346, - RISCV_FLD = 347, - RISCV_FLE_D = 348, - RISCV_FLE_S = 349, - RISCV_FLT_D = 350, - RISCV_FLT_S = 351, - RISCV_FLW = 352, - RISCV_FMADD_D = 353, - RISCV_FMADD_S = 354, - RISCV_FMAX_D = 355, - RISCV_FMAX_S = 356, - RISCV_FMIN_D = 357, - RISCV_FMIN_S = 358, - RISCV_FMSUB_D = 359, - RISCV_FMSUB_S = 360, - RISCV_FMUL_D = 361, - RISCV_FMUL_S = 362, - RISCV_FMV_D_X = 363, - RISCV_FMV_W_X = 364, - RISCV_FMV_X_D = 365, - RISCV_FMV_X_W = 366, - RISCV_FNMADD_D = 367, - RISCV_FNMADD_S = 368, - RISCV_FNMSUB_D = 369, - RISCV_FNMSUB_S = 370, - RISCV_FSD = 371, - RISCV_FSGNJN_D = 372, - RISCV_FSGNJN_S = 373, - RISCV_FSGNJX_D = 374, - RISCV_FSGNJX_S = 375, - RISCV_FSGNJ_D = 376, - RISCV_FSGNJ_S = 377, - RISCV_FSQRT_D = 378, - RISCV_FSQRT_S = 379, - RISCV_FSUB_D = 380, - RISCV_FSUB_S = 381, - RISCV_FSW = 382, - RISCV_JAL = 383, - RISCV_JALR = 384, - RISCV_LB = 385, - RISCV_LBU = 386, - RISCV_LD = 387, - RISCV_LH = 388, - RISCV_LHU = 389, - RISCV_LR_D = 390, - RISCV_LR_D_AQ = 391, - RISCV_LR_D_AQ_RL = 392, - RISCV_LR_D_RL = 393, - RISCV_LR_W = 394, - RISCV_LR_W_AQ = 395, - RISCV_LR_W_AQ_RL = 396, - RISCV_LR_W_RL = 397, - RISCV_LUI = 398, - RISCV_LW = 399, - RISCV_LWU = 400, - RISCV_MRET = 401, - RISCV_MUL = 402, - RISCV_MULH = 403, - RISCV_MULHSU = 404, - RISCV_MULHU = 405, - RISCV_MULW = 406, - RISCV_OR = 407, - RISCV_ORI = 408, - RISCV_REM = 409, - RISCV_REMU = 410, - RISCV_REMUW = 411, - RISCV_REMW = 412, - RISCV_SB = 413, - RISCV_SC_D = 414, - RISCV_SC_D_AQ = 415, - RISCV_SC_D_AQ_RL = 416, - RISCV_SC_D_RL = 417, - RISCV_SC_W = 418, - RISCV_SC_W_AQ = 419, - RISCV_SC_W_AQ_RL = 420, - RISCV_SC_W_RL = 421, - RISCV_SD = 422, - RISCV_SFENCE_VMA = 423, - RISCV_SH = 424, - RISCV_SLL = 425, - RISCV_SLLI = 426, - RISCV_SLLIW = 427, - RISCV_SLLW = 428, - RISCV_SLT = 429, - RISCV_SLTI = 430, - RISCV_SLTIU = 431, - RISCV_SLTU = 432, - RISCV_SRA = 433, - RISCV_SRAI = 434, - RISCV_SRAIW = 435, - RISCV_SRAW = 436, - RISCV_SRET = 437, - RISCV_SRL = 438, - RISCV_SRLI = 439, - RISCV_SRLIW = 440, - RISCV_SRLW = 441, - RISCV_SUB = 442, - RISCV_SUBW = 443, - RISCV_SW = 444, - RISCV_UNIMP = 445, - RISCV_URET = 446, - RISCV_WFI = 447, - RISCV_XOR = 448, - RISCV_XORI = 449, - RISCV_INSTRUCTION_LIST_END = 450 - }; - -#endif // GET_INSTRINFO_ENUM diff --git a/arch/RISCV/RISCVGenRegisterInfo.inc b/arch/RISCV/RISCVGenRegisterInfo.inc deleted file mode 100644 index 1eab56bf3b..0000000000 --- a/arch/RISCV/RISCVGenRegisterInfo.inc +++ /dev/null @@ -1,426 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* Target Register Enum Values *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - -#ifdef GET_REGINFO_ENUM -#undef GET_REGINFO_ENUM - -enum { - RISCV_NoRegister, - RISCV_X0 = 1, - RISCV_X1 = 2, - RISCV_X2 = 3, - RISCV_X3 = 4, - RISCV_X4 = 5, - RISCV_X5 = 6, - RISCV_X6 = 7, - RISCV_X7 = 8, - RISCV_X8 = 9, - RISCV_X9 = 10, - RISCV_X10 = 11, - RISCV_X11 = 12, - RISCV_X12 = 13, - RISCV_X13 = 14, - RISCV_X14 = 15, - RISCV_X15 = 16, - RISCV_X16 = 17, - RISCV_X17 = 18, - RISCV_X18 = 19, - RISCV_X19 = 20, - RISCV_X20 = 21, - RISCV_X21 = 22, - RISCV_X22 = 23, - RISCV_X23 = 24, - RISCV_X24 = 25, - RISCV_X25 = 26, - RISCV_X26 = 27, - RISCV_X27 = 28, - RISCV_X28 = 29, - RISCV_X29 = 30, - RISCV_X30 = 31, - RISCV_X31 = 32, - RISCV_F0_32 = 33, - RISCV_F0_64 = 34, - RISCV_F1_32 = 35, - RISCV_F1_64 = 36, - RISCV_F2_32 = 37, - RISCV_F2_64 = 38, - RISCV_F3_32 = 39, - RISCV_F3_64 = 40, - RISCV_F4_32 = 41, - RISCV_F4_64 = 42, - RISCV_F5_32 = 43, - RISCV_F5_64 = 44, - RISCV_F6_32 = 45, - RISCV_F6_64 = 46, - RISCV_F7_32 = 47, - RISCV_F7_64 = 48, - RISCV_F8_32 = 49, - RISCV_F8_64 = 50, - RISCV_F9_32 = 51, - RISCV_F9_64 = 52, - RISCV_F10_32 = 53, - RISCV_F10_64 = 54, - RISCV_F11_32 = 55, - RISCV_F11_64 = 56, - RISCV_F12_32 = 57, - RISCV_F12_64 = 58, - RISCV_F13_32 = 59, - RISCV_F13_64 = 60, - RISCV_F14_32 = 61, - RISCV_F14_64 = 62, - RISCV_F15_32 = 63, - RISCV_F15_64 = 64, - RISCV_F16_32 = 65, - RISCV_F16_64 = 66, - RISCV_F17_32 = 67, - RISCV_F17_64 = 68, - RISCV_F18_32 = 69, - RISCV_F18_64 = 70, - RISCV_F19_32 = 71, - RISCV_F19_64 = 72, - RISCV_F20_32 = 73, - RISCV_F20_64 = 74, - RISCV_F21_32 = 75, - RISCV_F21_64 = 76, - RISCV_F22_32 = 77, - RISCV_F22_64 = 78, - RISCV_F23_32 = 79, - RISCV_F23_64 = 80, - RISCV_F24_32 = 81, - RISCV_F24_64 = 82, - RISCV_F25_32 = 83, - RISCV_F25_64 = 84, - RISCV_F26_32 = 85, - RISCV_F26_64 = 86, - RISCV_F27_32 = 87, - RISCV_F27_64 = 88, - RISCV_F28_32 = 89, - RISCV_F28_64 = 90, - RISCV_F29_32 = 91, - RISCV_F29_64 = 92, - RISCV_F30_32 = 93, - RISCV_F30_64 = 94, - RISCV_F31_32 = 95, - RISCV_F31_64 = 96, - RISCV_NUM_TARGET_REGS // 97 -}; - -// Register classes -enum { - RISCV_FPR32RegClassID = 0, - RISCV_GPRRegClassID = 1, - RISCV_GPRNoX0RegClassID = 2, - RISCV_GPRNoX0X2RegClassID = 3, - RISCV_GPRTCRegClassID = 4, - RISCV_FPR32CRegClassID = 5, - RISCV_GPRCRegClassID = 6, - RISCV_GPRC_and_GPRTCRegClassID = 7, - RISCV_SPRegClassID = 8, - RISCV_FPR64RegClassID = 9, - RISCV_FPR64CRegClassID = 10, -}; - -// Register alternate name indices - -enum { - RISCV_ABIRegAltName, // 0 - RISCV_NoRegAltName, // 1 - RISCV_NUM_TARGET_REG_ALT_NAMES = 2 -}; - -// Subregister indices - -enum { - RISCV_NoSubRegister, - RISCV_sub_32, // 1 - RISCV_NUM_TARGET_SUBREGS -}; -#endif // GET_REGINFO_ENUM - -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* MC Register Information *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - - -#ifdef GET_REGINFO_MC_DESC -#undef GET_REGINFO_MC_DESC - -static const MCPhysReg RISCVRegDiffLists[] = { - /* 0 */ 1, 0, - /* 2 */ 32, 0, - /* 4 */ 33, 0, - /* 6 */ 34, 0, - /* 8 */ 35, 0, - /* 10 */ 36, 0, - /* 12 */ 37, 0, - /* 14 */ 38, 0, - /* 16 */ 39, 0, - /* 18 */ 40, 0, - /* 20 */ 41, 0, - /* 22 */ 42, 0, - /* 24 */ 43, 0, - /* 26 */ 44, 0, - /* 28 */ 45, 0, - /* 30 */ 46, 0, - /* 32 */ 47, 0, - /* 34 */ 48, 0, - /* 36 */ 49, 0, - /* 38 */ 50, 0, - /* 40 */ 51, 0, - /* 42 */ 52, 0, - /* 44 */ 53, 0, - /* 46 */ 54, 0, - /* 48 */ 55, 0, - /* 50 */ 56, 0, - /* 52 */ 57, 0, - /* 54 */ 58, 0, - /* 56 */ 59, 0, - /* 58 */ 60, 0, - /* 60 */ 61, 0, - /* 62 */ 62, 0, - /* 64 */ 63, 0, - /* 66 */ -1, 0, -}; - -static const uint16_t RISCVSubRegIdxLists[] = { - /* 0 */ 1, 0, -}; - -static const MCRegisterDesc RISCVRegDesc[] = { // Descriptors - { 3, 0, 0, 0, 0, 0 }, - { 12, 1, 1, 1, 1057, 0 }, - { 27, 1, 1, 1, 1057, 0 }, - { 252, 1, 1, 1, 1057, 0 }, - { 263, 1, 1, 1, 1057, 0 }, - { 488, 1, 1, 1, 1057, 0 }, - { 499, 1, 1, 1, 1057, 0 }, - { 510, 1, 1, 1, 1057, 0 }, - { 521, 1, 1, 1, 1057, 0 }, - { 532, 1, 1, 1, 1057, 0 }, - { 543, 1, 1, 1, 1057, 0 }, - { 0, 1, 1, 1, 1057, 0 }, - { 15, 1, 1, 1, 1057, 0 }, - { 30, 1, 1, 1, 1057, 0 }, - { 255, 1, 1, 1, 1057, 0 }, - { 266, 1, 1, 1, 1057, 0 }, - { 491, 1, 1, 1, 1057, 0 }, - { 502, 1, 1, 1, 1057, 0 }, - { 513, 1, 1, 1, 1057, 0 }, - { 524, 1, 1, 1, 1057, 0 }, - { 535, 1, 1, 1, 1057, 0 }, - { 4, 1, 1, 1, 1057, 0 }, - { 19, 1, 1, 1, 1057, 0 }, - { 34, 1, 1, 1, 1057, 0 }, - { 259, 1, 1, 1, 1057, 0 }, - { 270, 1, 1, 1, 1057, 0 }, - { 495, 1, 1, 1, 1057, 0 }, - { 506, 1, 1, 1, 1057, 0 }, - { 517, 1, 1, 1, 1057, 0 }, - { 528, 1, 1, 1, 1057, 0 }, - { 539, 1, 1, 1, 1057, 0 }, - { 8, 1, 1, 1, 1057, 0 }, - { 23, 1, 1, 1, 1057, 0 }, - { 59, 1, 0, 1, 32, 0 }, - { 295, 66, 1, 0, 32, 2 }, - { 86, 1, 0, 1, 64, 0 }, - { 322, 66, 1, 0, 64, 2 }, - { 106, 1, 0, 1, 96, 0 }, - { 342, 66, 1, 0, 96, 2 }, - { 126, 1, 0, 1, 128, 0 }, - { 362, 66, 1, 0, 128, 2 }, - { 146, 1, 0, 1, 160, 0 }, - { 382, 66, 1, 0, 160, 2 }, - { 166, 1, 0, 1, 192, 0 }, - { 402, 66, 1, 0, 192, 2 }, - { 186, 1, 0, 1, 224, 0 }, - { 422, 66, 1, 0, 224, 2 }, - { 206, 1, 0, 1, 256, 0 }, - { 442, 66, 1, 0, 256, 2 }, - { 226, 1, 0, 1, 288, 0 }, - { 462, 66, 1, 0, 288, 2 }, - { 246, 1, 0, 1, 320, 0 }, - { 482, 66, 1, 0, 320, 2 }, - { 38, 1, 0, 1, 352, 0 }, - { 274, 66, 1, 0, 352, 2 }, - { 65, 1, 0, 1, 384, 0 }, - { 301, 66, 1, 0, 384, 2 }, - { 92, 1, 0, 1, 416, 0 }, - { 328, 66, 1, 0, 416, 2 }, - { 112, 1, 0, 1, 448, 0 }, - { 348, 66, 1, 0, 448, 2 }, - { 132, 1, 0, 1, 480, 0 }, - { 368, 66, 1, 0, 480, 2 }, - { 152, 1, 0, 1, 512, 0 }, - { 388, 66, 1, 0, 512, 2 }, - { 172, 1, 0, 1, 544, 0 }, - { 408, 66, 1, 0, 544, 2 }, - { 192, 1, 0, 1, 576, 0 }, - { 428, 66, 1, 0, 576, 2 }, - { 212, 1, 0, 1, 608, 0 }, - { 448, 66, 1, 0, 608, 2 }, - { 232, 1, 0, 1, 640, 0 }, - { 468, 66, 1, 0, 640, 2 }, - { 45, 1, 0, 1, 672, 0 }, - { 281, 66, 1, 0, 672, 2 }, - { 72, 1, 0, 1, 704, 0 }, - { 308, 66, 1, 0, 704, 2 }, - { 99, 1, 0, 1, 736, 0 }, - { 335, 66, 1, 0, 736, 2 }, - { 119, 1, 0, 1, 768, 0 }, - { 355, 66, 1, 0, 768, 2 }, - { 139, 1, 0, 1, 800, 0 }, - { 375, 66, 1, 0, 800, 2 }, - { 159, 1, 0, 1, 832, 0 }, - { 395, 66, 1, 0, 832, 2 }, - { 179, 1, 0, 1, 864, 0 }, - { 415, 66, 1, 0, 864, 2 }, - { 199, 1, 0, 1, 896, 0 }, - { 435, 66, 1, 0, 896, 2 }, - { 219, 1, 0, 1, 928, 0 }, - { 455, 66, 1, 0, 928, 2 }, - { 239, 1, 0, 1, 960, 0 }, - { 475, 66, 1, 0, 960, 2 }, - { 52, 1, 0, 1, 992, 0 }, - { 288, 66, 1, 0, 992, 2 }, - { 79, 1, 0, 1, 1024, 0 }, - { 315, 66, 1, 0, 1024, 2 }, -}; - - // FPR32 Register Class... - static const MCPhysReg FPR32[] = { - RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F16_32, RISCV_F17_32, RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32, RISCV_F8_32, RISCV_F9_32, RISCV_F18_32, RISCV_F19_32, RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32, - }; - - // FPR32 Bit set. - static const uint8_t FPR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - }; - - // GPR Register Class... - static const MCPhysReg GPR[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, - }; - - // GPR Bit set. - static const uint8_t GPRBits[] = { - 0xfe, 0xff, 0xff, 0xff, 0x01, - }; - - // GPRNoX0 Register Class... - static const MCPhysReg GPRNoX0[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4, - }; - - // GPRNoX0 Bit set. - static const uint8_t GPRNoX0Bits[] = { - 0xfc, 0xff, 0xff, 0xff, 0x01, - }; - - // GPRNoX0X2 Register Class... - static const MCPhysReg GPRNoX0X2[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X3, RISCV_X4, - }; - - // GPRNoX0X2 Bit set. - static const uint8_t GPRNoX0X2Bits[] = { - 0xf4, 0xff, 0xff, 0xff, 0x01, - }; - - // GPRTC Register Class... - static const MCPhysReg GPRTC[] = { - RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, - }; - - // GPRTC Bit set. - static const uint8_t GPRTCBits[] = { - 0xc0, 0xf9, 0x07, 0xe0, 0x01, - }; - - // FPR32C Register Class... - static const MCPhysReg FPR32C[] = { - RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F8_32, RISCV_F9_32, - }; - - // FPR32C Bit set. - static const uint8_t FPR32CBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, - }; - - // GPRC Register Class... - static const MCPhysReg GPRC[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X8, RISCV_X9, - }; - - // GPRC Bit set. - static const uint8_t GPRCBits[] = { - 0x00, 0xfe, 0x01, - }; - - // GPRC_and_GPRTC Register Class... - static const MCPhysReg GPRC_and_GPRTC[] = { - RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, - }; - - // GPRC_and_GPRTC Bit set. - static const uint8_t GPRC_and_GPRTCBits[] = { - 0x00, 0xf8, 0x01, - }; - - // SP Register Class... - static const MCPhysReg SP[] = { - RISCV_X2, - }; - - // SP Bit set. - static const uint8_t SPBits[] = { - 0x08, - }; - - // FPR64 Register Class... - static const MCPhysReg FPR64[] = { - RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F16_64, RISCV_F17_64, RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64, RISCV_F8_64, RISCV_F9_64, RISCV_F18_64, RISCV_F19_64, RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64, - }; - - // FPR64 Bit set. - static const uint8_t FPR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x01, - }; - - // FPR64C Register Class... - static const MCPhysReg FPR64C[] = { - RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F8_64, RISCV_F9_64, - }; - - // FPR64C Bit set. - static const uint8_t FPR64CBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, - }; - -static const MCRegisterClass RISCVMCRegisterClasses[] = { - { FPR32, FPR32Bits, sizeof(FPR32Bits) }, - { GPR, GPRBits, sizeof(GPRBits) }, - { GPRNoX0, GPRNoX0Bits, sizeof(GPRNoX0Bits) }, - { GPRNoX0X2, GPRNoX0X2Bits, sizeof(GPRNoX0X2Bits) }, - { GPRTC, GPRTCBits, sizeof(GPRTCBits) }, - { FPR32C, FPR32CBits, sizeof(FPR32CBits) }, - { GPRC, GPRCBits, sizeof(GPRCBits) }, - { GPRC_and_GPRTC, GPRC_and_GPRTCBits, sizeof(GPRC_and_GPRTCBits) }, - { SP, SPBits, sizeof(SPBits) }, - { FPR64, FPR64Bits, sizeof(FPR64Bits) }, - { FPR64C, FPR64CBits, sizeof(FPR64CBits) }, -}; - -#endif // GET_REGINFO_MC_DESC \ No newline at end of file diff --git a/arch/RISCV/RISCVGenSubtargetInfo.inc b/arch/RISCV/RISCVGenSubtargetInfo.inc deleted file mode 100644 index c857ce6c1c..0000000000 --- a/arch/RISCV/RISCVGenSubtargetInfo.inc +++ /dev/null @@ -1,33 +0,0 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* Subtarget Enumeration Source Fragment *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - -#ifdef GET_SUBTARGETINFO_ENUM -#undef GET_SUBTARGETINFO_ENUM - -/* - Make sure: - CS_MODE_RISCV64 = 0b11111 - CS_MODE_RISCV32 = 0b11110 -*/ - -enum { - RISCV_Feature64Bit = 1ULL << 0, - RISCV_FeatureStdExtA = 1ULL << 1, - RISCV_FeatureStdExtC = 1ULL << 2, - RISCV_FeatureStdExtD = 1ULL << 3, - RISCV_FeatureStdExtF = 1ULL << 4, - RISCV_FeatureStdExtM = 1ULL << 5, - RISCV_FeatureRelax = 1ULL << 6, -}; - -#endif // GET_SUBTARGETINFO_ENUM - diff --git a/arch/RISCV/RISCVHelpers.c b/arch/RISCV/RISCVHelpers.c new file mode 100644 index 0000000000..9d7e6b007e --- /dev/null +++ b/arch/RISCV/RISCVHelpers.c @@ -0,0 +1,56 @@ +#include "RISCVHelpers.h" + +/* +The size calculation algorithm according to the RISCV spec: + 1- Check the first (least-significant) 2 bits... + 1.1- If they're not 11, then the instruction is a 16-bits instruction. + + 2- Otherwise, if they're 11, Check the next 3 bits (3rd-5th)... + 2.1- If they're not 111, then the instruction is a 32-bits instruction. + + 3- Otherwise, if they're 111, check the next (6th) bit... + 3.1- If it's not 1, then the instruction is a 48-bits instruction. + + 4- Otherwise, if it's 1, check the next (7th) bit... + 4.1- If it's not 1, then the instruction is 1 64-bits instruction. + + 5- Otherwise, the instruction size can be determined from other bits further from the first byte. + + (The spec actually specifies valid sizes up to 192-bits instructions, even reserving a pattern for + instructions beyond 192 bits. In practice, even 48-bits or 64-bits instructions are extremly rare, + and it's not worth complicating the code with a bitvector type to represent bigger instructions.) +*/ +int riscv_get_instruction_size(uint8_t first_byte) { + if ((first_byte & 0x3) != 0x3) { + return 2; + } else if (((first_byte >> 2) & 0x7) != 0x7) { + return 4; + } else if (((first_byte >> 5) & 0x1) == 0x0) { + return 6; + } else if (((first_byte >> 6) & 0x1) == 0x0) { + return 8; + } else { + return 0; + } +} + +// for now, just trivially enable everything +// TODO: make this configurable using whatever options mechanism capstone offers +void riscv_init_riscv_context(RVContext *ctx) { + ctx->xlen = 64; + ctx->xlen_bytes = 8; + ctx->flen = 64; + + ctx->misa = 0xFFFFFFFF; + ctx->mstatus = ~0ULL; + ctx->extensionsSupported = ~0ULL; + + ctx->vtype = (1ULL << 63); + ctx->vl = 0; + ctx->vstart = 0; + ctx->vlen = 8; + + // constants + ctx->zreg = 0x00; + ctx->sp = 0x02; +} \ No newline at end of file diff --git a/arch/RISCV/RISCVHelpers.h b/arch/RISCV/RISCVHelpers.h new file mode 100644 index 0000000000..625d136c07 --- /dev/null +++ b/arch/RISCV/RISCVHelpers.h @@ -0,0 +1,6 @@ +#include "../include/capstone/capstone.h" +#include "RISCVRVContextHelpers.h" + +int riscv_get_instruction_size(uint8_t first_byte); + +void riscv_init_riscv_context(RVContext *ctx); \ No newline at end of file diff --git a/arch/RISCV/RISCVInsn.gen.inc b/arch/RISCV/RISCVInsn.gen.inc new file mode 100644 index 0000000000..ec05335a16 --- /dev/null +++ b/arch/RISCV/RISCVInsn.gen.inc @@ -0,0 +1,1052 @@ +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ + +#ifndef __RISCVINSN_GEN_INC__ +#define __RISCVINSN_GEN_INC__ +#include +#include +#include + +enum riscv_insn { + //--------------------- RISCV_REV8--------------------- + RISCV_INSN_REV8, + //--------------------- RISCV_WXTYPE--------------------- + RISCV_INSN_WX_VSUBU, + RISCV_INSN_WX_VSUB, + RISCV_INSN_WX_VADDU, + RISCV_INSN_WX_VADD, + //--------------------- RISCV_C_SRLI_HINT--------------------- + RISCV_INSN_C_SRLI_HINT, + //--------------------- RISCV_AES64DS--------------------- + RISCV_INSN_AES64DS, + //--------------------- RISCV_VMSBF_M--------------------- + RISCV_INSN_VMSBF_M, + //--------------------- RISCV_RTYPE--------------------- + RISCV_INSN_XOR, + RISCV_INSN_SUB, + RISCV_INSN_SRL, + RISCV_INSN_SRA, + RISCV_INSN_SLTU, + RISCV_INSN_SLT, + RISCV_INSN_SLL, + RISCV_INSN_OR, + RISCV_INSN_AND, + RISCV_INSN_ADD, + //--------------------- RISCV_VFMERGE--------------------- + RISCV_INSN_VFMERGE, + //--------------------- RISCV_RIVVTYPE--------------------- + RISCV_INSN_IVV_VWREDSUMU, + RISCV_INSN_IVV_VWREDSUM, + //--------------------- RISCV_F_BIN_F_TYPE_H--------------------- + RISCV_INSN_FSGNJ_H, + RISCV_INSN_FSGNJX_H, + RISCV_INSN_FSGNJN_H, + RISCV_INSN_FMIN_H, + RISCV_INSN_FMAX_H, + //--------------------- RISCV_C_ZEXT_W--------------------- + RISCV_INSN_C_ZEXT_W, + //--------------------- RISCV_SFENCE_INVAL_IR--------------------- + RISCV_INSN_SFENCE_INVAL_IR, + //--------------------- RISCV_XPERM4--------------------- + RISCV_INSN_XPERM4, + //--------------------- RISCV_F_UN_TYPE_F_S--------------------- + RISCV_INSN_FMV_W_X, + //--------------------- RISCV_C_AND--------------------- + RISCV_INSN_C_AND, + //--------------------- RISCV_AES32DSI--------------------- + RISCV_INSN_AES32DSI, + //--------------------- RISCV_RORI--------------------- + RISCV_INSN_RORI, + //--------------------- RISCV_JALR--------------------- + RISCV_INSN_JALR, + //--------------------- RISCV_VMSIF_M--------------------- + RISCV_INSN_VMSIF_M, + //--------------------- RISCV_CSRImm--------------------- + RISCV_INSN_CSRRW, + RISCV_INSN_CSRRS, + RISCV_INSN_CSRRC, + //--------------------- RISCV_VLSSEGTYPE--------------------- + RISCV_INSN_VLSSEGTYPE, + //--------------------- RISCV_SHA512SIG1H--------------------- + RISCV_INSN_SHA512SIG1H, + //--------------------- RISCV_FLTQ_S--------------------- + RISCV_INSN_FLTQ_S, + //--------------------- RISCV_VXSG--------------------- + RISCV_INSN_VX_VSLIDEUP, + RISCV_INSN_VX_VSLIDEDOWN, + RISCV_INSN_VX_VRGATHER, + //--------------------- RISCV_VXCMPTYPE--------------------- + RISCV_INSN_VXCMP_VMSNE, + RISCV_INSN_VXCMP_VMSLTU, + RISCV_INSN_VXCMP_VMSLT, + RISCV_INSN_VXCMP_VMSLEU, + RISCV_INSN_VXCMP_VMSLE, + RISCV_INSN_VXCMP_VMSGTU, + RISCV_INSN_VXCMP_VMSGT, + RISCV_INSN_VXCMP_VMSEQ, + //--------------------- RISCV_C_LHU--------------------- + RISCV_INSN_C_LHU, + //--------------------- RISCV_F_UN_RM_FX_TYPE_S--------------------- + RISCV_INSN_FCVT_W_S, + RISCV_INSN_FCVT_WU_S, + RISCV_INSN_FCVT_L_S, + RISCV_INSN_FCVT_LU_S, + //--------------------- RISCV_JAL--------------------- + RISCV_INSN_JAL, + //--------------------- RISCV_ECALL--------------------- + RISCV_INSN_ECALL, + //--------------------- RISCV_F_UN_X_TYPE_D--------------------- + RISCV_INSN_FMV_X_D, + RISCV_INSN_FCLASS_D, + //--------------------- RISCV_C_FSWSP--------------------- + RISCV_INSN_C_FSWSP, + //--------------------- RISCV_VMVXS--------------------- + RISCV_INSN_VMVXS, + //--------------------- RISCV_ZVKSHA2TYPE--------------------- + RISCV_INSN_ZVK_VSHA2CL, + RISCV_INSN_ZVK_VSHA2CH, + //--------------------- RISCV_C_FLD--------------------- + RISCV_INSN_C_FLD, + //--------------------- RISCV_SHIFTIWOP--------------------- + RISCV_INSN_SRLIW, + RISCV_INSN_SRAIW, + RISCV_INSN_SLLIW, + //--------------------- RISCV_UNZIP--------------------- + RISCV_INSN_UNZIP, + //--------------------- RISCV_ZICBOM--------------------- + RISCV_INSN_CBO_INVAL, + RISCV_INSN_CBO_FLUSH, + RISCV_INSN_CBO_CLEAN, + //--------------------- RISCV_SHA512SIG1--------------------- + RISCV_INSN_SHA512SIG1, + //--------------------- RISCV_NITYPE--------------------- + RISCV_INSN_NI_VNCLIPU, + RISCV_INSN_NI_VNCLIP, + //--------------------- RISCV_WFI--------------------- + RISCV_INSN_WFI, + //--------------------- RISCV_VVMTYPE--------------------- + RISCV_INSN_VVM_VMSBC, + RISCV_INSN_VVM_VMADC, + //--------------------- RISCV_MVXMATYPE--------------------- + RISCV_INSN_MVX_VNMSUB, + RISCV_INSN_MVX_VNMSAC, + RISCV_INSN_MVX_VMADD, + RISCV_INSN_MVX_VMACC, + //--------------------- RISCV_FLI_D--------------------- + RISCV_INSN_FLI_D, + //--------------------- RISCV_C_ADDI_HINT--------------------- + RISCV_INSN_C_ADDI_HINT, + //--------------------- RISCV_MASKTYPEX--------------------- + RISCV_INSN_MASKTYPEX, + //--------------------- RISCV_FROUNDNX_D--------------------- + RISCV_INSN_FROUNDNX_D, + //--------------------- RISCV_FROUND_D--------------------- + RISCV_INSN_FROUND_D, + //--------------------- RISCV_VSETIVLI--------------------- + RISCV_INSN_VSETIVLI, + //--------------------- RISCV_FMAXM_D--------------------- + RISCV_INSN_FMAXM_D, + //--------------------- RISCV_C_SD--------------------- + RISCV_INSN_C_SD, + //--------------------- RISCV_ZBKB_PACKW--------------------- + RISCV_INSN_ZBKB_PACKW, + //--------------------- RISCV_FVVMTYPE--------------------- + RISCV_INSN_FVVM_VMFNE, + RISCV_INSN_FVVM_VMFLT, + RISCV_INSN_FVVM_VMFLE, + RISCV_INSN_FVVM_VMFEQ, + //--------------------- RISCV_VMVSX--------------------- + RISCV_INSN_VMVSX, + //--------------------- RISCV_ORCB--------------------- + RISCV_INSN_ORCB, + //--------------------- RISCV_C_MUL--------------------- + RISCV_INSN_C_MUL, + //--------------------- RISCV_SM3P1--------------------- + RISCV_INSN_SM3P1, + //--------------------- RISCV_CLMUL--------------------- + RISCV_INSN_CLMUL, + //--------------------- RISCV_FLEQ_S--------------------- + RISCV_INSN_FLEQ_S, + //--------------------- RISCV_F_UN_RM_FF_TYPE_S--------------------- + RISCV_INSN_FSQRT_S, + //--------------------- RISCV_WVXTYPE--------------------- + RISCV_INSN_WVX_VWMULU, + RISCV_INSN_WVX_VWMULSU, + RISCV_INSN_WVX_VWMUL, + RISCV_INSN_WVX_VSUBU, + RISCV_INSN_WVX_VSUB, + RISCV_INSN_WVX_VADDU, + RISCV_INSN_WVX_VADD, + //--------------------- RISCV_FMAXM_S--------------------- + RISCV_INSN_FMAXM_S, + //--------------------- RISCV_C_ILLEGAL--------------------- + RISCV_INSN_C_ILLEGAL, + //--------------------- RISCV_NXSTYPE--------------------- + RISCV_INSN_NXS_VNSRL, + RISCV_INSN_NXS_VNSRA, + //--------------------- RISCV_VSOXSEGTYPE--------------------- + RISCV_INSN_VSOXSEGTYPE, + //--------------------- RISCV_C_NOP--------------------- + RISCV_INSN_C_NOP, + //--------------------- RISCV_VXMCTYPE--------------------- + RISCV_INSN_VXMC_VMSBC, + RISCV_INSN_VXMC_VMADC, + //--------------------- RISCV_MMTYPE--------------------- + RISCV_INSN_MM_VMXOR, + RISCV_INSN_MM_VMXNOR, + RISCV_INSN_MM_VMORN, + RISCV_INSN_MM_VMOR, + RISCV_INSN_MM_VMNOR, + RISCV_INSN_MM_VMNAND, + RISCV_INSN_MM_VMANDN, + RISCV_INSN_MM_VMAND, + //--------------------- RISCV_NVTYPE--------------------- + RISCV_INSN_NV_VNCLIPU, + RISCV_INSN_NV_VNCLIP, + //--------------------- RISCV_AES64KS2--------------------- + RISCV_INSN_AES64KS2, + //--------------------- RISCV_F_BIN_F_TYPE_D--------------------- + RISCV_INSN_FSGNJ_D, + RISCV_INSN_FSGNJX_D, + RISCV_INSN_FSGNJN_D, + RISCV_INSN_FMIN_D, + RISCV_INSN_FMAX_D, + //--------------------- RISCV_AES32ESMI--------------------- + RISCV_INSN_AES32ESMI, + //--------------------- RISCV_F_MADD_TYPE_H--------------------- + RISCV_INSN_FNMSUB_H, + RISCV_INSN_FNMADD_H, + RISCV_INSN_FMSUB_H, + RISCV_INSN_FMADD_H, + //--------------------- RISCV_FROUNDNX_H--------------------- + RISCV_INSN_FROUNDNX_H, + //--------------------- RISCV_MOVETYPEI--------------------- + RISCV_INSN_MOVETYPEI, + //--------------------- RISCV_FLTQ_H--------------------- + RISCV_INSN_FLTQ_H, + //--------------------- RISCV_C_LW--------------------- + RISCV_INSN_C_LW, + //--------------------- RISCV_C_LWSP--------------------- + RISCV_INSN_C_LWSP, + //--------------------- RISCV_C_ADDI16SP--------------------- + RISCV_INSN_C_ADDI16SP, + //--------------------- RISCV_CSRReg--------------------- + + //--------------------- RISCV_SHA512SIG0L--------------------- + RISCV_INSN_SHA512SIG0L, + //--------------------- RISCV_SM3P0--------------------- + RISCV_INSN_SM3P0, + //--------------------- RISCV_SM4ED--------------------- + RISCV_INSN_SM4ED, + //--------------------- RISCV_FMINM_D--------------------- + RISCV_INSN_FMINM_D, + //--------------------- RISCV_AES64IM--------------------- + RISCV_INSN_AES64IM, + //--------------------- RISCV_VLRETYPE--------------------- + RISCV_INSN_VLRETYPE, + //--------------------- RISCV_VFMVFS--------------------- + RISCV_INSN_VFMVFS, + //--------------------- RISCV_CTZ--------------------- + RISCV_INSN_CTZ, + //--------------------- RISCV_FMVH_X_D--------------------- + RISCV_INSN_FMVH_X_D, + //--------------------- RISCV_SLLIUW--------------------- + RISCV_INSN_SLLIUW, + //--------------------- RISCV_ZCMOP--------------------- + RISCV_INSN_ZCMOP, + //--------------------- RISCV_FMINM_S--------------------- + RISCV_INSN_FMINM_S, + //--------------------- RISCV_ZBA_RTYPEUW--------------------- + RISCV_INSN_SH3ADDUW, + RISCV_INSN_SH2ADDUW, + RISCV_INSN_SH1ADDUW, + RISCV_INSN_ADDUW, + //--------------------- RISCV_F_BIN_RM_TYPE_D--------------------- + RISCV_INSN_FSUB_D, + RISCV_INSN_FMUL_D, + RISCV_INSN_FDIV_D, + RISCV_INSN_FADD_D, + //--------------------- RISCV_C_ADD_HINT--------------------- + RISCV_INSN_C_ADD_HINT, + //--------------------- RISCV_F_MADD_TYPE_S--------------------- + RISCV_INSN_FNMSUB_S, + RISCV_INSN_FNMADD_S, + RISCV_INSN_FMSUB_S, + RISCV_INSN_FMADD_S, + //--------------------- RISCV_ZIP--------------------- + RISCV_INSN_ZIP, + //--------------------- RISCV_SHA512SUM1--------------------- + RISCV_INSN_SHA512SUM1, + //--------------------- RISCV_VROR_VI--------------------- + RISCV_INSN_VROR_VI, + //--------------------- RISCV_C_LDSP--------------------- + RISCV_INSN_C_LDSP, + //--------------------- RISCV_VBREV_V--------------------- + RISCV_INSN_VBREV_V, + //--------------------- RISCV_CPOP--------------------- + RISCV_INSN_CPOP, + //--------------------- RISCV_FWFTYPE--------------------- + RISCV_INSN_FWF_VSUB, + RISCV_INSN_FWF_VADD, + //--------------------- RISCV_FWVTYPE--------------------- + RISCV_INSN_FWV_VSUB, + RISCV_INSN_FWV_VADD, + //--------------------- RISCV_ZBB_RTYPE--------------------- + RISCV_INSN_XNOR, + RISCV_INSN_ROR, + RISCV_INSN_ROL, + RISCV_INSN_ORN, + RISCV_INSN_MINU, + RISCV_INSN_MIN, + RISCV_INSN_MAXU, + RISCV_INSN_MAX, + RISCV_INSN_ANDN, + //--------------------- RISCV_SM4KS--------------------- + RISCV_INSN_SM4KS, + //--------------------- RISCV_RORIW--------------------- + RISCV_INSN_RORIW, + //--------------------- RISCV_F_UN_TYPE_X_S--------------------- + RISCV_INSN_FMV_X_W, + RISCV_INSN_FCLASS_S, + //--------------------- RISCV_NXTYPE--------------------- + RISCV_INSN_NX_VNCLIPU, + RISCV_INSN_NX_VNCLIP, + //--------------------- RISCV_C_ADDIW--------------------- + RISCV_INSN_C_ADDIW, + //--------------------- RISCV_C_LD--------------------- + RISCV_INSN_C_LD, + //--------------------- RISCV_CTZW--------------------- + RISCV_INSN_CTZW, + //--------------------- RISCV_XPERM8--------------------- + RISCV_INSN_XPERM8, + //--------------------- RISCV_ITYPE--------------------- + RISCV_INSN_XORI, + RISCV_INSN_SLTIU, + RISCV_INSN_SLTI, + RISCV_INSN_ORI, + RISCV_INSN_ANDI, + RISCV_INSN_ADDI, + //--------------------- RISCV_VCLMUL_VV--------------------- + RISCV_INSN_VCLMUL_VV, + //--------------------- RISCV_F_UN_F_TYPE_H--------------------- + RISCV_INSN_FMV_H_X, + //--------------------- RISCV_VCLZ_V--------------------- + RISCV_INSN_VCLZ_V, + //--------------------- RISCV_VID_V--------------------- + RISCV_INSN_VID_V, + //--------------------- RISCV_FENCE--------------------- + RISCV_INSN_FENCE, + //--------------------- RISCV_C_FLWSP--------------------- + RISCV_INSN_C_FLWSP, + //--------------------- RISCV_STORE--------------------- + RISCV_INSN_STORE, + //--------------------- RISCV_VBREV8_V--------------------- + RISCV_INSN_VBREV8_V, + //--------------------- RISCV_VSSEGTYPE--------------------- + RISCV_INSN_VSSEGTYPE, + //--------------------- RISCV_ZICOND_RTYPE--------------------- + RISCV_INSN_CZERO_NEZ, + RISCV_INSN_CZERO_EQZ, + //--------------------- RISCV_VCLMULH_VX--------------------- + RISCV_INSN_VCLMULH_VX, + //--------------------- RISCV_C_FSDSP--------------------- + RISCV_INSN_C_FSDSP, + //--------------------- RISCV_SRET--------------------- + RISCV_INSN_SRET, + //--------------------- RISCV_STORE_FP--------------------- + RISCV_INSN_STORE_FP, + //--------------------- RISCV_C_JALR--------------------- + RISCV_INSN_C_JALR, + //--------------------- RISCV_FENCE_TSO--------------------- + RISCV_INSN_FENCE_TSO, + //--------------------- RISCV_SHA512SIG0--------------------- + RISCV_INSN_SHA512SIG0, + //--------------------- RISCV_FLI_S--------------------- + RISCV_INSN_FLI_S, + //--------------------- RISCV_C_SB--------------------- + RISCV_INSN_C_SB, + //--------------------- RISCV_ZBB_RTYPEW--------------------- + RISCV_INSN_RORW, + RISCV_INSN_ROLW, + //--------------------- RISCV_C_FLDSP--------------------- + RISCV_INSN_C_FLDSP, + //--------------------- RISCV_C_MV_HINT--------------------- + RISCV_INSN_C_MV_HINT, + //--------------------- RISCV_VWSLL_VI--------------------- + RISCV_INSN_VWSLL_VI, + //--------------------- RISCV_FCVTMOD_W_D--------------------- + RISCV_INSN_FCVTMOD_W_D, + //--------------------- RISCV_RFVVTYPE--------------------- + RISCV_INSN_FVV_VFWREDUSUM, + RISCV_INSN_FVV_VFWREDOSUM, + RISCV_INSN_FVV_VFREDUSUM, + RISCV_INSN_FVV_VFREDOSUM, + RISCV_INSN_FVV_VFREDMIN, + RISCV_INSN_FVV_VFREDMAX, + //--------------------- RISCV_SHA512SIG0H--------------------- + RISCV_INSN_SHA512SIG0H, + //--------------------- RISCV_AMO--------------------- + RISCV_INSN_AMOXOR, + RISCV_INSN_AMOSWAP, + RISCV_INSN_AMOOR, + RISCV_INSN_AMOMINU, + RISCV_INSN_AMOMIN, + RISCV_INSN_AMOMAXU, + RISCV_INSN_AMOMAX, + RISCV_INSN_AMOAND, + RISCV_INSN_AMOADD, + //--------------------- RISCV_LOAD_FP--------------------- + RISCV_INSN_LOAD_FP, + //--------------------- RISCV_VROL_VV--------------------- + RISCV_INSN_VROL_VV, + //--------------------- RISCV_VVMSTYPE--------------------- + RISCV_INSN_VVMS_VSBC, + RISCV_INSN_VVMS_VADC, + //--------------------- RISCV_FVVMATYPE--------------------- + RISCV_INSN_FVV_VNMSUB, + RISCV_INSN_FVV_VNMSAC, + RISCV_INSN_FVV_VNMADD, + RISCV_INSN_FVV_VNMACC, + RISCV_INSN_FVV_VMSUB, + RISCV_INSN_FVV_VMSAC, + RISCV_INSN_FVV_VMADD, + RISCV_INSN_FVV_VMACC, + //--------------------- RISCV_VEXT2TYPE--------------------- + RISCV_INSN_VEXT2_ZVF2, + RISCV_INSN_VEXT2_SVF2, + //--------------------- RISCV_EBREAK--------------------- + RISCV_INSN_EBREAK, + //--------------------- RISCV_C_LUI--------------------- + RISCV_INSN_C_LUI, + //--------------------- RISCV_F_MADD_TYPE_D--------------------- + RISCV_INSN_FNMSUB_D, + RISCV_INSN_FNMADD_D, + RISCV_INSN_FMSUB_D, + RISCV_INSN_FMADD_D, + //--------------------- RISCV_C_ZEXT_H--------------------- + RISCV_INSN_C_ZEXT_H, + //--------------------- RISCV_SHA512SIG1L--------------------- + RISCV_INSN_SHA512SIG1L, + //--------------------- RISCV_VLSEGTYPE--------------------- + RISCV_INSN_VLSEGTYPE, + //--------------------- RISCV_SHA256SIG0--------------------- + RISCV_INSN_SHA256SIG0, + //--------------------- RISCV_ZIMOP_MOP_RR--------------------- + RISCV_INSN_ZIMOP_MOP_RR, + //--------------------- RISCV_C_ADDI4SPN--------------------- + RISCV_INSN_C_ADDI4SPN, + //--------------------- RISCV_VVTYPE--------------------- + RISCV_INSN_VV_VXOR, + RISCV_INSN_VV_VSUB, + RISCV_INSN_VV_VSSUBU, + RISCV_INSN_VV_VSSUB, + RISCV_INSN_VV_VSSRL, + RISCV_INSN_VV_VSSRA, + RISCV_INSN_VV_VSRL, + RISCV_INSN_VV_VSRA, + RISCV_INSN_VV_VSMUL, + RISCV_INSN_VV_VSLL, + RISCV_INSN_VV_VSADDU, + RISCV_INSN_VV_VSADD, + RISCV_INSN_VV_VRGATHEREI16, + RISCV_INSN_VV_VRGATHER, + RISCV_INSN_VV_VOR, + RISCV_INSN_VV_VMINU, + RISCV_INSN_VV_VMIN, + RISCV_INSN_VV_VMAXU, + RISCV_INSN_VV_VMAX, + RISCV_INSN_VV_VAND, + RISCV_INSN_VV_VADD, + //--------------------- RISCV_VSHA2MS_VV--------------------- + RISCV_INSN_VSHA2MS_VV, + //--------------------- RISCV_FLEQ_H--------------------- + RISCV_INSN_FLEQ_H, + //--------------------- RISCV_VICMPTYPE--------------------- + RISCV_INSN_VICMP_VMSNE, + RISCV_INSN_VICMP_VMSLEU, + RISCV_INSN_VICMP_VMSLE, + RISCV_INSN_VICMP_VMSGTU, + RISCV_INSN_VICMP_VMSGT, + RISCV_INSN_VICMP_VMSEQ, + //--------------------- RISCV_C_FLW--------------------- + RISCV_INSN_C_FLW, + //--------------------- RISCV_C_SWSP--------------------- + RISCV_INSN_C_SWSP, + //--------------------- RISCV_FLTQ_D--------------------- + RISCV_INSN_FLTQ_D, + //--------------------- RISCV_AES64ES--------------------- + RISCV_INSN_AES64ES, + //--------------------- RISCV_C_SRAI_HINT--------------------- + RISCV_INSN_C_SRAI_HINT, + //--------------------- RISCV_DIV--------------------- + RISCV_INSN_DIV, + //--------------------- RISCV_C_LH--------------------- + RISCV_INSN_C_LH, + //--------------------- RISCV_C_NOP_HINT--------------------- + RISCV_INSN_C_NOP_HINT, + //--------------------- RISCV_VFIRST_M--------------------- + RISCV_INSN_VFIRST_M, + //--------------------- RISCV_MVVMATYPE--------------------- + RISCV_INSN_MVV_VNMSUB, + RISCV_INSN_MVV_VNMSAC, + RISCV_INSN_MVV_VMADD, + RISCV_INSN_MVV_VMACC, + //--------------------- RISCV_FENCEI_RESERVED--------------------- + RISCV_INSN_FENCEI_RESERVED, + //--------------------- RISCV_C_ADDI--------------------- + RISCV_INSN_C_ADDI, + //--------------------- RISCV_VLOXSEGTYPE--------------------- + RISCV_INSN_VLOXSEGTYPE, + //--------------------- RISCV_MUL--------------------- + RISCV_INSN_MUL, + //--------------------- RISCV_VMSOF_M--------------------- + RISCV_INSN_VMSOF_M, + //--------------------- RISCV_FLEQ_D--------------------- + RISCV_INSN_FLEQ_D, + //--------------------- RISCV_VSSSEGTYPE--------------------- + RISCV_INSN_VSSSEGTYPE, + //--------------------- RISCV_VXTYPE--------------------- + RISCV_INSN_VX_VXOR, + RISCV_INSN_VX_VSUB, + RISCV_INSN_VX_VSSUBU, + RISCV_INSN_VX_VSSUB, + RISCV_INSN_VX_VSSRL, + RISCV_INSN_VX_VSSRA, + RISCV_INSN_VX_VSRL, + RISCV_INSN_VX_VSRA, + RISCV_INSN_VX_VSMUL, + RISCV_INSN_VX_VSLL, + RISCV_INSN_VX_VSADDU, + RISCV_INSN_VX_VSADD, + RISCV_INSN_VX_VRSUB, + RISCV_INSN_VX_VOR, + RISCV_INSN_VX_VMINU, + RISCV_INSN_VX_VMIN, + RISCV_INSN_VX_VMAXU, + RISCV_INSN_VX_VMAX, + RISCV_INSN_VX_VAND, + RISCV_INSN_VX_VADD, + //--------------------- RISCV_BTYPE--------------------- + RISCV_INSN_BNE, + RISCV_INSN_BLTU, + RISCV_INSN_BLT, + RISCV_INSN_BGEU, + RISCV_INSN_BGE, + RISCV_INSN_BEQ, + //--------------------- RISCV_VROR_VX--------------------- + RISCV_INSN_VROR_VX, + //--------------------- RISCV_LOAD--------------------- + RISCV_INSN_LOAD, + //--------------------- RISCV_VIOTA_M--------------------- + RISCV_INSN_VIOTA_M, + //--------------------- RISCV_VROL_VX--------------------- + RISCV_INSN_VROL_VX, + //--------------------- RISCV_CLMULR--------------------- + RISCV_INSN_CLMULR, + //--------------------- RISCV_VROR_VV--------------------- + RISCV_INSN_VROR_VV, + //--------------------- RISCV_VXMSTYPE--------------------- + RISCV_INSN_VXMS_VSBC, + RISCV_INSN_VXMS_VADC, + //--------------------- RISCV_CLZ--------------------- + RISCV_INSN_CLZ, + //--------------------- RISCV_UTYPE--------------------- + RISCV_INSN_LUI, + RISCV_INSN_AUIPC, + //--------------------- RISCV_CLMULH--------------------- + RISCV_INSN_CLMULH, + //--------------------- RISCV_FLI_H--------------------- + RISCV_INSN_FLI_H, + //--------------------- RISCV_F_UN_X_TYPE_H--------------------- + RISCV_INSN_FMV_X_H, + RISCV_INSN_FCLASS_H, + //--------------------- RISCV_F_BIN_RM_TYPE_H--------------------- + RISCV_INSN_FSUB_H, + RISCV_INSN_FMUL_H, + RISCV_INSN_FDIV_H, + RISCV_INSN_FADD_H, + //--------------------- RISCV_VSETVLI--------------------- + RISCV_INSN_VSETVLI, + //--------------------- RISCV_C_SEXT_B--------------------- + RISCV_INSN_C_SEXT_B, + //--------------------- RISCV_VLUXSEGTYPE--------------------- + RISCV_INSN_VLUXSEGTYPE, + //--------------------- RISCV_SHA512SUM1R--------------------- + RISCV_INSN_SHA512SUM1R, + //--------------------- RISCV_VITYPE--------------------- + RISCV_INSN_VI_VXOR, + RISCV_INSN_VI_VSSRL, + RISCV_INSN_VI_VSSRA, + RISCV_INSN_VI_VSRL, + RISCV_INSN_VI_VSRA, + RISCV_INSN_VI_VSLL, + RISCV_INSN_VI_VSADDU, + RISCV_INSN_VI_VSADD, + RISCV_INSN_VI_VRSUB, + RISCV_INSN_VI_VOR, + RISCV_INSN_VI_VAND, + RISCV_INSN_VI_VADD, + //--------------------- RISCV_STORECON--------------------- + RISCV_INSN_STORECON, + //--------------------- RISCV_VMVRTYPE--------------------- + RISCV_INSN_VMVRTYPE, + //--------------------- RISCV_ZBKB_RTYPE--------------------- + RISCV_INSN_PACKH, + RISCV_INSN_PACK, + //--------------------- RISCV_VWSLL_VX--------------------- + RISCV_INSN_VWSLL_VX, + //--------------------- RISCV_F_UN_RM_FX_TYPE_H--------------------- + RISCV_INSN_FCVT_W_H, + RISCV_INSN_FCVT_WU_H, + RISCV_INSN_FCVT_L_H, + RISCV_INSN_FCVT_LU_H, + //--------------------- RISCV_VISG--------------------- + RISCV_INSN_VI_VSLIDEUP, + RISCV_INSN_VI_VSLIDEDOWN, + RISCV_INSN_VI_VRGATHER, + //--------------------- RISCV_VCLMUL_VX--------------------- + RISCV_INSN_VCLMUL_VX, + //--------------------- RISCV_C_ADD--------------------- + RISCV_INSN_C_ADD, + //--------------------- RISCV_FVFTYPE--------------------- + RISCV_INSN_VF_VSUB, + RISCV_INSN_VF_VSLIDE1UP, + RISCV_INSN_VF_VSLIDE1DOWN, + RISCV_INSN_VF_VSGNJX, + RISCV_INSN_VF_VSGNJN, + RISCV_INSN_VF_VSGNJ, + RISCV_INSN_VF_VRSUB, + RISCV_INSN_VF_VRDIV, + RISCV_INSN_VF_VMUL, + RISCV_INSN_VF_VMIN, + RISCV_INSN_VF_VMAX, + RISCV_INSN_VF_VDIV, + RISCV_INSN_VF_VADD, + //--------------------- RISCV_F_UN_RM_FX_TYPE_D--------------------- + RISCV_INSN_FCVT_W_D, + RISCV_INSN_FCVT_WU_D, + RISCV_INSN_FCVT_L_D, + RISCV_INSN_FCVT_LU_D, + //--------------------- RISCV_FENCE_RESERVED--------------------- + RISCV_INSN_FENCE_RESERVED, + //--------------------- RISCV_MASKTYPEI--------------------- + RISCV_INSN_MASKTYPEI, + //--------------------- RISCV_FVVTYPE--------------------- + RISCV_INSN_FVV_VSUB, + RISCV_INSN_FVV_VSGNJX, + RISCV_INSN_FVV_VSGNJN, + RISCV_INSN_FVV_VSGNJ, + RISCV_INSN_FVV_VMUL, + RISCV_INSN_FVV_VMIN, + RISCV_INSN_FVV_VMAX, + RISCV_INSN_FVV_VDIV, + RISCV_INSN_FVV_VADD, + //--------------------- RISCV_CPOPW--------------------- + RISCV_INSN_CPOPW, + //--------------------- RISCV_C_LI_HINT--------------------- + RISCV_INSN_C_LI_HINT, + //--------------------- RISCV_SHA256SUM1--------------------- + RISCV_INSN_SHA256SUM1, + //--------------------- RISCV_VSUXSEGTYPE--------------------- + RISCV_INSN_VSUXSEGTYPE, + //--------------------- RISCV_VANDN_VX--------------------- + RISCV_INSN_VANDN_VX, + //--------------------- RISCV_VCTZ_V--------------------- + RISCV_INSN_VCTZ_V, + //--------------------- RISCV_F_UN_RM_XF_TYPE_D--------------------- + RISCV_INSN_FCVT_D_WU, + RISCV_INSN_FCVT_D_W, + RISCV_INSN_FCVT_D_LU, + RISCV_INSN_FCVT_D_L, + //--------------------- RISCV_VIMCTYPE--------------------- + RISCV_INSN_VIMC_VMADC, + //--------------------- RISCV_VIMSTYPE--------------------- + RISCV_INSN_VIMS_VADC, + //--------------------- RISCV_MASKTYPEV--------------------- + RISCV_INSN_MASKTYPEV, + //--------------------- RISCV_THREAD_START--------------------- + RISCV_INSN_THREAD_START, + //--------------------- RISCV_FVFMTYPE--------------------- + RISCV_INSN_VFM_VMFNE, + RISCV_INSN_VFM_VMFLT, + RISCV_INSN_VFM_VMFLE, + RISCV_INSN_VFM_VMFGT, + RISCV_INSN_VFM_VMFGE, + RISCV_INSN_VFM_VMFEQ, + //--------------------- RISCV_ADDIW--------------------- + RISCV_INSN_ADDIW, + //--------------------- RISCV_MRET--------------------- + RISCV_INSN_MRET, + //--------------------- RISCV_VLSEGFFTYPE--------------------- + RISCV_INSN_VLSEGFFTYPE, + //--------------------- RISCV_C_ANDI--------------------- + RISCV_INSN_C_ANDI, + //--------------------- RISCV_WVTYPE--------------------- + RISCV_INSN_WV_VSUBU, + RISCV_INSN_WV_VSUB, + RISCV_INSN_WV_VADDU, + RISCV_INSN_WV_VADD, + //--------------------- RISCV_C_SDSP--------------------- + RISCV_INSN_C_SDSP, + //--------------------- RISCV_C_SUBW--------------------- + RISCV_INSN_C_SUBW, + //--------------------- RISCV_VEXT4TYPE--------------------- + RISCV_INSN_VEXT4_ZVF4, + RISCV_INSN_VEXT4_SVF4, + //--------------------- RISCV_VSETVL--------------------- + RISCV_INSN_VSETVL, + //--------------------- RISCV_C_SH--------------------- + RISCV_INSN_C_SH, + //--------------------- RISCV_MVVCOMPRESS--------------------- + RISCV_INSN_MVVCOMPRESS, + //--------------------- RISCV_FWVVTYPE--------------------- + RISCV_INSN_FWVV_VSUB, + RISCV_INSN_FWVV_VMUL, + RISCV_INSN_FWVV_VADD, + //--------------------- RISCV_VMTYPE--------------------- + RISCV_INSN_VSM, + RISCV_INSN_VLM, + //--------------------- RISCV_FROUND_H--------------------- + RISCV_INSN_FROUND_H, + //--------------------- RISCV_C_JAL--------------------- + RISCV_INSN_C_JAL, + //--------------------- RISCV_SFENCE_VMA--------------------- + RISCV_INSN_SFENCE_VMA, + //--------------------- RISCV_STOP_FETCHING--------------------- + RISCV_INSN_STOP_FETCHING, + //--------------------- RISCV_NVSTYPE--------------------- + RISCV_INSN_NVS_VNSRL, + RISCV_INSN_NVS_VNSRA, + //--------------------- RISCV_FROUND_S--------------------- + RISCV_INSN_FROUND_S, + //--------------------- RISCV_NISTYPE--------------------- + RISCV_INSN_NIS_VNSRL, + RISCV_INSN_NIS_VNSRA, + //--------------------- RISCV_C_SLLI--------------------- + RISCV_INSN_C_SLLI, + //--------------------- RISCV_VXMTYPE--------------------- + RISCV_INSN_VXM_VMSBC, + RISCV_INSN_VXM_VMADC, + //--------------------- RISCV_FENCEI--------------------- + RISCV_INSN_FENCEI, + //--------------------- RISCV_F_UN_F_TYPE_D--------------------- + RISCV_INSN_FMV_D_X, + //--------------------- RISCV_VFMVSF--------------------- + RISCV_INSN_VFMVSF, + //--------------------- RISCV_VEXT8TYPE--------------------- + RISCV_INSN_VEXT8_ZVF8, + RISCV_INSN_VEXT8_SVF8, + //--------------------- RISCV_C_OR--------------------- + RISCV_INSN_C_OR, + //--------------------- RISCV_FWVFMATYPE--------------------- + RISCV_INSN_FWVF_VNMSAC, + RISCV_INSN_FWVF_VNMACC, + RISCV_INSN_FWVF_VMSAC, + RISCV_INSN_FWVF_VMACC, + //--------------------- RISCV_SHIFTIOP--------------------- + RISCV_INSN_SRLI, + RISCV_INSN_SRAI, + RISCV_INSN_SLLI, + //--------------------- RISCV_DIVW--------------------- + RISCV_INSN_DIVW, + //--------------------- RISCV_C_ZEXT_B--------------------- + RISCV_INSN_C_ZEXT_B, + //--------------------- RISCV_C_MV--------------------- + RISCV_INSN_C_MV, + //--------------------- RISCV_VIMTYPE--------------------- + RISCV_INSN_VIM_VMADC, + //--------------------- RISCV_F_UN_RM_FF_TYPE_H--------------------- + RISCV_INSN_FSQRT_H, + RISCV_INSN_FCVT_S_H, + RISCV_INSN_FCVT_H_S, + RISCV_INSN_FCVT_H_D, + RISCV_INSN_FCVT_D_H, + //--------------------- RISCV_LOADRES--------------------- + RISCV_INSN_LOADRES, + //--------------------- RISCV_C_J--------------------- + RISCV_INSN_C_J, + //--------------------- RISCV_AES32ESI--------------------- + RISCV_INSN_AES32ESI, + //--------------------- RISCV_C_BEQZ--------------------- + RISCV_INSN_C_BEQZ, + //--------------------- RISCV_SHA512SUM0--------------------- + RISCV_INSN_SHA512SUM0, + //--------------------- RISCV_SHA512SUM0R--------------------- + RISCV_INSN_SHA512SUM0R, + //--------------------- RISCV_REMW--------------------- + RISCV_INSN_REMW, + //--------------------- RISCV_VFMV--------------------- + RISCV_INSN_VFMV, + //--------------------- RISCV_C_SEXT_H--------------------- + RISCV_INSN_C_SEXT_H, + //--------------------- RISCV_WMVXTYPE--------------------- + RISCV_INSN_WMVX_VWMACCUS, + RISCV_INSN_WMVX_VWMACCU, + RISCV_INSN_WMVX_VWMACCSU, + RISCV_INSN_WMVX_VWMACC, + //--------------------- RISCV_C_FSW--------------------- + RISCV_INSN_C_FSW, + //--------------------- RISCV_C_SW--------------------- + RISCV_INSN_C_SW, + //--------------------- RISCV_ZBS_RTYPE--------------------- + RISCV_INSN_BSET, + RISCV_INSN_BINV, + RISCV_INSN_BEXT, + RISCV_INSN_BCLR, + //--------------------- RISCV_F_BIN_TYPE_X_S--------------------- + RISCV_INSN_FLT_S, + RISCV_INSN_FLE_S, + RISCV_INSN_FEQ_S, + //--------------------- RISCV_C_SUB--------------------- + RISCV_INSN_C_SUB, + //--------------------- RISCV_VFUNARY0--------------------- + RISCV_INSN_FV_CVT_X_F, + RISCV_INSN_FV_CVT_XU_F, + RISCV_INSN_FV_CVT_RTZ_X_F, + RISCV_INSN_FV_CVT_RTZ_XU_F, + RISCV_INSN_FV_CVT_F_XU, + RISCV_INSN_FV_CVT_F_X, + //--------------------- RISCV_FROUNDNX_S--------------------- + RISCV_INSN_FROUNDNX_S, + //--------------------- RISCV_ZICBOZ--------------------- + RISCV_INSN_ZICBOZ, + //--------------------- RISCV_SFENCE_W_INVAL--------------------- + RISCV_INSN_SFENCE_W_INVAL, + //--------------------- RISCV_C_JR--------------------- + RISCV_INSN_C_JR, + //--------------------- RISCV_C_NOT--------------------- + RISCV_INSN_C_NOT, + //--------------------- RISCV_ZBB_EXTOP--------------------- + RISCV_INSN_ZEXTH, + RISCV_INSN_SEXTH, + RISCV_INSN_SEXTB, + //--------------------- RISCV_MVVTYPE--------------------- + RISCV_INSN_MVV_VREMU, + RISCV_INSN_MVV_VREM, + RISCV_INSN_MVV_VMULHU, + RISCV_INSN_MVV_VMULHSU, + RISCV_INSN_MVV_VMULH, + RISCV_INSN_MVV_VMUL, + RISCV_INSN_MVV_VDIVU, + RISCV_INSN_MVV_VDIV, + RISCV_INSN_MVV_VASUBU, + RISCV_INSN_MVV_VASUB, + RISCV_INSN_MVV_VAADDU, + RISCV_INSN_MVV_VAADD, + //--------------------- RISCV_FVFMATYPE--------------------- + RISCV_INSN_VF_VNMSUB, + RISCV_INSN_VF_VNMSAC, + RISCV_INSN_VF_VNMADD, + RISCV_INSN_VF_VNMACC, + RISCV_INSN_VF_VMSUB, + RISCV_INSN_VF_VMSAC, + RISCV_INSN_VF_VMADD, + RISCV_INSN_VF_VMACC, + //--------------------- RISCV_FMAXM_H--------------------- + RISCV_INSN_FMAXM_H, + //--------------------- RISCV_SHA256SUM0--------------------- + RISCV_INSN_SHA256SUM0, + //--------------------- RISCV_ZBS_IOP--------------------- + RISCV_INSN_BSETI, + RISCV_INSN_BINVI, + RISCV_INSN_BEXTI, + RISCV_INSN_BCLRI, + //--------------------- RISCV_C_XOR--------------------- + RISCV_INSN_C_XOR, + //--------------------- RISCV_ZIMOP_MOP_R--------------------- + RISCV_INSN_ZIMOP_MOP_R, + //--------------------- RISCV_FMINM_H--------------------- + RISCV_INSN_FMINM_H, + //--------------------- RISCV_C_LUI_HINT--------------------- + RISCV_INSN_C_LUI_HINT, + //--------------------- RISCV_VVMCTYPE--------------------- + RISCV_INSN_VVMC_VMSBC, + RISCV_INSN_VVMC_VMADC, + //--------------------- RISCV_F_UN_RM_XF_TYPE_H--------------------- + RISCV_INSN_FCVT_H_WU, + RISCV_INSN_FCVT_H_W, + RISCV_INSN_FCVT_H_LU, + RISCV_INSN_FCVT_H_L, + //--------------------- RISCV_F_BIN_RM_TYPE_S--------------------- + RISCV_INSN_FSUB_S, + RISCV_INSN_FMUL_S, + RISCV_INSN_FDIV_S, + RISCV_INSN_FADD_S, + //--------------------- RISCV_SINVAL_VMA--------------------- + RISCV_INSN_SINVAL_VMA, + //--------------------- RISCV_MOVETYPEX--------------------- + RISCV_INSN_MOVETYPEX, + //--------------------- RISCV_VCPOP_V--------------------- + RISCV_INSN_VCPOP_V, + //--------------------- RISCV_C_BNEZ--------------------- + RISCV_INSN_C_BNEZ, + //--------------------- RISCV_FWVVMATYPE--------------------- + RISCV_INSN_FWVV_VNMSAC, + RISCV_INSN_FWVV_VNMACC, + RISCV_INSN_FWVV_VMSAC, + RISCV_INSN_FWVV_VMACC, + //--------------------- RISCV_AES64KS1I--------------------- + RISCV_INSN_AES64KS1I, + //--------------------- RISCV_F_BIN_X_TYPE_D--------------------- + RISCV_INSN_FLT_D, + RISCV_INSN_FLE_D, + RISCV_INSN_FEQ_D, + //--------------------- RISCV_RMVVTYPE--------------------- + RISCV_INSN_MVV_VREDXOR, + RISCV_INSN_MVV_VREDSUM, + RISCV_INSN_MVV_VREDOR, + RISCV_INSN_MVV_VREDMINU, + RISCV_INSN_MVV_VREDMIN, + RISCV_INSN_MVV_VREDMAXU, + RISCV_INSN_MVV_VREDMAX, + RISCV_INSN_MVV_VREDAND, + //--------------------- RISCV_F_UN_RM_XF_TYPE_S--------------------- + RISCV_INSN_FCVT_S_WU, + RISCV_INSN_FCVT_S_W, + RISCV_INSN_FCVT_S_LU, + RISCV_INSN_FCVT_S_L, + //--------------------- RISCV_CLZW--------------------- + RISCV_INSN_CLZW, + //--------------------- RISCV_REM--------------------- + RISCV_INSN_REM, + //--------------------- RISCV_C_EBREAK--------------------- + RISCV_INSN_C_EBREAK, + //--------------------- RISCV_AES64ESM--------------------- + RISCV_INSN_AES64ESM, + //--------------------- RISCV_VFNUNARY0--------------------- + RISCV_INSN_FNV_CVT_X_F, + RISCV_INSN_FNV_CVT_XU_F, + RISCV_INSN_FNV_CVT_RTZ_X_F, + RISCV_INSN_FNV_CVT_RTZ_XU_F, + RISCV_INSN_FNV_CVT_ROD_F_F, + RISCV_INSN_FNV_CVT_F_XU, + RISCV_INSN_FNV_CVT_F_X, + RISCV_INSN_FNV_CVT_F_F, + //--------------------- RISCV_VFWUNARY0--------------------- + RISCV_INSN_FWV_CVT_X_F, + RISCV_INSN_FWV_CVT_XU_F, + RISCV_INSN_FWV_CVT_RTZ_X_F, + RISCV_INSN_FWV_CVT_RTZ_XU_F, + RISCV_INSN_FWV_CVT_F_XU, + RISCV_INSN_FWV_CVT_F_X, + RISCV_INSN_FWV_CVT_F_F, + //--------------------- RISCV_MOVETYPEV--------------------- + RISCV_INSN_MOVETYPEV, + //--------------------- RISCV_VFUNARY1--------------------- + RISCV_INSN_FVV_VSQRT, + RISCV_INSN_FVV_VRSQRT7, + RISCV_INSN_FVV_VREC7, + RISCV_INSN_FVV_VCLASS, + //--------------------- RISCV_FWVFTYPE--------------------- + RISCV_INSN_FWVF_VSUB, + RISCV_INSN_FWVF_VMUL, + RISCV_INSN_FWVF_VADD, + //--------------------- RISCV_ZBA_RTYPE--------------------- + RISCV_INSN_SH3ADD, + RISCV_INSN_SH2ADD, + RISCV_INSN_SH1ADD, + //--------------------- RISCV_C_SRLI--------------------- + RISCV_INSN_C_SRLI, + //--------------------- RISCV_VSRETYPE--------------------- + RISCV_INSN_VSRETYPE, + //--------------------- RISCV_C_SLLI_HINT--------------------- + RISCV_INSN_C_SLLI_HINT, + //--------------------- RISCV_WVVTYPE--------------------- + RISCV_INSN_WVV_VWMULU, + RISCV_INSN_WVV_VWMULSU, + RISCV_INSN_WVV_VWMUL, + RISCV_INSN_WVV_VSUBU, + RISCV_INSN_WVV_VSUB, + RISCV_INSN_WVV_VADDU, + RISCV_INSN_WVV_VADD, + //--------------------- RISCV_F_BIN_TYPE_F_S--------------------- + RISCV_INSN_FSGNJ_S, + RISCV_INSN_FSGNJX_S, + RISCV_INSN_FSGNJN_S, + RISCV_INSN_FMIN_S, + RISCV_INSN_FMAX_S, + //--------------------- RISCV_AES64DSM--------------------- + RISCV_INSN_AES64DSM, + //--------------------- RISCV_C_LI--------------------- + RISCV_INSN_C_LI, + //--------------------- RISCV_F_BIN_X_TYPE_H--------------------- + RISCV_INSN_FLT_H, + RISCV_INSN_FLE_H, + RISCV_INSN_FEQ_H, + //--------------------- RISCV_C_SRAI--------------------- + RISCV_INSN_C_SRAI, + //--------------------- RISCV_F_UN_RM_FF_TYPE_D--------------------- + RISCV_INSN_FSQRT_D, + RISCV_INSN_FCVT_S_D, + RISCV_INSN_FCVT_D_S, + //--------------------- RISCV_FMVP_D_X--------------------- + RISCV_INSN_FMVP_D_X, + //--------------------- RISCV_C_LBU--------------------- + RISCV_INSN_C_LBU, + //--------------------- RISCV_RTYPEW--------------------- + RISCV_INSN_SUBW, + RISCV_INSN_SRLW, + RISCV_INSN_SRAW, + RISCV_INSN_SLLW, + RISCV_INSN_ADDW, + //--------------------- RISCV_WMVVTYPE--------------------- + RISCV_INSN_WMVV_VWMACCU, + RISCV_INSN_WMVV_VWMACCSU, + RISCV_INSN_WMVV_VWMACC, + //--------------------- RISCV_MULW--------------------- + RISCV_INSN_MULW, + //--------------------- RISCV_VWSLL_VV--------------------- + RISCV_INSN_VWSLL_VV, + //--------------------- RISCV_VVCMPTYPE--------------------- + RISCV_INSN_VVCMP_VMSNE, + RISCV_INSN_VVCMP_VMSLTU, + RISCV_INSN_VVCMP_VMSLT, + RISCV_INSN_VVCMP_VMSLEU, + RISCV_INSN_VVCMP_VMSLE, + RISCV_INSN_VVCMP_VMSEQ, + //--------------------- RISCV_ILLEGAL--------------------- + RISCV_INSN_ILLEGAL, + //--------------------- RISCV_VREV8_V--------------------- + RISCV_INSN_VREV8_V, + //--------------------- RISCV_BREV8--------------------- + RISCV_INSN_BREV8, + //--------------------- RISCV_VCLMULH_VV--------------------- + RISCV_INSN_VCLMULH_VV, + //--------------------- RISCV_AES32DSMI--------------------- + RISCV_INSN_AES32DSMI, + //--------------------- RISCV_VANDN_VV--------------------- + RISCV_INSN_VANDN_VV, + //--------------------- RISCV_C_FSD--------------------- + RISCV_INSN_C_FSD, + //--------------------- RISCV_C_ADDW--------------------- + RISCV_INSN_C_ADDW, + //--------------------- RISCV_VCPOP_M--------------------- + RISCV_INSN_VCPOP_M, + //--------------------- RISCV_SHA256SIG1--------------------- + RISCV_INSN_SHA256SIG1, + //--------------------- RISCV_MVXTYPE--------------------- + RISCV_INSN_MVX_VSLIDE1UP, + RISCV_INSN_MVX_VSLIDE1DOWN, + RISCV_INSN_MVX_VREMU, + RISCV_INSN_MVX_VREM, + RISCV_INSN_MVX_VMULHU, + RISCV_INSN_MVX_VMULHSU, + RISCV_INSN_MVX_VMULH, + RISCV_INSN_MVX_VMUL, + RISCV_INSN_MVX_VDIVU, + RISCV_INSN_MVX_VDIV, + RISCV_INSN_MVX_VASUBU, + RISCV_INSN_MVX_VASUB, + RISCV_INSN_MVX_VAADDU, + RISCV_INSN_MVX_VAADD, +}; +#endif diff --git a/arch/RISCV/RISCVInsnMappings.gen.inc b/arch/RISCV/RISCVInsnMappings.gen.inc new file mode 100644 index 0000000000..ec5a353bba --- /dev/null +++ b/arch/RISCV/RISCVInsnMappings.gen.inc @@ -0,0 +1,719 @@ +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ + +#ifndef __RISCVINSNMAPPINGS_GEN_INC__ +#define __RISCVINSNMAPPINGS_GEN_INC__ +#include +#include +#include + +#include "RISCVInsn.gen.inc" + +static const uint16_t to_insn[334][21] = { + [RISCV_REV8] = {RISCV_INSN_REV8}, + [RISCV_WXTYPE] = {RISCV_INSN_WX_VSUBU, RISCV_INSN_WX_VSUB, + RISCV_INSN_WX_VADDU, RISCV_INSN_WX_VADD}, + [RISCV_C_SRLI_HINT] = {RISCV_INSN_C_SRLI_HINT}, + [RISCV_AES64DS] = {RISCV_INSN_AES64DS}, + [RISCV_VMSBF_M] = {RISCV_INSN_VMSBF_M}, + [RISCV_RTYPE] = {RISCV_INSN_XOR, RISCV_INSN_SUB, RISCV_INSN_SRL, + RISCV_INSN_SRA, RISCV_INSN_SLTU, RISCV_INSN_SLT, + RISCV_INSN_SLL, RISCV_INSN_OR, RISCV_INSN_AND, + RISCV_INSN_ADD}, + [RISCV_VFMERGE] = {RISCV_INSN_VFMERGE}, + [RISCV_RIVVTYPE] = {RISCV_INSN_IVV_VWREDSUMU, RISCV_INSN_IVV_VWREDSUM}, + [RISCV_F_BIN_F_TYPE_H] = {RISCV_INSN_FSGNJ_H, RISCV_INSN_FSGNJX_H, + RISCV_INSN_FSGNJN_H, RISCV_INSN_FMIN_H, + RISCV_INSN_FMAX_H}, + [RISCV_C_ZEXT_W] = {RISCV_INSN_C_ZEXT_W}, + [RISCV_SFENCE_INVAL_IR] = {RISCV_INSN_SFENCE_INVAL_IR}, + [RISCV_XPERM4] = {RISCV_INSN_XPERM4}, + [RISCV_F_UN_TYPE_F_S] = {RISCV_INSN_FMV_W_X}, + [RISCV_C_AND] = {RISCV_INSN_C_AND}, + [RISCV_AES32DSI] = {RISCV_INSN_AES32DSI}, + [RISCV_RORI] = {RISCV_INSN_RORI}, + [RISCV_JALR] = {RISCV_INSN_JALR}, + [RISCV_VMSIF_M] = {RISCV_INSN_VMSIF_M}, + [RISCV_CSRImm] = {RISCV_INSN_CSRRW, RISCV_INSN_CSRRS, RISCV_INSN_CSRRC}, + [RISCV_VLSSEGTYPE] = {RISCV_INSN_VLSSEGTYPE}, + [RISCV_SHA512SIG1H] = {RISCV_INSN_SHA512SIG1H}, + [RISCV_FLTQ_S] = {RISCV_INSN_FLTQ_S}, + [RISCV_VXSG] = {RISCV_INSN_VX_VSLIDEUP, RISCV_INSN_VX_VSLIDEDOWN, + RISCV_INSN_VX_VRGATHER}, + [RISCV_VXCMPTYPE] = {RISCV_INSN_VXCMP_VMSNE, RISCV_INSN_VXCMP_VMSLTU, + RISCV_INSN_VXCMP_VMSLT, RISCV_INSN_VXCMP_VMSLEU, + RISCV_INSN_VXCMP_VMSLE, RISCV_INSN_VXCMP_VMSGTU, + RISCV_INSN_VXCMP_VMSGT, RISCV_INSN_VXCMP_VMSEQ}, + [RISCV_C_LHU] = {RISCV_INSN_C_LHU}, + [RISCV_F_UN_RM_FX_TYPE_S] = {RISCV_INSN_FCVT_W_S, RISCV_INSN_FCVT_WU_S, + RISCV_INSN_FCVT_L_S, RISCV_INSN_FCVT_LU_S}, + [RISCV_JAL] = {RISCV_INSN_JAL}, + [RISCV_ECALL] = {RISCV_INSN_ECALL}, + [RISCV_F_UN_X_TYPE_D] = {RISCV_INSN_FMV_X_D, RISCV_INSN_FCLASS_D}, + [RISCV_C_FSWSP] = {RISCV_INSN_C_FSWSP}, + [RISCV_VMVXS] = {RISCV_INSN_VMVXS}, + [RISCV_ZVKSHA2TYPE] = {RISCV_INSN_ZVK_VSHA2CL, RISCV_INSN_ZVK_VSHA2CH}, + [RISCV_C_FLD] = {RISCV_INSN_C_FLD}, + [RISCV_SHIFTIWOP] = {RISCV_INSN_SRLIW, RISCV_INSN_SRAIW, RISCV_INSN_SLLIW}, + [RISCV_UNZIP] = {RISCV_INSN_UNZIP}, + [RISCV_ZICBOM] = {RISCV_INSN_CBO_INVAL, RISCV_INSN_CBO_FLUSH, + RISCV_INSN_CBO_CLEAN}, + [RISCV_SHA512SIG1] = {RISCV_INSN_SHA512SIG1}, + [RISCV_NITYPE] = {RISCV_INSN_NI_VNCLIPU, RISCV_INSN_NI_VNCLIP}, + [RISCV_WFI] = {RISCV_INSN_WFI}, + [RISCV_VVMTYPE] = {RISCV_INSN_VVM_VMSBC, RISCV_INSN_VVM_VMADC}, + [RISCV_MVXMATYPE] = {RISCV_INSN_MVX_VNMSUB, RISCV_INSN_MVX_VNMSAC, + RISCV_INSN_MVX_VMADD, RISCV_INSN_MVX_VMACC}, + [RISCV_FLI_D] = {RISCV_INSN_FLI_D}, + [RISCV_C_ADDI_HINT] = {RISCV_INSN_C_ADDI_HINT}, + [RISCV_MASKTYPEX] = {RISCV_INSN_MASKTYPEX}, + [RISCV_FROUNDNX_D] = {RISCV_INSN_FROUNDNX_D}, + [RISCV_FROUND_D] = {RISCV_INSN_FROUND_D}, + [RISCV_VSETIVLI] = {RISCV_INSN_VSETIVLI}, + [RISCV_FMAXM_D] = {RISCV_INSN_FMAXM_D}, + [RISCV_C_SD] = {RISCV_INSN_C_SD}, + [RISCV_ZBKB_PACKW] = {RISCV_INSN_ZBKB_PACKW}, + [RISCV_FVVMTYPE] = {RISCV_INSN_FVVM_VMFNE, RISCV_INSN_FVVM_VMFLT, + RISCV_INSN_FVVM_VMFLE, RISCV_INSN_FVVM_VMFEQ}, + [RISCV_VMVSX] = {RISCV_INSN_VMVSX}, + [RISCV_ORCB] = {RISCV_INSN_ORCB}, + [RISCV_C_MUL] = {RISCV_INSN_C_MUL}, + [RISCV_SM3P1] = {RISCV_INSN_SM3P1}, + [RISCV_CLMUL] = {RISCV_INSN_CLMUL}, + [RISCV_FLEQ_S] = {RISCV_INSN_FLEQ_S}, + [RISCV_F_UN_RM_FF_TYPE_S] = {RISCV_INSN_FSQRT_S}, + [RISCV_WVXTYPE] = {RISCV_INSN_WVX_VWMULU, RISCV_INSN_WVX_VWMULSU, + RISCV_INSN_WVX_VWMUL, RISCV_INSN_WVX_VSUBU, + RISCV_INSN_WVX_VSUB, RISCV_INSN_WVX_VADDU, + RISCV_INSN_WVX_VADD}, + [RISCV_FMAXM_S] = {RISCV_INSN_FMAXM_S}, + [RISCV_C_ILLEGAL] = {RISCV_INSN_C_ILLEGAL}, + [RISCV_NXSTYPE] = {RISCV_INSN_NXS_VNSRL, RISCV_INSN_NXS_VNSRA}, + [RISCV_VSOXSEGTYPE] = {RISCV_INSN_VSOXSEGTYPE}, + [RISCV_C_NOP] = {RISCV_INSN_C_NOP}, + [RISCV_VXMCTYPE] = {RISCV_INSN_VXMC_VMSBC, RISCV_INSN_VXMC_VMADC}, + [RISCV_MMTYPE] = {RISCV_INSN_MM_VMXOR, RISCV_INSN_MM_VMXNOR, + RISCV_INSN_MM_VMORN, RISCV_INSN_MM_VMOR, + RISCV_INSN_MM_VMNOR, RISCV_INSN_MM_VMNAND, + RISCV_INSN_MM_VMANDN, RISCV_INSN_MM_VMAND}, + [RISCV_NVTYPE] = {RISCV_INSN_NV_VNCLIPU, RISCV_INSN_NV_VNCLIP}, + [RISCV_AES64KS2] = {RISCV_INSN_AES64KS2}, + [RISCV_F_BIN_F_TYPE_D] = {RISCV_INSN_FSGNJ_D, RISCV_INSN_FSGNJX_D, + RISCV_INSN_FSGNJN_D, RISCV_INSN_FMIN_D, + RISCV_INSN_FMAX_D}, + [RISCV_AES32ESMI] = {RISCV_INSN_AES32ESMI}, + [RISCV_F_MADD_TYPE_H] = {RISCV_INSN_FNMSUB_H, RISCV_INSN_FNMADD_H, + RISCV_INSN_FMSUB_H, RISCV_INSN_FMADD_H}, + [RISCV_FROUNDNX_H] = {RISCV_INSN_FROUNDNX_H}, + [RISCV_MOVETYPEI] = {RISCV_INSN_MOVETYPEI}, + [RISCV_FLTQ_H] = {RISCV_INSN_FLTQ_H}, + [RISCV_C_LW] = {RISCV_INSN_C_LW}, + [RISCV_C_LWSP] = {RISCV_INSN_C_LWSP}, + [RISCV_C_ADDI16SP] = {RISCV_INSN_C_ADDI16SP}, + [RISCV_CSRReg] = {RISCV_INSN_CSRRW, RISCV_INSN_CSRRS, RISCV_INSN_CSRRC}, + [RISCV_SHA512SIG0L] = {RISCV_INSN_SHA512SIG0L}, + [RISCV_SM3P0] = {RISCV_INSN_SM3P0}, + [RISCV_SM4ED] = {RISCV_INSN_SM4ED}, + [RISCV_FMINM_D] = {RISCV_INSN_FMINM_D}, + [RISCV_AES64IM] = {RISCV_INSN_AES64IM}, + [RISCV_VLRETYPE] = {RISCV_INSN_VLRETYPE}, + [RISCV_VFMVFS] = {RISCV_INSN_VFMVFS}, + [RISCV_CTZ] = {RISCV_INSN_CTZ}, + [RISCV_FMVH_X_D] = {RISCV_INSN_FMVH_X_D}, + [RISCV_SLLIUW] = {RISCV_INSN_SLLIUW}, + [RISCV_ZCMOP] = {RISCV_INSN_ZCMOP}, + [RISCV_FMINM_S] = {RISCV_INSN_FMINM_S}, + [RISCV_ZBA_RTYPEUW] = {RISCV_INSN_SH3ADDUW, RISCV_INSN_SH2ADDUW, + RISCV_INSN_SH1ADDUW, RISCV_INSN_ADDUW}, + [RISCV_F_BIN_RM_TYPE_D] = {RISCV_INSN_FSUB_D, RISCV_INSN_FMUL_D, + RISCV_INSN_FDIV_D, RISCV_INSN_FADD_D}, + [RISCV_C_ADD_HINT] = {RISCV_INSN_C_ADD_HINT}, + [RISCV_F_MADD_TYPE_S] = {RISCV_INSN_FNMSUB_S, RISCV_INSN_FNMADD_S, + RISCV_INSN_FMSUB_S, RISCV_INSN_FMADD_S}, + [RISCV_ZIP] = {RISCV_INSN_ZIP}, + [RISCV_SHA512SUM1] = {RISCV_INSN_SHA512SUM1}, + [RISCV_VROR_VI] = {RISCV_INSN_VROR_VI}, + [RISCV_C_LDSP] = {RISCV_INSN_C_LDSP}, + [RISCV_VBREV_V] = {RISCV_INSN_VBREV_V}, + [RISCV_CPOP] = {RISCV_INSN_CPOP}, + [RISCV_FWFTYPE] = {RISCV_INSN_FWF_VSUB, RISCV_INSN_FWF_VADD}, + [RISCV_FWVTYPE] = {RISCV_INSN_FWV_VSUB, RISCV_INSN_FWV_VADD}, + [RISCV_ZBB_RTYPE] = {RISCV_INSN_XNOR, RISCV_INSN_ROR, RISCV_INSN_ROL, + RISCV_INSN_ORN, RISCV_INSN_MINU, RISCV_INSN_MIN, + RISCV_INSN_MAXU, RISCV_INSN_MAX, RISCV_INSN_ANDN}, + [RISCV_SM4KS] = {RISCV_INSN_SM4KS}, + [RISCV_RORIW] = {RISCV_INSN_RORIW}, + [RISCV_F_UN_TYPE_X_S] = {RISCV_INSN_FMV_X_W, RISCV_INSN_FCLASS_S}, + [RISCV_NXTYPE] = {RISCV_INSN_NX_VNCLIPU, RISCV_INSN_NX_VNCLIP}, + [RISCV_C_ADDIW] = {RISCV_INSN_C_ADDIW}, + [RISCV_C_LD] = {RISCV_INSN_C_LD}, + [RISCV_CTZW] = {RISCV_INSN_CTZW}, + [RISCV_XPERM8] = {RISCV_INSN_XPERM8}, + [RISCV_ITYPE] = {RISCV_INSN_XORI, RISCV_INSN_SLTIU, RISCV_INSN_SLTI, + RISCV_INSN_ORI, RISCV_INSN_ANDI, RISCV_INSN_ADDI}, + [RISCV_VCLMUL_VV] = {RISCV_INSN_VCLMUL_VV}, + [RISCV_F_UN_F_TYPE_H] = {RISCV_INSN_FMV_H_X}, + [RISCV_VCLZ_V] = {RISCV_INSN_VCLZ_V}, + [RISCV_VID_V] = {RISCV_INSN_VID_V}, + [RISCV_FENCE] = {RISCV_INSN_FENCE}, + [RISCV_C_FLWSP] = {RISCV_INSN_C_FLWSP}, + [RISCV_STORE] = {RISCV_INSN_STORE}, + [RISCV_VBREV8_V] = {RISCV_INSN_VBREV8_V}, + [RISCV_VSSEGTYPE] = {RISCV_INSN_VSSEGTYPE}, + [RISCV_ZICOND_RTYPE] = {RISCV_INSN_CZERO_NEZ, RISCV_INSN_CZERO_EQZ}, + [RISCV_VCLMULH_VX] = {RISCV_INSN_VCLMULH_VX}, + [RISCV_C_FSDSP] = {RISCV_INSN_C_FSDSP}, + [RISCV_SRET] = {RISCV_INSN_SRET}, + [RISCV_STORE_FP] = {RISCV_INSN_STORE_FP}, + [RISCV_C_JALR] = {RISCV_INSN_C_JALR}, + [RISCV_FENCE_TSO] = {RISCV_INSN_FENCE_TSO}, + [RISCV_SHA512SIG0] = {RISCV_INSN_SHA512SIG0}, + [RISCV_FLI_S] = {RISCV_INSN_FLI_S}, + [RISCV_C_SB] = {RISCV_INSN_C_SB}, + [RISCV_ZBB_RTYPEW] = {RISCV_INSN_RORW, RISCV_INSN_ROLW}, + [RISCV_C_FLDSP] = {RISCV_INSN_C_FLDSP}, + [RISCV_C_MV_HINT] = {RISCV_INSN_C_MV_HINT}, + [RISCV_VWSLL_VI] = {RISCV_INSN_VWSLL_VI}, + [RISCV_FCVTMOD_W_D] = {RISCV_INSN_FCVTMOD_W_D}, + [RISCV_RFVVTYPE] = {RISCV_INSN_FVV_VFWREDUSUM, RISCV_INSN_FVV_VFWREDOSUM, + RISCV_INSN_FVV_VFREDUSUM, RISCV_INSN_FVV_VFREDOSUM, + RISCV_INSN_FVV_VFREDMIN, RISCV_INSN_FVV_VFREDMAX}, + [RISCV_SHA512SIG0H] = {RISCV_INSN_SHA512SIG0H}, + [RISCV_AMO] = {RISCV_INSN_AMOXOR, RISCV_INSN_AMOSWAP, RISCV_INSN_AMOOR, + RISCV_INSN_AMOMINU, RISCV_INSN_AMOMIN, RISCV_INSN_AMOMAXU, + RISCV_INSN_AMOMAX, RISCV_INSN_AMOAND, RISCV_INSN_AMOADD}, + [RISCV_LOAD_FP] = {RISCV_INSN_LOAD_FP}, + [RISCV_VROL_VV] = {RISCV_INSN_VROL_VV}, + [RISCV_VVMSTYPE] = {RISCV_INSN_VVMS_VSBC, RISCV_INSN_VVMS_VADC}, + [RISCV_FVVMATYPE] = {RISCV_INSN_FVV_VNMSUB, RISCV_INSN_FVV_VNMSAC, + RISCV_INSN_FVV_VNMADD, RISCV_INSN_FVV_VNMACC, + RISCV_INSN_FVV_VMSUB, RISCV_INSN_FVV_VMSAC, + RISCV_INSN_FVV_VMADD, RISCV_INSN_FVV_VMACC}, + [RISCV_VEXT2TYPE] = {RISCV_INSN_VEXT2_ZVF2, RISCV_INSN_VEXT2_SVF2}, + [RISCV_EBREAK] = {RISCV_INSN_EBREAK}, + [RISCV_C_LUI] = {RISCV_INSN_C_LUI}, + [RISCV_F_MADD_TYPE_D] = {RISCV_INSN_FNMSUB_D, RISCV_INSN_FNMADD_D, + RISCV_INSN_FMSUB_D, RISCV_INSN_FMADD_D}, + [RISCV_C_ZEXT_H] = {RISCV_INSN_C_ZEXT_H}, + [RISCV_SHA512SIG1L] = {RISCV_INSN_SHA512SIG1L}, + [RISCV_VLSEGTYPE] = {RISCV_INSN_VLSEGTYPE}, + [RISCV_SHA256SIG0] = {RISCV_INSN_SHA256SIG0}, + [RISCV_ZIMOP_MOP_RR] = {RISCV_INSN_ZIMOP_MOP_RR}, + [RISCV_C_ADDI4SPN] = {RISCV_INSN_C_ADDI4SPN}, + [RISCV_VVTYPE] = {RISCV_INSN_VV_VXOR, RISCV_INSN_VV_VSUB, + RISCV_INSN_VV_VSSUBU, RISCV_INSN_VV_VSSUB, + RISCV_INSN_VV_VSSRL, RISCV_INSN_VV_VSSRA, + RISCV_INSN_VV_VSRL, RISCV_INSN_VV_VSRA, + RISCV_INSN_VV_VSMUL, RISCV_INSN_VV_VSLL, + RISCV_INSN_VV_VSADDU, RISCV_INSN_VV_VSADD, + RISCV_INSN_VV_VRGATHEREI16, RISCV_INSN_VV_VRGATHER, + RISCV_INSN_VV_VOR, RISCV_INSN_VV_VMINU, + RISCV_INSN_VV_VMIN, RISCV_INSN_VV_VMAXU, + RISCV_INSN_VV_VMAX, RISCV_INSN_VV_VAND, + RISCV_INSN_VV_VADD}, + [RISCV_VSHA2MS_VV] = {RISCV_INSN_VSHA2MS_VV}, + [RISCV_FLEQ_H] = {RISCV_INSN_FLEQ_H}, + [RISCV_VICMPTYPE] = {RISCV_INSN_VICMP_VMSNE, RISCV_INSN_VICMP_VMSLEU, + RISCV_INSN_VICMP_VMSLE, RISCV_INSN_VICMP_VMSGTU, + RISCV_INSN_VICMP_VMSGT, RISCV_INSN_VICMP_VMSEQ}, + [RISCV_C_FLW] = {RISCV_INSN_C_FLW}, + [RISCV_C_SWSP] = {RISCV_INSN_C_SWSP}, + [RISCV_FLTQ_D] = {RISCV_INSN_FLTQ_D}, + [RISCV_AES64ES] = {RISCV_INSN_AES64ES}, + [RISCV_C_SRAI_HINT] = {RISCV_INSN_C_SRAI_HINT}, + [RISCV_DIV] = {RISCV_INSN_DIV}, + [RISCV_C_LH] = {RISCV_INSN_C_LH}, + [RISCV_C_NOP_HINT] = {RISCV_INSN_C_NOP_HINT}, + [RISCV_VFIRST_M] = {RISCV_INSN_VFIRST_M}, + [RISCV_MVVMATYPE] = {RISCV_INSN_MVV_VNMSUB, RISCV_INSN_MVV_VNMSAC, + RISCV_INSN_MVV_VMADD, RISCV_INSN_MVV_VMACC}, + [RISCV_FENCEI_RESERVED] = {RISCV_INSN_FENCEI_RESERVED}, + [RISCV_C_ADDI] = {RISCV_INSN_C_ADDI}, + [RISCV_VLOXSEGTYPE] = {RISCV_INSN_VLOXSEGTYPE}, + [RISCV_MUL] = {RISCV_INSN_MUL}, + [RISCV_VMSOF_M] = {RISCV_INSN_VMSOF_M}, + [RISCV_FLEQ_D] = {RISCV_INSN_FLEQ_D}, + [RISCV_VSSSEGTYPE] = {RISCV_INSN_VSSSEGTYPE}, + [RISCV_VXTYPE] = {RISCV_INSN_VX_VXOR, RISCV_INSN_VX_VSUB, + RISCV_INSN_VX_VSSUBU, RISCV_INSN_VX_VSSUB, + RISCV_INSN_VX_VSSRL, RISCV_INSN_VX_VSSRA, + RISCV_INSN_VX_VSRL, RISCV_INSN_VX_VSRA, + RISCV_INSN_VX_VSMUL, RISCV_INSN_VX_VSLL, + RISCV_INSN_VX_VSADDU, RISCV_INSN_VX_VSADD, + RISCV_INSN_VX_VRSUB, RISCV_INSN_VX_VOR, + RISCV_INSN_VX_VMINU, RISCV_INSN_VX_VMIN, + RISCV_INSN_VX_VMAXU, RISCV_INSN_VX_VMAX, + RISCV_INSN_VX_VAND, RISCV_INSN_VX_VADD}, + [RISCV_BTYPE] = {RISCV_INSN_BNE, RISCV_INSN_BLTU, RISCV_INSN_BLT, + RISCV_INSN_BGEU, RISCV_INSN_BGE, RISCV_INSN_BEQ}, + [RISCV_VROR_VX] = {RISCV_INSN_VROR_VX}, + [RISCV_LOAD] = {RISCV_INSN_LOAD}, + [RISCV_VIOTA_M] = {RISCV_INSN_VIOTA_M}, + [RISCV_VROL_VX] = {RISCV_INSN_VROL_VX}, + [RISCV_CLMULR] = {RISCV_INSN_CLMULR}, + [RISCV_VROR_VV] = {RISCV_INSN_VROR_VV}, + [RISCV_VXMSTYPE] = {RISCV_INSN_VXMS_VSBC, RISCV_INSN_VXMS_VADC}, + [RISCV_CLZ] = {RISCV_INSN_CLZ}, + [RISCV_UTYPE] = {RISCV_INSN_LUI, RISCV_INSN_AUIPC}, + [RISCV_CLMULH] = {RISCV_INSN_CLMULH}, + [RISCV_FLI_H] = {RISCV_INSN_FLI_H}, + [RISCV_F_UN_X_TYPE_H] = {RISCV_INSN_FMV_X_H, RISCV_INSN_FCLASS_H}, + [RISCV_F_BIN_RM_TYPE_H] = {RISCV_INSN_FSUB_H, RISCV_INSN_FMUL_H, + RISCV_INSN_FDIV_H, RISCV_INSN_FADD_H}, + [RISCV_VSETVLI] = {RISCV_INSN_VSETVLI}, + [RISCV_C_SEXT_B] = {RISCV_INSN_C_SEXT_B}, + [RISCV_VLUXSEGTYPE] = {RISCV_INSN_VLUXSEGTYPE}, + [RISCV_SHA512SUM1R] = {RISCV_INSN_SHA512SUM1R}, + [RISCV_VITYPE] = {RISCV_INSN_VI_VXOR, RISCV_INSN_VI_VSSRL, + RISCV_INSN_VI_VSSRA, RISCV_INSN_VI_VSRL, + RISCV_INSN_VI_VSRA, RISCV_INSN_VI_VSLL, + RISCV_INSN_VI_VSADDU, RISCV_INSN_VI_VSADD, + RISCV_INSN_VI_VRSUB, RISCV_INSN_VI_VOR, + RISCV_INSN_VI_VAND, RISCV_INSN_VI_VADD}, + [RISCV_STORECON] = {RISCV_INSN_STORECON}, + [RISCV_VMVRTYPE] = {RISCV_INSN_VMVRTYPE}, + [RISCV_ZBKB_RTYPE] = {RISCV_INSN_PACKH, RISCV_INSN_PACK}, + [RISCV_VWSLL_VX] = {RISCV_INSN_VWSLL_VX}, + [RISCV_F_UN_RM_FX_TYPE_H] = {RISCV_INSN_FCVT_W_H, RISCV_INSN_FCVT_WU_H, + RISCV_INSN_FCVT_L_H, RISCV_INSN_FCVT_LU_H}, + [RISCV_VISG] = {RISCV_INSN_VI_VSLIDEUP, RISCV_INSN_VI_VSLIDEDOWN, + RISCV_INSN_VI_VRGATHER}, + [RISCV_VCLMUL_VX] = {RISCV_INSN_VCLMUL_VX}, + [RISCV_C_ADD] = {RISCV_INSN_C_ADD}, + [RISCV_FVFTYPE] = {RISCV_INSN_VF_VSUB, RISCV_INSN_VF_VSLIDE1UP, + RISCV_INSN_VF_VSLIDE1DOWN, RISCV_INSN_VF_VSGNJX, + RISCV_INSN_VF_VSGNJN, RISCV_INSN_VF_VSGNJ, + RISCV_INSN_VF_VRSUB, RISCV_INSN_VF_VRDIV, + RISCV_INSN_VF_VMUL, RISCV_INSN_VF_VMIN, + RISCV_INSN_VF_VMAX, RISCV_INSN_VF_VDIV, + RISCV_INSN_VF_VADD}, + [RISCV_F_UN_RM_FX_TYPE_D] = {RISCV_INSN_FCVT_W_D, RISCV_INSN_FCVT_WU_D, + RISCV_INSN_FCVT_L_D, RISCV_INSN_FCVT_LU_D}, + [RISCV_FENCE_RESERVED] = {RISCV_INSN_FENCE_RESERVED}, + [RISCV_MASKTYPEI] = {RISCV_INSN_MASKTYPEI}, + [RISCV_FVVTYPE] = {RISCV_INSN_FVV_VSUB, RISCV_INSN_FVV_VSGNJX, + RISCV_INSN_FVV_VSGNJN, RISCV_INSN_FVV_VSGNJ, + RISCV_INSN_FVV_VMUL, RISCV_INSN_FVV_VMIN, + RISCV_INSN_FVV_VMAX, RISCV_INSN_FVV_VDIV, + RISCV_INSN_FVV_VADD}, + [RISCV_CPOPW] = {RISCV_INSN_CPOPW}, + [RISCV_C_LI_HINT] = {RISCV_INSN_C_LI_HINT}, + [RISCV_SHA256SUM1] = {RISCV_INSN_SHA256SUM1}, + [RISCV_VSUXSEGTYPE] = {RISCV_INSN_VSUXSEGTYPE}, + [RISCV_VANDN_VX] = {RISCV_INSN_VANDN_VX}, + [RISCV_VCTZ_V] = {RISCV_INSN_VCTZ_V}, + [RISCV_F_UN_RM_XF_TYPE_D] = {RISCV_INSN_FCVT_D_WU, RISCV_INSN_FCVT_D_W, + RISCV_INSN_FCVT_D_LU, RISCV_INSN_FCVT_D_L}, + [RISCV_VIMCTYPE] = {RISCV_INSN_VIMC_VMADC}, + [RISCV_VIMSTYPE] = {RISCV_INSN_VIMS_VADC}, + [RISCV_MASKTYPEV] = {RISCV_INSN_MASKTYPEV}, + [RISCV_THREAD_START] = {RISCV_INSN_THREAD_START}, + [RISCV_FVFMTYPE] = {RISCV_INSN_VFM_VMFNE, RISCV_INSN_VFM_VMFLT, + RISCV_INSN_VFM_VMFLE, RISCV_INSN_VFM_VMFGT, + RISCV_INSN_VFM_VMFGE, RISCV_INSN_VFM_VMFEQ}, + [RISCV_ADDIW] = {RISCV_INSN_ADDIW}, + [RISCV_MRET] = {RISCV_INSN_MRET}, + [RISCV_VLSEGFFTYPE] = {RISCV_INSN_VLSEGFFTYPE}, + [RISCV_C_ANDI] = {RISCV_INSN_C_ANDI}, + [RISCV_WVTYPE] = {RISCV_INSN_WV_VSUBU, RISCV_INSN_WV_VSUB, + RISCV_INSN_WV_VADDU, RISCV_INSN_WV_VADD}, + [RISCV_C_SDSP] = {RISCV_INSN_C_SDSP}, + [RISCV_C_SUBW] = {RISCV_INSN_C_SUBW}, + [RISCV_VEXT4TYPE] = {RISCV_INSN_VEXT4_ZVF4, RISCV_INSN_VEXT4_SVF4}, + [RISCV_VSETVL] = {RISCV_INSN_VSETVL}, + [RISCV_C_SH] = {RISCV_INSN_C_SH}, + [RISCV_MVVCOMPRESS] = {RISCV_INSN_MVVCOMPRESS}, + [RISCV_FWVVTYPE] = {RISCV_INSN_FWVV_VSUB, RISCV_INSN_FWVV_VMUL, + RISCV_INSN_FWVV_VADD}, + [RISCV_VMTYPE] = {RISCV_INSN_VSM, RISCV_INSN_VLM}, + [RISCV_FROUND_H] = {RISCV_INSN_FROUND_H}, + [RISCV_C_JAL] = {RISCV_INSN_C_JAL}, + [RISCV_SFENCE_VMA] = {RISCV_INSN_SFENCE_VMA}, + [RISCV_STOP_FETCHING] = {RISCV_INSN_STOP_FETCHING}, + [RISCV_NVSTYPE] = {RISCV_INSN_NVS_VNSRL, RISCV_INSN_NVS_VNSRA}, + [RISCV_FROUND_S] = {RISCV_INSN_FROUND_S}, + [RISCV_NISTYPE] = {RISCV_INSN_NIS_VNSRL, RISCV_INSN_NIS_VNSRA}, + [RISCV_C_SLLI] = {RISCV_INSN_C_SLLI}, + [RISCV_VXMTYPE] = {RISCV_INSN_VXM_VMSBC, RISCV_INSN_VXM_VMADC}, + [RISCV_FENCEI] = {RISCV_INSN_FENCEI}, + [RISCV_F_UN_F_TYPE_D] = {RISCV_INSN_FMV_D_X}, + [RISCV_VFMVSF] = {RISCV_INSN_VFMVSF}, + [RISCV_VEXT8TYPE] = {RISCV_INSN_VEXT8_ZVF8, RISCV_INSN_VEXT8_SVF8}, + [RISCV_C_OR] = {RISCV_INSN_C_OR}, + [RISCV_FWVFMATYPE] = {RISCV_INSN_FWVF_VNMSAC, RISCV_INSN_FWVF_VNMACC, + RISCV_INSN_FWVF_VMSAC, RISCV_INSN_FWVF_VMACC}, + [RISCV_SHIFTIOP] = {RISCV_INSN_SRLI, RISCV_INSN_SRAI, RISCV_INSN_SLLI}, + [RISCV_DIVW] = {RISCV_INSN_DIVW}, + [RISCV_C_ZEXT_B] = {RISCV_INSN_C_ZEXT_B}, + [RISCV_C_MV] = {RISCV_INSN_C_MV}, + [RISCV_VIMTYPE] = {RISCV_INSN_VIM_VMADC}, + [RISCV_F_UN_RM_FF_TYPE_H] = {RISCV_INSN_FSQRT_H, RISCV_INSN_FCVT_S_H, + RISCV_INSN_FCVT_H_S, RISCV_INSN_FCVT_H_D, + RISCV_INSN_FCVT_D_H}, + [RISCV_LOADRES] = {RISCV_INSN_LOADRES}, + [RISCV_C_J] = {RISCV_INSN_C_J}, + [RISCV_AES32ESI] = {RISCV_INSN_AES32ESI}, + [RISCV_C_BEQZ] = {RISCV_INSN_C_BEQZ}, + [RISCV_SHA512SUM0] = {RISCV_INSN_SHA512SUM0}, + [RISCV_SHA512SUM0R] = {RISCV_INSN_SHA512SUM0R}, + [RISCV_REMW] = {RISCV_INSN_REMW}, + [RISCV_VFMV] = {RISCV_INSN_VFMV}, + [RISCV_C_SEXT_H] = {RISCV_INSN_C_SEXT_H}, + [RISCV_WMVXTYPE] = {RISCV_INSN_WMVX_VWMACCUS, RISCV_INSN_WMVX_VWMACCU, + RISCV_INSN_WMVX_VWMACCSU, RISCV_INSN_WMVX_VWMACC}, + [RISCV_C_FSW] = {RISCV_INSN_C_FSW}, + [RISCV_C_SW] = {RISCV_INSN_C_SW}, + [RISCV_ZBS_RTYPE] = {RISCV_INSN_BSET, RISCV_INSN_BINV, RISCV_INSN_BEXT, + RISCV_INSN_BCLR}, + [RISCV_F_BIN_TYPE_X_S] = {RISCV_INSN_FLT_S, RISCV_INSN_FLE_S, + RISCV_INSN_FEQ_S}, + [RISCV_C_SUB] = {RISCV_INSN_C_SUB}, + [RISCV_VFUNARY0] = {RISCV_INSN_FV_CVT_X_F, RISCV_INSN_FV_CVT_XU_F, + RISCV_INSN_FV_CVT_RTZ_X_F, RISCV_INSN_FV_CVT_RTZ_XU_F, + RISCV_INSN_FV_CVT_F_XU, RISCV_INSN_FV_CVT_F_X}, + [RISCV_FROUNDNX_S] = {RISCV_INSN_FROUNDNX_S}, + [RISCV_ZICBOZ] = {RISCV_INSN_ZICBOZ}, + [RISCV_SFENCE_W_INVAL] = {RISCV_INSN_SFENCE_W_INVAL}, + [RISCV_C_JR] = {RISCV_INSN_C_JR}, + [RISCV_C_NOT] = {RISCV_INSN_C_NOT}, + [RISCV_ZBB_EXTOP] = {RISCV_INSN_ZEXTH, RISCV_INSN_SEXTH, RISCV_INSN_SEXTB}, + [RISCV_MVVTYPE] = {RISCV_INSN_MVV_VREMU, RISCV_INSN_MVV_VREM, + RISCV_INSN_MVV_VMULHU, RISCV_INSN_MVV_VMULHSU, + RISCV_INSN_MVV_VMULH, RISCV_INSN_MVV_VMUL, + RISCV_INSN_MVV_VDIVU, RISCV_INSN_MVV_VDIV, + RISCV_INSN_MVV_VASUBU, RISCV_INSN_MVV_VASUB, + RISCV_INSN_MVV_VAADDU, RISCV_INSN_MVV_VAADD}, + [RISCV_FVFMATYPE] = {RISCV_INSN_VF_VNMSUB, RISCV_INSN_VF_VNMSAC, + RISCV_INSN_VF_VNMADD, RISCV_INSN_VF_VNMACC, + RISCV_INSN_VF_VMSUB, RISCV_INSN_VF_VMSAC, + RISCV_INSN_VF_VMADD, RISCV_INSN_VF_VMACC}, + [RISCV_FMAXM_H] = {RISCV_INSN_FMAXM_H}, + [RISCV_SHA256SUM0] = {RISCV_INSN_SHA256SUM0}, + [RISCV_ZBS_IOP] = {RISCV_INSN_BSETI, RISCV_INSN_BINVI, RISCV_INSN_BEXTI, + RISCV_INSN_BCLRI}, + [RISCV_C_XOR] = {RISCV_INSN_C_XOR}, + [RISCV_ZIMOP_MOP_R] = {RISCV_INSN_ZIMOP_MOP_R}, + [RISCV_FMINM_H] = {RISCV_INSN_FMINM_H}, + [RISCV_C_LUI_HINT] = {RISCV_INSN_C_LUI_HINT}, + [RISCV_VVMCTYPE] = {RISCV_INSN_VVMC_VMSBC, RISCV_INSN_VVMC_VMADC}, + [RISCV_F_UN_RM_XF_TYPE_H] = {RISCV_INSN_FCVT_H_WU, RISCV_INSN_FCVT_H_W, + RISCV_INSN_FCVT_H_LU, RISCV_INSN_FCVT_H_L}, + [RISCV_F_BIN_RM_TYPE_S] = {RISCV_INSN_FSUB_S, RISCV_INSN_FMUL_S, + RISCV_INSN_FDIV_S, RISCV_INSN_FADD_S}, + [RISCV_SINVAL_VMA] = {RISCV_INSN_SINVAL_VMA}, + [RISCV_MOVETYPEX] = {RISCV_INSN_MOVETYPEX}, + [RISCV_VCPOP_V] = {RISCV_INSN_VCPOP_V}, + [RISCV_C_BNEZ] = {RISCV_INSN_C_BNEZ}, + [RISCV_FWVVMATYPE] = {RISCV_INSN_FWVV_VNMSAC, RISCV_INSN_FWVV_VNMACC, + RISCV_INSN_FWVV_VMSAC, RISCV_INSN_FWVV_VMACC}, + [RISCV_AES64KS1I] = {RISCV_INSN_AES64KS1I}, + [RISCV_F_BIN_X_TYPE_D] = {RISCV_INSN_FLT_D, RISCV_INSN_FLE_D, + RISCV_INSN_FEQ_D}, + [RISCV_RMVVTYPE] = {RISCV_INSN_MVV_VREDXOR, RISCV_INSN_MVV_VREDSUM, + RISCV_INSN_MVV_VREDOR, RISCV_INSN_MVV_VREDMINU, + RISCV_INSN_MVV_VREDMIN, RISCV_INSN_MVV_VREDMAXU, + RISCV_INSN_MVV_VREDMAX, RISCV_INSN_MVV_VREDAND}, + [RISCV_F_UN_RM_XF_TYPE_S] = {RISCV_INSN_FCVT_S_WU, RISCV_INSN_FCVT_S_W, + RISCV_INSN_FCVT_S_LU, RISCV_INSN_FCVT_S_L}, + [RISCV_CLZW] = {RISCV_INSN_CLZW}, + [RISCV_REM] = {RISCV_INSN_REM}, + [RISCV_C_EBREAK] = {RISCV_INSN_C_EBREAK}, + [RISCV_AES64ESM] = {RISCV_INSN_AES64ESM}, + [RISCV_VFNUNARY0] = {RISCV_INSN_FNV_CVT_X_F, RISCV_INSN_FNV_CVT_XU_F, + RISCV_INSN_FNV_CVT_RTZ_X_F, + RISCV_INSN_FNV_CVT_RTZ_XU_F, + RISCV_INSN_FNV_CVT_ROD_F_F, RISCV_INSN_FNV_CVT_F_XU, + RISCV_INSN_FNV_CVT_F_X, RISCV_INSN_FNV_CVT_F_F}, + [RISCV_VFWUNARY0] = {RISCV_INSN_FWV_CVT_X_F, RISCV_INSN_FWV_CVT_XU_F, + RISCV_INSN_FWV_CVT_RTZ_X_F, + RISCV_INSN_FWV_CVT_RTZ_XU_F, RISCV_INSN_FWV_CVT_F_XU, + RISCV_INSN_FWV_CVT_F_X, RISCV_INSN_FWV_CVT_F_F}, + [RISCV_MOVETYPEV] = {RISCV_INSN_MOVETYPEV}, + [RISCV_VFUNARY1] = {RISCV_INSN_FVV_VSQRT, RISCV_INSN_FVV_VRSQRT7, + RISCV_INSN_FVV_VREC7, RISCV_INSN_FVV_VCLASS}, + [RISCV_FWVFTYPE] = {RISCV_INSN_FWVF_VSUB, RISCV_INSN_FWVF_VMUL, + RISCV_INSN_FWVF_VADD}, + [RISCV_ZBA_RTYPE] = {RISCV_INSN_SH3ADD, RISCV_INSN_SH2ADD, + RISCV_INSN_SH1ADD}, + [RISCV_C_SRLI] = {RISCV_INSN_C_SRLI}, + [RISCV_VSRETYPE] = {RISCV_INSN_VSRETYPE}, + [RISCV_C_SLLI_HINT] = {RISCV_INSN_C_SLLI_HINT}, + [RISCV_WVVTYPE] = {RISCV_INSN_WVV_VWMULU, RISCV_INSN_WVV_VWMULSU, + RISCV_INSN_WVV_VWMUL, RISCV_INSN_WVV_VSUBU, + RISCV_INSN_WVV_VSUB, RISCV_INSN_WVV_VADDU, + RISCV_INSN_WVV_VADD}, + [RISCV_F_BIN_TYPE_F_S] = {RISCV_INSN_FSGNJ_S, RISCV_INSN_FSGNJX_S, + RISCV_INSN_FSGNJN_S, RISCV_INSN_FMIN_S, + RISCV_INSN_FMAX_S}, + [RISCV_AES64DSM] = {RISCV_INSN_AES64DSM}, + [RISCV_C_LI] = {RISCV_INSN_C_LI}, + [RISCV_F_BIN_X_TYPE_H] = {RISCV_INSN_FLT_H, RISCV_INSN_FLE_H, + RISCV_INSN_FEQ_H}, + [RISCV_C_SRAI] = {RISCV_INSN_C_SRAI}, + [RISCV_F_UN_RM_FF_TYPE_D] = {RISCV_INSN_FSQRT_D, RISCV_INSN_FCVT_S_D, + RISCV_INSN_FCVT_D_S}, + [RISCV_FMVP_D_X] = {RISCV_INSN_FMVP_D_X}, + [RISCV_C_LBU] = {RISCV_INSN_C_LBU}, + [RISCV_RTYPEW] = {RISCV_INSN_SUBW, RISCV_INSN_SRLW, RISCV_INSN_SRAW, + RISCV_INSN_SLLW, RISCV_INSN_ADDW}, + [RISCV_WMVVTYPE] = {RISCV_INSN_WMVV_VWMACCU, RISCV_INSN_WMVV_VWMACCSU, + RISCV_INSN_WMVV_VWMACC}, + [RISCV_MULW] = {RISCV_INSN_MULW}, + [RISCV_VWSLL_VV] = {RISCV_INSN_VWSLL_VV}, + [RISCV_VVCMPTYPE] = {RISCV_INSN_VVCMP_VMSNE, RISCV_INSN_VVCMP_VMSLTU, + RISCV_INSN_VVCMP_VMSLT, RISCV_INSN_VVCMP_VMSLEU, + RISCV_INSN_VVCMP_VMSLE, RISCV_INSN_VVCMP_VMSEQ}, + [RISCV_ILLEGAL] = {RISCV_INSN_ILLEGAL}, + [RISCV_VREV8_V] = {RISCV_INSN_VREV8_V}, + [RISCV_BREV8] = {RISCV_INSN_BREV8}, + [RISCV_VCLMULH_VV] = {RISCV_INSN_VCLMULH_VV}, + [RISCV_AES32DSMI] = {RISCV_INSN_AES32DSMI}, + [RISCV_VANDN_VV] = {RISCV_INSN_VANDN_VV}, + [RISCV_C_FSD] = {RISCV_INSN_C_FSD}, + [RISCV_C_ADDW] = {RISCV_INSN_C_ADDW}, + [RISCV_VCPOP_M] = {RISCV_INSN_VCPOP_M}, + [RISCV_SHA256SIG1] = {RISCV_INSN_SHA256SIG1}, + [RISCV_MVXTYPE] = {RISCV_INSN_MVX_VSLIDE1UP, RISCV_INSN_MVX_VSLIDE1DOWN, + RISCV_INSN_MVX_VREMU, RISCV_INSN_MVX_VREM, + RISCV_INSN_MVX_VMULHU, RISCV_INSN_MVX_VMULHSU, + RISCV_INSN_MVX_VMULH, RISCV_INSN_MVX_VMUL, + RISCV_INSN_MVX_VDIVU, RISCV_INSN_MVX_VDIV, + RISCV_INSN_MVX_VASUBU, RISCV_INSN_MVX_VASUB, + RISCV_INSN_MVX_VAADDU, RISCV_INSN_MVX_VAADD}, +}; +uint16_t get_insn_type(struct ast *tree) { + switch (tree->ast_node_type) { + case RISCV_WXTYPE: + return to_insn[RISCV_WXTYPE][tree->ast_node.wxtype.funct6]; + case RISCV_RTYPE: + return to_insn[RISCV_RTYPE][tree->ast_node.rtype.op]; + case RISCV_RIVVTYPE: + return to_insn[RISCV_RIVVTYPE][tree->ast_node.rivvtype.funct6]; + case RISCV_F_BIN_F_TYPE_H: + return to_insn[RISCV_F_BIN_F_TYPE_H][tree->ast_node.f_bin_f_type_h.fmax_h]; + case RISCV_F_UN_TYPE_F_S: + return to_insn[RISCV_F_UN_TYPE_F_S][tree->ast_node.f_un_type_f_s.fmv_w_x]; + case RISCV_CSRImm: + return to_insn[RISCV_CSRImm][tree->ast_node.csrimm.op]; + case RISCV_VXSG: + return to_insn[RISCV_VXSG][tree->ast_node.vxsg.funct6]; + case RISCV_VXCMPTYPE: + return to_insn[RISCV_VXCMPTYPE][tree->ast_node.vxcmptype.funct6]; + case RISCV_F_UN_RM_FX_TYPE_S: + return to_insn[RISCV_F_UN_RM_FX_TYPE_S] + [tree->ast_node.f_un_rm_fx_type_s.fcvt_lu_s]; + case RISCV_F_UN_X_TYPE_D: + return to_insn[RISCV_F_UN_X_TYPE_D][tree->ast_node.f_un_x_type_d.fmv_x_d]; + case RISCV_ZVKSHA2TYPE: + return to_insn[RISCV_ZVKSHA2TYPE][tree->ast_node.zvksha2type.funct6]; + case RISCV_SHIFTIWOP: + return to_insn[RISCV_SHIFTIWOP][tree->ast_node.shiftiwop.op]; + case RISCV_ZICBOM: + return to_insn[RISCV_ZICBOM][tree->ast_node.riscv_zicbom.cbo_inval]; + case RISCV_NITYPE: + return to_insn[RISCV_NITYPE][tree->ast_node.nitype.funct6]; + case RISCV_VVMTYPE: + return to_insn[RISCV_VVMTYPE][tree->ast_node.vvmtype.funct6]; + case RISCV_MVXMATYPE: + return to_insn[RISCV_MVXMATYPE][tree->ast_node.mvxmatype.funct6]; + case RISCV_FVVMTYPE: + return to_insn[RISCV_FVVMTYPE][tree->ast_node.fvvmtype.funct6]; + case RISCV_F_UN_RM_FF_TYPE_S: + return to_insn[RISCV_F_UN_RM_FF_TYPE_S] + [tree->ast_node.f_un_rm_ff_type_s.fsqrt_s]; + case RISCV_WVXTYPE: + return to_insn[RISCV_WVXTYPE][tree->ast_node.wvxtype.funct6]; + case RISCV_NXSTYPE: + return to_insn[RISCV_NXSTYPE][tree->ast_node.nxstype.funct6]; + case RISCV_VXMCTYPE: + return to_insn[RISCV_VXMCTYPE][tree->ast_node.vxmctype.funct6]; + case RISCV_MMTYPE: + return to_insn[RISCV_MMTYPE][tree->ast_node.mmtype.funct6]; + case RISCV_NVTYPE: + return to_insn[RISCV_NVTYPE][tree->ast_node.nvtype.funct6]; + case RISCV_F_BIN_F_TYPE_D: + return to_insn[RISCV_F_BIN_F_TYPE_D][tree->ast_node.f_bin_f_type_d.fmax_d]; + case RISCV_F_MADD_TYPE_H: + return to_insn[RISCV_F_MADD_TYPE_H][tree->ast_node.f_madd_type_h.op]; + case RISCV_CSRReg: + return to_insn[RISCV_CSRReg][tree->ast_node.csrreg.op]; + case RISCV_ZBA_RTYPEUW: + return to_insn[RISCV_ZBA_RTYPEUW][tree->ast_node.zba_rtypeuw.op]; + case RISCV_F_BIN_RM_TYPE_D: + return to_insn[RISCV_F_BIN_RM_TYPE_D][tree->ast_node.f_bin_rm_type_d.op]; + case RISCV_F_MADD_TYPE_S: + return to_insn[RISCV_F_MADD_TYPE_S][tree->ast_node.f_madd_type_s.op]; + case RISCV_FWFTYPE: + return to_insn[RISCV_FWFTYPE][tree->ast_node.fwftype.funct6]; + case RISCV_FWVTYPE: + return to_insn[RISCV_FWVTYPE][tree->ast_node.fwvtype.funct6]; + case RISCV_ZBB_RTYPE: + return to_insn[RISCV_ZBB_RTYPE][tree->ast_node.zbb_rtype.op]; + case RISCV_F_UN_TYPE_X_S: + return to_insn[RISCV_F_UN_TYPE_X_S][tree->ast_node.f_un_type_x_s.fmv_x_w]; + case RISCV_NXTYPE: + return to_insn[RISCV_NXTYPE][tree->ast_node.nxtype.funct6]; + case RISCV_ITYPE: + return to_insn[RISCV_ITYPE][tree->ast_node.itype.op]; + case RISCV_F_UN_F_TYPE_H: + return to_insn[RISCV_F_UN_F_TYPE_H][tree->ast_node.f_un_f_type_h.fmv_h_x]; + case RISCV_ZICOND_RTYPE: + return to_insn[RISCV_ZICOND_RTYPE] + [tree->ast_node.zicond_rtype.riscv_czero_nez]; + case RISCV_ZBB_RTYPEW: + return to_insn[RISCV_ZBB_RTYPEW][tree->ast_node.zbb_rtypew.op]; + case RISCV_RFVVTYPE: + return to_insn[RISCV_RFVVTYPE][tree->ast_node.rfvvtype.funct6]; + case RISCV_AMO: + return to_insn[RISCV_AMO][tree->ast_node.amo.op]; + case RISCV_VVMSTYPE: + return to_insn[RISCV_VVMSTYPE][tree->ast_node.vvmstype.funct6]; + case RISCV_FVVMATYPE: + return to_insn[RISCV_FVVMATYPE][tree->ast_node.fvvmatype.funct6]; + case RISCV_VEXT2TYPE: + return to_insn[RISCV_VEXT2TYPE][tree->ast_node.vext2type.funct6]; + case RISCV_F_MADD_TYPE_D: + return to_insn[RISCV_F_MADD_TYPE_D][tree->ast_node.f_madd_type_d.op]; + case RISCV_VVTYPE: + return to_insn[RISCV_VVTYPE][tree->ast_node.vvtype.funct6]; + case RISCV_VICMPTYPE: + return to_insn[RISCV_VICMPTYPE][tree->ast_node.vicmptype.funct6]; + case RISCV_MVVMATYPE: + return to_insn[RISCV_MVVMATYPE][tree->ast_node.mvvmatype.funct6]; + case RISCV_VXTYPE: + return to_insn[RISCV_VXTYPE][tree->ast_node.vxtype.funct6]; + case RISCV_BTYPE: + return to_insn[RISCV_BTYPE][tree->ast_node.btype.op]; + case RISCV_VXMSTYPE: + return to_insn[RISCV_VXMSTYPE][tree->ast_node.vxmstype.funct6]; + case RISCV_UTYPE: + return to_insn[RISCV_UTYPE][tree->ast_node.utype.op]; + case RISCV_F_UN_X_TYPE_H: + return to_insn[RISCV_F_UN_X_TYPE_H][tree->ast_node.f_un_x_type_h.fmv_x_h]; + case RISCV_F_BIN_RM_TYPE_H: + return to_insn[RISCV_F_BIN_RM_TYPE_H][tree->ast_node.f_bin_rm_type_h.op]; + case RISCV_VITYPE: + return to_insn[RISCV_VITYPE][tree->ast_node.vitype.funct6]; + case RISCV_ZBKB_RTYPE: + return to_insn[RISCV_ZBKB_RTYPE][tree->ast_node.zbkb_rtype.op]; + case RISCV_F_UN_RM_FX_TYPE_H: + return to_insn[RISCV_F_UN_RM_FX_TYPE_H] + [tree->ast_node.f_un_rm_fx_type_h.fcvt_lu_h]; + case RISCV_VISG: + return to_insn[RISCV_VISG][tree->ast_node.visg.funct6]; + case RISCV_FVFTYPE: + return to_insn[RISCV_FVFTYPE][tree->ast_node.fvftype.funct6]; + case RISCV_F_UN_RM_FX_TYPE_D: + return to_insn[RISCV_F_UN_RM_FX_TYPE_D] + [tree->ast_node.f_un_rm_fx_type_d.fcvt_lu_d]; + case RISCV_FVVTYPE: + return to_insn[RISCV_FVVTYPE][tree->ast_node.fvvtype.funct6]; + case RISCV_F_UN_RM_XF_TYPE_D: + return to_insn[RISCV_F_UN_RM_XF_TYPE_D] + [tree->ast_node.f_un_rm_xf_type_d.fcvt_d_lu]; + case RISCV_VIMCTYPE: + return to_insn[RISCV_VIMCTYPE][tree->ast_node.vimctype.funct6]; + case RISCV_VIMSTYPE: + return to_insn[RISCV_VIMSTYPE][tree->ast_node.vimstype.funct6]; + case RISCV_FVFMTYPE: + return to_insn[RISCV_FVFMTYPE][tree->ast_node.fvfmtype.funct6]; + case RISCV_WVTYPE: + return to_insn[RISCV_WVTYPE][tree->ast_node.wvtype.funct6]; + case RISCV_VEXT4TYPE: + return to_insn[RISCV_VEXT4TYPE][tree->ast_node.vext4type.funct6]; + case RISCV_FWVVTYPE: + return to_insn[RISCV_FWVVTYPE][tree->ast_node.fwvvtype.funct6]; + case RISCV_VMTYPE: + return to_insn[RISCV_VMTYPE][tree->ast_node.vmtype.op]; + case RISCV_NVSTYPE: + return to_insn[RISCV_NVSTYPE][tree->ast_node.nvstype.funct6]; + case RISCV_NISTYPE: + return to_insn[RISCV_NISTYPE][tree->ast_node.nistype.funct6]; + case RISCV_VXMTYPE: + return to_insn[RISCV_VXMTYPE][tree->ast_node.vxmtype.funct6]; + case RISCV_F_UN_F_TYPE_D: + return to_insn[RISCV_F_UN_F_TYPE_D][tree->ast_node.f_un_f_type_d.fmv_d_x]; + case RISCV_VEXT8TYPE: + return to_insn[RISCV_VEXT8TYPE][tree->ast_node.vext8type.funct6]; + case RISCV_FWVFMATYPE: + return to_insn[RISCV_FWVFMATYPE][tree->ast_node.fwvfmatype.funct6]; + case RISCV_SHIFTIOP: + return to_insn[RISCV_SHIFTIOP][tree->ast_node.shiftiop.op]; + case RISCV_VIMTYPE: + return to_insn[RISCV_VIMTYPE][tree->ast_node.vimtype.funct6]; + case RISCV_F_UN_RM_FF_TYPE_H: + return to_insn[RISCV_F_UN_RM_FF_TYPE_H] + [tree->ast_node.f_un_rm_ff_type_h.fcvt_d_h]; + case RISCV_WMVXTYPE: + return to_insn[RISCV_WMVXTYPE][tree->ast_node.wmvxtype.funct6]; + case RISCV_ZBS_RTYPE: + return to_insn[RISCV_ZBS_RTYPE][tree->ast_node.zbs_rtype.op]; + case RISCV_F_BIN_TYPE_X_S: + return to_insn[RISCV_F_BIN_TYPE_X_S][tree->ast_node.f_bin_type_x_s.fle_s]; + case RISCV_VFUNARY0: + return to_insn[RISCV_VFUNARY0][tree->ast_node.vfunary0.vfunary0]; + case RISCV_ZBB_EXTOP: + return to_insn[RISCV_ZBB_EXTOP][tree->ast_node.zbb_extop.op]; + case RISCV_MVVTYPE: + return to_insn[RISCV_MVVTYPE][tree->ast_node.mvvtype.funct6]; + case RISCV_FVFMATYPE: + return to_insn[RISCV_FVFMATYPE][tree->ast_node.fvfmatype.funct6]; + case RISCV_ZBS_IOP: + return to_insn[RISCV_ZBS_IOP][tree->ast_node.zbs_iop.op]; + case RISCV_VVMCTYPE: + return to_insn[RISCV_VVMCTYPE][tree->ast_node.vvmctype.funct6]; + case RISCV_F_UN_RM_XF_TYPE_H: + return to_insn[RISCV_F_UN_RM_XF_TYPE_H] + [tree->ast_node.f_un_rm_xf_type_h.fcvt_h_lu]; + case RISCV_F_BIN_RM_TYPE_S: + return to_insn[RISCV_F_BIN_RM_TYPE_S][tree->ast_node.f_bin_rm_type_s.op]; + case RISCV_FWVVMATYPE: + return to_insn[RISCV_FWVVMATYPE][tree->ast_node.fwvvmatype.funct6]; + case RISCV_F_BIN_X_TYPE_D: + return to_insn[RISCV_F_BIN_X_TYPE_D][tree->ast_node.f_bin_x_type_d.fle_d]; + case RISCV_RMVVTYPE: + return to_insn[RISCV_RMVVTYPE][tree->ast_node.rmvvtype.funct6]; + case RISCV_F_UN_RM_XF_TYPE_S: + return to_insn[RISCV_F_UN_RM_XF_TYPE_S] + [tree->ast_node.f_un_rm_xf_type_s.fcvt_s_lu]; + case RISCV_VFNUNARY0: + return to_insn[RISCV_VFNUNARY0][tree->ast_node.vfnunary0.vfnunary0]; + case RISCV_VFWUNARY0: + return to_insn[RISCV_VFWUNARY0][tree->ast_node.vfwunary0.vfwunary0]; + case RISCV_VFUNARY1: + return to_insn[RISCV_VFUNARY1][tree->ast_node.vfunary1.vfunary1]; + case RISCV_FWVFTYPE: + return to_insn[RISCV_FWVFTYPE][tree->ast_node.fwvftype.funct6]; + case RISCV_ZBA_RTYPE: + return to_insn[RISCV_ZBA_RTYPE][tree->ast_node.zba_rtype.op]; + case RISCV_WVVTYPE: + return to_insn[RISCV_WVVTYPE][tree->ast_node.wvvtype.funct6]; + case RISCV_F_BIN_TYPE_F_S: + return to_insn[RISCV_F_BIN_TYPE_F_S][tree->ast_node.f_bin_type_f_s.fmax_s]; + case RISCV_F_BIN_X_TYPE_H: + return to_insn[RISCV_F_BIN_X_TYPE_H][tree->ast_node.f_bin_x_type_h.fle_h]; + case RISCV_F_UN_RM_FF_TYPE_D: + return to_insn[RISCV_F_UN_RM_FF_TYPE_D] + [tree->ast_node.f_un_rm_ff_type_d.fcvt_d_s]; + case RISCV_RTYPEW: + return to_insn[RISCV_RTYPEW][tree->ast_node.rtypew.op]; + case RISCV_WMVVTYPE: + return to_insn[RISCV_WMVVTYPE][tree->ast_node.wmvvtype.funct6]; + case RISCV_VVCMPTYPE: + return to_insn[RISCV_VVCMPTYPE][tree->ast_node.vvcmptype.funct6]; + case RISCV_MVXTYPE: + return to_insn[RISCV_MVXTYPE][tree->ast_node.mvxtype.funct6]; + default: + return to_insn[tree->ast_node_type][0]; + } +} +#endif diff --git a/arch/RISCV/RISCVInstPrinter.c b/arch/RISCV/RISCVInstPrinter.c deleted file mode 100644 index feb7e3d74b..0000000000 --- a/arch/RISCV/RISCVInstPrinter.c +++ /dev/null @@ -1,591 +0,0 @@ -//===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This class prints an RISCV MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifdef CAPSTONE_HAS_RISCV - -#include // DEBUG -#include -#include -#include - -#include "RISCVInstPrinter.h" -#include "RISCVBaseInfo.h" -#include "../../MCInst.h" -#include "../../SStream.h" -#include "../../MCRegisterInfo.h" -#include "../../utils.h" -#include "../../Mapping.h" -#include "RISCVMapping.h" - -//#include "RISCVDisassembler.h" - -#define GET_REGINFO_ENUM -#define GET_REGINFO_MC_DESC -#include "RISCVGenRegisterInfo.inc" -#define GET_INSTRINFO_ENUM -#include "RISCVGenInstrInfo.inc" - -// Autogenerated by tblgen. -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); -static bool printAliasInstr(MCInst *MI, SStream *OS, void *info); -static void printOperand(MCInst *MI, unsigned OpNo, SStream *O); -static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O); -static void printCSRSystemRegister(MCInst*, unsigned, SStream *); -static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O); -static void printCustomAliasOperand( MCInst *, unsigned, unsigned, SStream *); -/// getRegisterName - This method is automatically generated by tblgen -/// from the register set description. This returns the assembler name -/// for the specified register. -static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); - -// Include the auto-generated portion of the assembly writer. -#define PRINT_ALIAS_INSTR -#include "RISCVGenAsmWriter.inc" - - -static void fixDetailOfEffectiveAddr(MCInst *MI) -{ - // Operands for load and store instructions in RISCV vary widely - unsigned id = MI->flat_insn->id; - unsigned reg = 0; - int64_t imm = 0; - uint8_t access = 0; - - switch (id) { - case RISCV_INS_C_FLD: - case RISCV_INS_C_LW: - case RISCV_INS_C_FLW: - case RISCV_INS_C_LD: - case RISCV_INS_C_FSD: - case RISCV_INS_C_SW: - case RISCV_INS_C_FSW: - case RISCV_INS_C_SD: - case RISCV_INS_C_FLDSP: - case RISCV_INS_C_LWSP: - case RISCV_INS_C_FLWSP: - case RISCV_INS_C_LDSP: - case RISCV_INS_C_FSDSP: - case RISCV_INS_C_SWSP: - case RISCV_INS_C_FSWSP: - case RISCV_INS_C_SDSP: - case RISCV_INS_FLW: - case RISCV_INS_FSW: - case RISCV_INS_FLD: - case RISCV_INS_FSD: - case RISCV_INS_LB: - case RISCV_INS_LBU: - case RISCV_INS_LD: - case RISCV_INS_LH: - case RISCV_INS_LHU: - case RISCV_INS_LW: - case RISCV_INS_LWU: - case RISCV_INS_SB: - case RISCV_INS_SD: - case RISCV_INS_SH: - case RISCV_INS_SW: { - CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); - CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -3)->type); - CS_ASSERT(RISCV_OP_IMM == RISCV_get_detail_op(MI, -2)->type); - CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); - - imm = RISCV_get_detail_op(MI, -2)->imm; - reg = RISCV_get_detail_op(MI, -1)->reg; - access = RISCV_get_detail_op(MI, -1)->access; - - RISCV_get_detail_op(MI, -2)->type = RISCV_OP_MEM; - RISCV_get_detail_op(MI, -2)->mem.base = reg; - RISCV_get_detail_op(MI, -2)->mem.disp = imm; - RISCV_get_detail_op(MI, -2)->access = access; - - RISCV_dec_op_count(MI); - - break; - } - case RISCV_INS_LR_W: - case RISCV_INS_LR_W_AQ: - case RISCV_INS_LR_W_AQ_RL: - case RISCV_INS_LR_W_RL: - case RISCV_INS_LR_D: - case RISCV_INS_LR_D_AQ: - case RISCV_INS_LR_D_AQ_RL: - case RISCV_INS_LR_D_RL: { - CS_ASSERT(2 == MI->flat_insn->detail->riscv.op_count); - CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); - CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -2)->type); - - reg = RISCV_get_detail_op(MI, -1)->reg; - - RISCV_get_detail_op(MI, -1)->type = RISCV_OP_MEM; - RISCV_get_detail_op(MI, -1)->mem.base = reg; - RISCV_get_detail_op(MI, -1)->mem.disp = 0; - - break; - } - case RISCV_INS_SC_W: - case RISCV_INS_SC_W_AQ: - case RISCV_INS_SC_W_AQ_RL: - case RISCV_INS_SC_W_RL: - case RISCV_INS_SC_D: - case RISCV_INS_SC_D_AQ: - case RISCV_INS_SC_D_AQ_RL: - case RISCV_INS_SC_D_RL: - case RISCV_INS_AMOADD_D: - case RISCV_INS_AMOADD_D_AQ: - case RISCV_INS_AMOADD_D_AQ_RL: - case RISCV_INS_AMOADD_D_RL: - case RISCV_INS_AMOADD_W: - case RISCV_INS_AMOADD_W_AQ: - case RISCV_INS_AMOADD_W_AQ_RL: - case RISCV_INS_AMOADD_W_RL: - case RISCV_INS_AMOAND_D: - case RISCV_INS_AMOAND_D_AQ: - case RISCV_INS_AMOAND_D_AQ_RL: - case RISCV_INS_AMOAND_D_RL: - case RISCV_INS_AMOAND_W: - case RISCV_INS_AMOAND_W_AQ: - case RISCV_INS_AMOAND_W_AQ_RL: - case RISCV_INS_AMOAND_W_RL: - case RISCV_INS_AMOMAXU_D: - case RISCV_INS_AMOMAXU_D_AQ: - case RISCV_INS_AMOMAXU_D_AQ_RL: - case RISCV_INS_AMOMAXU_D_RL: - case RISCV_INS_AMOMAXU_W: - case RISCV_INS_AMOMAXU_W_AQ: - case RISCV_INS_AMOMAXU_W_AQ_RL: - case RISCV_INS_AMOMAXU_W_RL: - case RISCV_INS_AMOMAX_D: - case RISCV_INS_AMOMAX_D_AQ: - case RISCV_INS_AMOMAX_D_AQ_RL: - case RISCV_INS_AMOMAX_D_RL: - case RISCV_INS_AMOMAX_W: - case RISCV_INS_AMOMAX_W_AQ: - case RISCV_INS_AMOMAX_W_AQ_RL: - case RISCV_INS_AMOMAX_W_RL: - case RISCV_INS_AMOMINU_D: - case RISCV_INS_AMOMINU_D_AQ: - case RISCV_INS_AMOMINU_D_AQ_RL: - case RISCV_INS_AMOMINU_D_RL: - case RISCV_INS_AMOMINU_W: - case RISCV_INS_AMOMINU_W_AQ: - case RISCV_INS_AMOMINU_W_AQ_RL: - case RISCV_INS_AMOMINU_W_RL: - case RISCV_INS_AMOMIN_D: - case RISCV_INS_AMOMIN_D_AQ: - case RISCV_INS_AMOMIN_D_AQ_RL: - case RISCV_INS_AMOMIN_D_RL: - case RISCV_INS_AMOMIN_W: - case RISCV_INS_AMOMIN_W_AQ: - case RISCV_INS_AMOMIN_W_AQ_RL: - case RISCV_INS_AMOMIN_W_RL: - case RISCV_INS_AMOOR_D: - case RISCV_INS_AMOOR_D_AQ: - case RISCV_INS_AMOOR_D_AQ_RL: - case RISCV_INS_AMOOR_D_RL: - case RISCV_INS_AMOOR_W: - case RISCV_INS_AMOOR_W_AQ: - case RISCV_INS_AMOOR_W_AQ_RL: - case RISCV_INS_AMOOR_W_RL: - case RISCV_INS_AMOSWAP_D: - case RISCV_INS_AMOSWAP_D_AQ: - case RISCV_INS_AMOSWAP_D_AQ_RL: - case RISCV_INS_AMOSWAP_D_RL: - case RISCV_INS_AMOSWAP_W: - case RISCV_INS_AMOSWAP_W_AQ: - case RISCV_INS_AMOSWAP_W_AQ_RL: - case RISCV_INS_AMOSWAP_W_RL: - case RISCV_INS_AMOXOR_D: - case RISCV_INS_AMOXOR_D_AQ: - case RISCV_INS_AMOXOR_D_AQ_RL: - case RISCV_INS_AMOXOR_D_RL: - case RISCV_INS_AMOXOR_W: - case RISCV_INS_AMOXOR_W_AQ: - case RISCV_INS_AMOXOR_W_AQ_RL: - case RISCV_INS_AMOXOR_W_RL: { - CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); - CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -3)->type); - CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -2)->type); - CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type); - - reg = RISCV_get_detail_op(MI, -1)->reg; - - RISCV_get_detail_op(MI, -1)->type = RISCV_OP_MEM; - RISCV_get_detail_op(MI, -1)->mem.base = reg; - RISCV_get_detail_op(MI, -1)->mem.disp = 0; - - break; - } - default: { - CS_ASSERT(0 && "id is not a RISC-V memory instruction"); - break; - } - } - return; -} - - -//void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O, -// StringRef Annot, const MCSubtargetInfo &STI) -void RISCV_printInst(MCInst *MI, SStream *O, void *info) -{ - MCRegisterInfo *MRI = (MCRegisterInfo *) info; - //bool Res = false; - //MCInst *NewMI = MI; - // TODO: RISCV compressd instructions. - //MCInst UncompressedMI; - //if (!NoAliases) - //Res = uncompressInst(UncompressedMI, *MI, MRI, STI); - //if (Res) - //NewMI = const_cast(&UncompressedMI); - if (/*NoAliases ||*/ !printAliasInstr(MI, O, info)) - printInstruction(MI, O, MRI); - //printAnnotation(O, Annot); - // fix load/store type insttuction - if (MI->csh->detail_opt && - MI->flat_insn->detail->riscv.need_effective_addr) - fixDetailOfEffectiveAddr(MI); - - return; -} - -static void printRegName(SStream *OS, unsigned RegNo) -{ - SStream_concat0(OS, getRegisterName(RegNo, RISCV_ABIRegAltName)); -} - -/** -void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O, const char *Modifier) -*/ -static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned reg; - int64_t Imm = 0; - - RISCV_add_cs_detail(MI, OpNo); - - MCOperand *MO = MCInst_getOperand(MI, OpNo); - - if (MCOperand_isReg(MO)) { - reg = MCOperand_getReg(MO); - printRegName(O, reg); - } else { - CS_ASSERT(MCOperand_isImm(MO) && "Unknown operand kind in printOperand"); - Imm = MCOperand_getImm(MO); - if (Imm >= 0) { - if (Imm > HEX_THRESHOLD) - SStream_concat(O, "0x%" PRIx64, Imm); - else - SStream_concat(O, "%" PRIu64, Imm); - } else { - if (Imm < -HEX_THRESHOLD) - SStream_concat(O, "-0x%" PRIx64, -Imm); - else - SStream_concat(O, "-%" PRIu64, -Imm); - } - } - - //CS_ASSERT(MO.isExpr() && "Unknown operand kind in printOperand"); - - return; -} - -static const char *getCSRSystemRegisterName(unsigned CsrNo) -{ - switch (CsrNo) { - /* - * From RISC-V Privileged Architecture Version 1.10. - * In the same order as Table 2.5. - */ - case 0x0000: return "ustatus"; - case 0x0004: return "uie"; - case 0x0005: return "utvec"; - - case 0x0040: return "uscratch"; - case 0x0041: return "uepc"; - case 0x0042: return "ucause"; - case 0x0043: return "utval"; - case 0x0044: return "uip"; - - case 0x0001: return "fflags"; - case 0x0002: return "frm"; - case 0x0003: return "fcsr"; - - case 0x0c00: return "cycle"; - case 0x0c01: return "time"; - case 0x0c02: return "instret"; - case 0x0c03: return "hpmcounter3"; - case 0x0c04: return "hpmcounter4"; - case 0x0c05: return "hpmcounter5"; - case 0x0c06: return "hpmcounter6"; - case 0x0c07: return "hpmcounter7"; - case 0x0c08: return "hpmcounter8"; - case 0x0c09: return "hpmcounter9"; - case 0x0c0a: return "hpmcounter10"; - case 0x0c0b: return "hpmcounter11"; - case 0x0c0c: return "hpmcounter12"; - case 0x0c0d: return "hpmcounter13"; - case 0x0c0e: return "hpmcounter14"; - case 0x0c0f: return "hpmcounter15"; - case 0x0c10: return "hpmcounter16"; - case 0x0c11: return "hpmcounter17"; - case 0x0c12: return "hpmcounter18"; - case 0x0c13: return "hpmcounter19"; - case 0x0c14: return "hpmcounter20"; - case 0x0c15: return "hpmcounter21"; - case 0x0c16: return "hpmcounter22"; - case 0x0c17: return "hpmcounter23"; - case 0x0c18: return "hpmcounter24"; - case 0x0c19: return "hpmcounter25"; - case 0x0c1a: return "hpmcounter26"; - case 0x0c1b: return "hpmcounter27"; - case 0x0c1c: return "hpmcounter28"; - case 0x0c1d: return "hpmcounter29"; - case 0x0c1e: return "hpmcounter30"; - case 0x0c1f: return "hpmcounter31"; - case 0x0c80: return "cycleh"; - case 0x0c81: return "timeh"; - case 0x0c82: return "instreth"; - case 0x0c83: return "hpmcounter3h"; - case 0x0c84: return "hpmcounter4h"; - case 0x0c85: return "hpmcounter5h"; - case 0x0c86: return "hpmcounter6h"; - case 0x0c87: return "hpmcounter7h"; - case 0x0c88: return "hpmcounter8h"; - case 0x0c89: return "hpmcounter9h"; - case 0x0c8a: return "hpmcounter10h"; - case 0x0c8b: return "hpmcounter11h"; - case 0x0c8c: return "hpmcounter12h"; - case 0x0c8d: return "hpmcounter13h"; - case 0x0c8e: return "hpmcounter14h"; - case 0x0c8f: return "hpmcounter15h"; - case 0x0c90: return "hpmcounter16h"; - case 0x0c91: return "hpmcounter17h"; - case 0x0c92: return "hpmcounter18h"; - case 0x0c93: return "hpmcounter19h"; - case 0x0c94: return "hpmcounter20h"; - case 0x0c95: return "hpmcounter21h"; - case 0x0c96: return "hpmcounter22h"; - case 0x0c97: return "hpmcounter23h"; - case 0x0c98: return "hpmcounter24h"; - case 0x0c99: return "hpmcounter25h"; - case 0x0c9a: return "hpmcounter26h"; - case 0x0c9b: return "hpmcounter27h"; - case 0x0c9c: return "hpmcounter28h"; - case 0x0c9d: return "hpmcounter29h"; - case 0x0c9e: return "hpmcounter30h"; - case 0x0c9f: return "hpmcounter31h"; - - case 0x0100: return "sstatus"; - case 0x0102: return "sedeleg"; - case 0x0103: return "sideleg"; - case 0x0104: return "sie"; - case 0x0105: return "stvec"; - case 0x0106: return "scounteren"; - - case 0x0140: return "sscratch"; - case 0x0141: return "sepc"; - case 0x0142: return "scause"; - case 0x0143: return "stval"; - case 0x0144: return "sip"; - - case 0x0180: return "satp"; - - case 0x0f11: return "mvendorid"; - case 0x0f12: return "marchid"; - case 0x0f13: return "mimpid"; - case 0x0f14: return "mhartid"; - - case 0x0300: return "mstatus"; - case 0x0301: return "misa"; - case 0x0302: return "medeleg"; - case 0x0303: return "mideleg"; - case 0x0304: return "mie"; - case 0x0305: return "mtvec"; - case 0x0306: return "mcounteren"; - - case 0x0340: return "mscratch"; - case 0x0341: return "mepc"; - case 0x0342: return "mcause"; - case 0x0343: return "mtval"; - case 0x0344: return "mip"; - - case 0x03a0: return "pmpcfg0"; - case 0x03a1: return "pmpcfg1"; - case 0x03a2: return "pmpcfg2"; - case 0x03a3: return "pmpcfg3"; - case 0x03b0: return "pmpaddr0"; - case 0x03b1: return "pmpaddr1"; - case 0x03b2: return "pmpaddr2"; - case 0x03b3: return "pmpaddr3"; - case 0x03b4: return "pmpaddr4"; - case 0x03b5: return "pmpaddr5"; - case 0x03b6: return "pmpaddr6"; - case 0x03b7: return "pmpaddr7"; - case 0x03b8: return "pmpaddr8"; - case 0x03b9: return "pmpaddr9"; - case 0x03ba: return "pmpaddr10"; - case 0x03bb: return "pmpaddr11"; - case 0x03bc: return "pmpaddr12"; - case 0x03bd: return "pmpaddr13"; - case 0x03be: return "pmpaddr14"; - case 0x03bf: return "pmpaddr15"; - - case 0x0b00: return "mcycle"; - case 0x0b02: return "minstret"; - case 0x0b03: return "mhpmcounter3"; - case 0x0b04: return "mhpmcounter4"; - case 0x0b05: return "mhpmcounter5"; - case 0x0b06: return "mhpmcounter6"; - case 0x0b07: return "mhpmcounter7"; - case 0x0b08: return "mhpmcounter8"; - case 0x0b09: return "mhpmcounter9"; - case 0x0b0a: return "mhpmcounter10"; - case 0x0b0b: return "mhpmcounter11"; - case 0x0b0c: return "mhpmcounter12"; - case 0x0b0d: return "mhpmcounter13"; - case 0x0b0e: return "mhpmcounter14"; - case 0x0b0f: return "mhpmcounter15"; - case 0x0b10: return "mhpmcounter16"; - case 0x0b11: return "mhpmcounter17"; - case 0x0b12: return "mhpmcounter18"; - case 0x0b13: return "mhpmcounter19"; - case 0x0b14: return "mhpmcounter20"; - case 0x0b15: return "mhpmcounter21"; - case 0x0b16: return "mhpmcounter22"; - case 0x0b17: return "mhpmcounter23"; - case 0x0b18: return "mhpmcounter24"; - case 0x0b19: return "mhpmcounter25"; - case 0x0b1a: return "mhpmcounter26"; - case 0x0b1b: return "mhpmcounter27"; - case 0x0b1c: return "mhpmcounter28"; - case 0x0b1d: return "mhpmcounter29"; - case 0x0b1e: return "mhpmcounter30"; - case 0x0b1f: return "mhpmcounter31"; - case 0x0b80: return "mcycleh"; - case 0x0b82: return "minstreth"; - case 0x0b83: return "mhpmcounter3h"; - case 0x0b84: return "mhpmcounter4h"; - case 0x0b85: return "mhpmcounter5h"; - case 0x0b86: return "mhpmcounter6h"; - case 0x0b87: return "mhpmcounter7h"; - case 0x0b88: return "mhpmcounter8h"; - case 0x0b89: return "mhpmcounter9h"; - case 0x0b8a: return "mhpmcounter10h"; - case 0x0b8b: return "mhpmcounter11h"; - case 0x0b8c: return "mhpmcounter12h"; - case 0x0b8d: return "mhpmcounter13h"; - case 0x0b8e: return "mhpmcounter14h"; - case 0x0b8f: return "mhpmcounter15h"; - case 0x0b90: return "mhpmcounter16h"; - case 0x0b91: return "mhpmcounter17h"; - case 0x0b92: return "mhpmcounter18h"; - case 0x0b93: return "mhpmcounter19h"; - case 0x0b94: return "mhpmcounter20h"; - case 0x0b95: return "mhpmcounter21h"; - case 0x0b96: return "mhpmcounter22h"; - case 0x0b97: return "mhpmcounter23h"; - case 0x0b98: return "mhpmcounter24h"; - case 0x0b99: return "mhpmcounter25h"; - case 0x0b9a: return "mhpmcounter26h"; - case 0x0b9b: return "mhpmcounter27h"; - case 0x0b9c: return "mhpmcounter28h"; - case 0x0b9d: return "mhpmcounter29h"; - case 0x0b9e: return "mhpmcounter30h"; - case 0x0b9f: return "mhpmcounter31h"; - - case 0x0323: return "mhpmevent3"; - case 0x0324: return "mhpmevent4"; - case 0x0325: return "mhpmevent5"; - case 0x0326: return "mhpmevent6"; - case 0x0327: return "mhpmevent7"; - case 0x0328: return "mhpmevent8"; - case 0x0329: return "mhpmevent9"; - case 0x032a: return "mhpmevent10"; - case 0x032b: return "mhpmevent11"; - case 0x032c: return "mhpmevent12"; - case 0x032d: return "mhpmevent13"; - case 0x032e: return "mhpmevent14"; - case 0x032f: return "mhpmevent15"; - case 0x0330: return "mhpmevent16"; - case 0x0331: return "mhpmevent17"; - case 0x0332: return "mhpmevent18"; - case 0x0333: return "mhpmevent19"; - case 0x0334: return "mhpmevent20"; - case 0x0335: return "mhpmevent21"; - case 0x0336: return "mhpmevent22"; - case 0x0337: return "mhpmevent23"; - case 0x0338: return "mhpmevent24"; - case 0x0339: return "mhpmevent25"; - case 0x033a: return "mhpmevent26"; - case 0x033b: return "mhpmevent27"; - case 0x033c: return "mhpmevent28"; - case 0x033d: return "mhpmevent29"; - case 0x033e: return "mhpmevent30"; - case 0x033f: return "mhpmevent31"; - - case 0x07a0: return "tselect"; - case 0x07a1: return "tdata1"; - case 0x07a2: return "tdata2"; - case 0x07a3: return "tdata3"; - - case 0x07b0: return "dcsr"; - case 0x07b1: return "dpc"; - case 0x07b2: return "dscratch"; - } - return NULL; -} - -static void printCSRSystemRegister(MCInst *MI, unsigned OpNo, - //const MCSubtargetInfo &STI, - SStream *O) -{ - unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - const char *Name = getCSRSystemRegisterName(Imm); - - if (Name) { - SStream_concat0(O, Name); - } else { - SStream_concat(O, "%u", Imm); - } -} - -static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O) -{ - unsigned FenceArg = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //CS_ASSERT (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); - - if ((FenceArg & RISCVFenceField_I) != 0) - SStream_concat0(O, "i"); - if ((FenceArg & RISCVFenceField_O) != 0) - SStream_concat0(O, "o"); - if ((FenceArg & RISCVFenceField_R) != 0) - SStream_concat0(O, "r"); - if ((FenceArg & RISCVFenceField_W) != 0) - SStream_concat0(O, "w"); - if (FenceArg == 0) - SStream_concat0(O, "unknown"); -} - -static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O) -{ - enum RoundingMode FRMArg = - (enum RoundingMode)MCOperand_getImm(MCInst_getOperand(MI, OpNo)); -#if 0 - auto FRMArg = - static_cast(MI->getOperand(OpNo).getImm()); - O << RISCVFPRndMode::roundingModeToString(FRMArg); -#endif - SStream_concat0(O, roundingModeToString(FRMArg)); -} - -#endif // CAPSTONE_HAS_RISCV diff --git a/arch/RISCV/RISCVInstPrinter.h b/arch/RISCV/RISCVInstPrinter.h deleted file mode 100644 index 466c3f86db..0000000000 --- a/arch/RISCV/RISCVInstPrinter.h +++ /dev/null @@ -1,24 +0,0 @@ -//===-- RISCVInstPrinter.h - Convert RISCV MCInst to asm syntax ---*- C++ -*--// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This class prints a RISCV MCInst to a .s file. -// -//===----------------------------------------------------------------------===// - -#ifndef CS_RISCVINSTPRINTER_H -#define CS_RISCVINSTPRINTER_H - -#include "../../MCInst.h" -#include "../../SStream.h" - -void RISCV_printInst(MCInst * MI, SStream * O, void *info); - -void RISCV_post_printer(csh ud, cs_insn * insn, char *insn_asm, MCInst * mci); - -#endif diff --git a/arch/RISCV/RISCVMapping.c b/arch/RISCV/RISCVMapping.c deleted file mode 100644 index 5d4a90e5ca..0000000000 --- a/arch/RISCV/RISCVMapping.c +++ /dev/null @@ -1,399 +0,0 @@ - -#ifdef CAPSTONE_HAS_RISCV - -#include // debug -#include - -#include "../../Mapping.h" -#include "../../utils.h" -#include "../../cs_simple_types.h" - -#include "RISCVMapping.h" -#include "RISCVInstPrinter.h" - -#define GET_INSTRINFO_ENUM -#include "RISCVGenInstrInfo.inc" - -#ifndef CAPSTONE_DIET -static const name_map reg_name_maps[] = { - { RISCV_REG_INVALID, NULL }, - - { RISCV_REG_X0, "zero" }, - { RISCV_REG_X1, "ra" }, - { RISCV_REG_X2, "sp" }, - { RISCV_REG_X3, "gp" }, - { RISCV_REG_X4, "tp" }, - { RISCV_REG_X5, "t0" }, - { RISCV_REG_X6, "t1" }, - { RISCV_REG_X7, "t2" }, - { RISCV_REG_X8, "s0" }, - { RISCV_REG_X9, "s1" }, - { RISCV_REG_X10, "a0" }, - { RISCV_REG_X11, "a1" }, - { RISCV_REG_X12, "a2" }, - { RISCV_REG_X13, "a3" }, - { RISCV_REG_X14, "a4" }, - { RISCV_REG_X15, "a5" }, - { RISCV_REG_X16, "a6" }, - { RISCV_REG_X17, "a7" }, - { RISCV_REG_X18, "s2" }, - { RISCV_REG_X19, "s3" }, - { RISCV_REG_X20, "s4" }, - { RISCV_REG_X21, "s5" }, - { RISCV_REG_X22, "s6" }, - { RISCV_REG_X23, "s7" }, - { RISCV_REG_X24, "s8" }, - { RISCV_REG_X25, "s9" }, - { RISCV_REG_X26, "s10" }, - { RISCV_REG_X27, "s11" }, - { RISCV_REG_X28, "t3" }, - { RISCV_REG_X29, "t4" }, - { RISCV_REG_X30, "t5" }, - { RISCV_REG_X31, "t6" }, - - { RISCV_REG_F0_32, "ft0" }, - { RISCV_REG_F0_64, "ft0" }, - { RISCV_REG_F1_32, "ft1" }, - { RISCV_REG_F1_64, "ft1" }, - { RISCV_REG_F2_32, "ft2" }, - { RISCV_REG_F2_64, "ft2" }, - { RISCV_REG_F3_32, "ft3" }, - { RISCV_REG_F3_64, "ft3" }, - { RISCV_REG_F4_32, "ft4" }, - { RISCV_REG_F4_64, "ft4" }, - { RISCV_REG_F5_32, "ft5" }, - { RISCV_REG_F5_64, "ft5" }, - { RISCV_REG_F6_32, "ft6" }, - { RISCV_REG_F6_64, "ft6" }, - { RISCV_REG_F7_32, "ft7" }, - { RISCV_REG_F7_64, "ft7" }, - { RISCV_REG_F8_32, "fs0" }, - { RISCV_REG_F8_64, "fs0" }, - { RISCV_REG_F9_32, "fs1" }, - { RISCV_REG_F9_64, "fs1" }, - { RISCV_REG_F10_32, "fa0" }, - { RISCV_REG_F10_64, "fa0" }, - { RISCV_REG_F11_32, "fa1" }, - { RISCV_REG_F11_64, "fa1" }, - { RISCV_REG_F12_32, "fa2" }, - { RISCV_REG_F12_64, "fa2" }, - { RISCV_REG_F13_32, "fa3" }, - { RISCV_REG_F13_64, "fa3" }, - { RISCV_REG_F14_32, "fa4" }, - { RISCV_REG_F14_64, "fa4" }, - { RISCV_REG_F15_32, "fa5" }, - { RISCV_REG_F15_64, "fa5" }, - { RISCV_REG_F16_32, "fa6" }, - { RISCV_REG_F16_64, "fa6" }, - { RISCV_REG_F17_32, "fa7" }, - { RISCV_REG_F17_64, "fa7" }, - { RISCV_REG_F18_32, "fs2" }, - { RISCV_REG_F18_64, "fs2" }, - { RISCV_REG_F19_32, "fs3" }, - { RISCV_REG_F19_64, "fs3" }, - { RISCV_REG_F20_32, "fs4" }, - { RISCV_REG_F20_64, "fs4" }, - { RISCV_REG_F21_32, "fs5" }, - { RISCV_REG_F21_64, "fs5" }, - { RISCV_REG_F22_32, "fs6" }, - { RISCV_REG_F22_64, "fs6" }, - { RISCV_REG_F23_32, "fs7" }, - { RISCV_REG_F23_64, "fs7" }, - { RISCV_REG_F24_32, "fs8" }, - { RISCV_REG_F24_64, "fs8" }, - { RISCV_REG_F25_32, "fs9" }, - { RISCV_REG_F25_64, "fs9" }, - { RISCV_REG_F26_32, "fs10" }, - { RISCV_REG_F26_64, "fs10" }, - { RISCV_REG_F27_32, "fs11" }, - { RISCV_REG_F27_64, "fs11" }, - { RISCV_REG_F28_32, "ft8" }, - { RISCV_REG_F28_64, "ft8" }, - { RISCV_REG_F29_32, "ft9" }, - { RISCV_REG_F29_64, "ft9" }, - { RISCV_REG_F30_32, "ft10" }, - { RISCV_REG_F30_64, "ft10" }, - { RISCV_REG_F31_32, "ft11" }, - { RISCV_REG_F31_64, "ft11" }, -}; -#endif - -const char *RISCV_reg_name(csh handle, unsigned int reg) -{ -#ifndef CAPSTONE_DIET - if (reg >= RISCV_REG_ENDING) - return NULL; - return reg_name_maps[reg].name; -#else - return NULL; -#endif -} - -static const insn_map insns[] = { - // dummy item - { - 0, 0, -#ifndef CAPSTONE_DIET - {0}, {0}, {0}, 0, 0 -#endif - }, - -#include "RISCVMappingInsn.inc" -}; - -#ifndef CAPSTONE_DIET - -static const map_insn_ops insn_operands[] = { -#include "RISCVMappingInsnOp.inc" -}; - -#endif - -void RISCV_add_cs_detail(MCInst *MI, unsigned OpNum) { - if (!detail_is_set(MI)) - return; - - cs_op_type op_type = map_get_op_type(MI, OpNum); - - if (op_type == CS_OP_IMM) { - RISCV_get_detail_op(MI, 0)->type = RISCV_OP_IMM; - RISCV_get_detail_op(MI, 0)->imm = MCInst_getOpVal(MI, OpNum); - RISCV_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); - RISCV_inc_op_count(MI); - } - else if (op_type == CS_OP_REG) { - RISCV_get_detail_op(MI, 0)->type = RISCV_OP_REG; - RISCV_get_detail_op(MI, 0)->reg = MCInst_getOpVal(MI, OpNum); - RISCV_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); - RISCV_inc_op_count(MI); - } - else { - CS_ASSERT(0 && "Op type not handled."); - } -} - -// given internal insn id, return public instruction info -void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id) -{ - unsigned int i; - - i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); - if (i != 0) { - insn->id = insns[i].mapid; - - if (h->detail_opt) { -#ifndef CAPSTONE_DIET - memcpy(insn->detail->regs_read, - insns[i].regs_use, sizeof(insns[i].regs_use)); - insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use); - - memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); - insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod); - - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups); - - if (insns[i].branch || insns[i].indirect_branch) { - // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = RISCV_GRP_JUMP; - insn->detail->groups_count++; - } -#endif - } - } -} - -static const name_map insn_name_maps[] = { - {RISCV_INS_INVALID, NULL}, - -#include "RISCVGenInsnNameMaps.inc" -}; - -const char *RISCV_insn_name(csh handle, unsigned int id) -{ -#ifndef CAPSTONE_DIET - if (id >= RISCV_INS_ENDING) - return NULL; - - return insn_name_maps[id].name; -#else - return NULL; -#endif -} - -#ifndef CAPSTONE_DIET -static const name_map group_name_maps[] = { - // generic groups - { RISCV_GRP_INVALID, NULL }, - { RISCV_GRP_JUMP, "jump" }, - { RISCV_GRP_CALL, "call" }, - { RISCV_GRP_RET, "ret" }, - { RISCV_GRP_INT, "int" }, - { RISCV_GRP_IRET, "iret" }, - { RISCV_GRP_PRIVILEGE, "privileged" }, - { RISCV_GRP_BRANCH_RELATIVE, "branch_relative" }, - - // architecture specific - { RISCV_GRP_ISRV32, "isrv32" }, - { RISCV_GRP_ISRV64, "isrv64" }, - { RISCV_GRP_HASSTDEXTA, "hasStdExtA" }, - { RISCV_GRP_HASSTDEXTC, "hasStdExtC" }, - { RISCV_GRP_HASSTDEXTD, "hasStdExtD" }, - { RISCV_GRP_HASSTDEXTF, "hasStdExtF" }, - { RISCV_GRP_HASSTDEXTM, "hasStdExtM" }, - - /* - { RISCV_GRP_ISRVA, "isrva" }, - { RISCV_GRP_ISRVC, "isrvc" }, - { RISCV_GRP_ISRVD, "isrvd" }, - { RISCV_GRP_ISRVCD, "isrvcd" }, - { RISCV_GRP_ISRVF, "isrvf" }, - { RISCV_GRP_ISRV32C, "isrv32c" }, - { RISCV_GRP_ISRV32CF, "isrv32cf" }, - { RISCV_GRP_ISRVM, "isrvm" }, - { RISCV_GRP_ISRV64A, "isrv64a" }, - { RISCV_GRP_ISRV64C, "isrv64c" }, - { RISCV_GRP_ISRV64D, "isrv64d" }, - { RISCV_GRP_ISRV64F, "isrv64f" }, - { RISCV_GRP_ISRV64M, "isrv64m" } - */ - { RISCV_GRP_ENDING, NULL } -}; -#endif - -const char *RISCV_group_name(csh handle, unsigned int id) -{ -#ifndef CAPSTONE_DIET - // verify group id - if (id >= RISCV_GRP_ENDING || - (id > RISCV_GRP_BRANCH_RELATIVE && id < RISCV_GRP_ISRV32)) - return NULL; - return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); -#else - return NULL; -#endif -} - -// map instruction name to public instruction ID -riscv_reg RISCV_map_insn(const char *name) -{ - // handle special alias first - unsigned int i; - - // NOTE: skip first NULL name in insn_name_maps - i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); - - return (i != -1) ? i : RISCV_REG_INVALID; -} - -// map internal raw register to 'public' register -riscv_reg RISCV_map_register(unsigned int r) -{ - static const unsigned int map[] = { 0, - RISCV_REG_X0, - RISCV_REG_X1, - RISCV_REG_X2, - RISCV_REG_X3, - RISCV_REG_X4, - RISCV_REG_X5, - RISCV_REG_X6, - RISCV_REG_X7, - RISCV_REG_X8, - RISCV_REG_X9, - RISCV_REG_X10, - RISCV_REG_X11, - RISCV_REG_X12, - RISCV_REG_X13, - RISCV_REG_X14, - RISCV_REG_X15, - RISCV_REG_X16, - RISCV_REG_X17, - RISCV_REG_X18, - RISCV_REG_X19, - RISCV_REG_X20, - RISCV_REG_X21, - RISCV_REG_X22, - RISCV_REG_X23, - RISCV_REG_X24, - RISCV_REG_X25, - RISCV_REG_X26, - RISCV_REG_X27, - RISCV_REG_X28, - RISCV_REG_X29, - RISCV_REG_X30, - RISCV_REG_X31, - - RISCV_REG_F0_32, - RISCV_REG_F0_64, - RISCV_REG_F1_32, - RISCV_REG_F1_64, - RISCV_REG_F2_32, - RISCV_REG_F2_64, - RISCV_REG_F3_32, - RISCV_REG_F3_64, - RISCV_REG_F4_32, - RISCV_REG_F4_64, - RISCV_REG_F5_32, - RISCV_REG_F5_64, - RISCV_REG_F6_32, - RISCV_REG_F6_64, - RISCV_REG_F7_32, - RISCV_REG_F7_64, - RISCV_REG_F8_32, - RISCV_REG_F8_64, - RISCV_REG_F9_32, - RISCV_REG_F9_64, - RISCV_REG_F10_32, - RISCV_REG_F10_64, - RISCV_REG_F11_32, - RISCV_REG_F11_64, - RISCV_REG_F12_32, - RISCV_REG_F12_64, - RISCV_REG_F13_32, - RISCV_REG_F13_64, - RISCV_REG_F14_32, - RISCV_REG_F14_64, - RISCV_REG_F15_32, - RISCV_REG_F15_64, - RISCV_REG_F16_32, - RISCV_REG_F16_64, - RISCV_REG_F17_32, - RISCV_REG_F17_64, - RISCV_REG_F18_32, - RISCV_REG_F18_64, - RISCV_REG_F19_32, - RISCV_REG_F19_64, - RISCV_REG_F20_32, - RISCV_REG_F20_64, - RISCV_REG_F21_32, - RISCV_REG_F21_64, - RISCV_REG_F22_32, - RISCV_REG_F22_64, - RISCV_REG_F23_32, - RISCV_REG_F23_64, - RISCV_REG_F24_32, - RISCV_REG_F24_64, - RISCV_REG_F25_32, - RISCV_REG_F25_64, - RISCV_REG_F26_32, - RISCV_REG_F26_64, - RISCV_REG_F27_32, - RISCV_REG_F27_64, - RISCV_REG_F28_32, - RISCV_REG_F28_64, - RISCV_REG_F29_32, - RISCV_REG_F29_64, - RISCV_REG_F30_32, - RISCV_REG_F30_64, - RISCV_REG_F31_32, - RISCV_REG_F31_64, - }; - - if (r < ARR_SIZE(map)) - return map[r]; - - // cannot find this register - return 0; -} - -#endif diff --git a/arch/RISCV/RISCVMapping.h b/arch/RISCV/RISCVMapping.h deleted file mode 100644 index e2992231d1..0000000000 --- a/arch/RISCV/RISCVMapping.h +++ /dev/null @@ -1,24 +0,0 @@ - -#ifndef CS_RISCV_MAP_H -#define CS_RISCV_MAP_H - -#include "../../include/capstone/capstone.h" - -// given internal insn id, return public instruction info -void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id); - -const char *RISCV_insn_name(csh handle, unsigned int id); - -const char *RISCV_group_name(csh handle, unsigned int id); - -const char *RISCV_reg_name(csh handle, unsigned int reg); - -void RISCV_add_cs_detail(MCInst *MI, unsigned OpNum); - -// map instruction name to instruction ID -riscv_reg RISCV_map_insn(const char *name); - -// map internal raw register to 'public' register -riscv_reg RISCV_map_register(unsigned int r); - -#endif diff --git a/arch/RISCV/RISCVMappingInsn.inc b/arch/RISCV/RISCVMappingInsn.inc deleted file mode 100644 index b2a9a10957..0000000000 --- a/arch/RISCV/RISCVMappingInsn.inc +++ /dev/null @@ -1,1635 +0,0 @@ -// This is auto-gen data for Capstone engine (www.capstone-engine.org) -// By Nguyen Anh Quynh - -{ - RISCV_ADD, RISCV_INS_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ADDI, RISCV_INS_ADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ADDIW, RISCV_INS_ADDIW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_ADDW, RISCV_INS_ADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_D, RISCV_INS_AMOADD_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_D_AQ, RISCV_INS_AMOADD_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_D_AQ_RL, RISCV_INS_AMOADD_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_D_RL, RISCV_INS_AMOADD_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_W, RISCV_INS_AMOADD_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_W_AQ, RISCV_INS_AMOADD_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_W_AQ_RL, RISCV_INS_AMOADD_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOADD_W_RL, RISCV_INS_AMOADD_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_D, RISCV_INS_AMOAND_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_D_AQ, RISCV_INS_AMOAND_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_D_AQ_RL, RISCV_INS_AMOAND_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_D_RL, RISCV_INS_AMOAND_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_W, RISCV_INS_AMOAND_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_W_AQ, RISCV_INS_AMOAND_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_W_AQ_RL, RISCV_INS_AMOAND_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOAND_W_RL, RISCV_INS_AMOAND_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_D, RISCV_INS_AMOMAXU_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_D_AQ, RISCV_INS_AMOMAXU_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_D_AQ_RL, RISCV_INS_AMOMAXU_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_D_RL, RISCV_INS_AMOMAXU_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_W, RISCV_INS_AMOMAXU_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_W_AQ, RISCV_INS_AMOMAXU_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_W_AQ_RL, RISCV_INS_AMOMAXU_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAXU_W_RL, RISCV_INS_AMOMAXU_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_D, RISCV_INS_AMOMAX_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_D_AQ, RISCV_INS_AMOMAX_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_D_AQ_RL, RISCV_INS_AMOMAX_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_D_RL, RISCV_INS_AMOMAX_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_W, RISCV_INS_AMOMAX_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_W_AQ, RISCV_INS_AMOMAX_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_W_AQ_RL, RISCV_INS_AMOMAX_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMAX_W_RL, RISCV_INS_AMOMAX_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_D, RISCV_INS_AMOMINU_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_D_AQ, RISCV_INS_AMOMINU_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_D_AQ_RL, RISCV_INS_AMOMINU_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_D_RL, RISCV_INS_AMOMINU_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_W, RISCV_INS_AMOMINU_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_W_AQ, RISCV_INS_AMOMINU_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_W_AQ_RL, RISCV_INS_AMOMINU_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMINU_W_RL, RISCV_INS_AMOMINU_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_D, RISCV_INS_AMOMIN_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_D_AQ, RISCV_INS_AMOMIN_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_D_AQ_RL, RISCV_INS_AMOMIN_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_D_RL, RISCV_INS_AMOMIN_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_W, RISCV_INS_AMOMIN_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_W_AQ, RISCV_INS_AMOMIN_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_W_AQ_RL, RISCV_INS_AMOMIN_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOMIN_W_RL, RISCV_INS_AMOMIN_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_D, RISCV_INS_AMOOR_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_D_AQ, RISCV_INS_AMOOR_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_D_AQ_RL, RISCV_INS_AMOOR_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_D_RL, RISCV_INS_AMOOR_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_W, RISCV_INS_AMOOR_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_W_AQ, RISCV_INS_AMOOR_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_W_AQ_RL, RISCV_INS_AMOOR_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOOR_W_RL, RISCV_INS_AMOOR_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_D, RISCV_INS_AMOSWAP_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_D_AQ, RISCV_INS_AMOSWAP_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_D_AQ_RL, RISCV_INS_AMOSWAP_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_D_RL, RISCV_INS_AMOSWAP_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_W, RISCV_INS_AMOSWAP_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_W_AQ, RISCV_INS_AMOSWAP_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_W_AQ_RL, RISCV_INS_AMOSWAP_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOSWAP_W_RL, RISCV_INS_AMOSWAP_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_D, RISCV_INS_AMOXOR_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_D_AQ, RISCV_INS_AMOXOR_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_D_AQ_RL, RISCV_INS_AMOXOR_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_D_RL, RISCV_INS_AMOXOR_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_W, RISCV_INS_AMOXOR_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_W_AQ, RISCV_INS_AMOXOR_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_W_AQ_RL, RISCV_INS_AMOXOR_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AMOXOR_W_RL, RISCV_INS_AMOXOR_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_AND, RISCV_INS_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ANDI, RISCV_INS_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_AUIPC, RISCV_INS_AUIPC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_BEQ, RISCV_INS_BEQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0 -#endif -}, -{ - RISCV_BGE, RISCV_INS_BGE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0 -#endif -}, -{ - RISCV_BGEU, RISCV_INS_BGEU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0 -#endif -}, -{ - RISCV_BLT, RISCV_INS_BLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0 -#endif -}, -{ - RISCV_BLTU, RISCV_INS_BLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0 -#endif -}, -{ - RISCV_BNE, RISCV_INS_BNE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0 -#endif -}, -{ - RISCV_CSRRC, RISCV_INS_CSRRC, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRCI, RISCV_INS_CSRRCI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRS, RISCV_INS_CSRRS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRSI, RISCV_INS_CSRRSI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRW, RISCV_INS_CSRRW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_CSRRWI, RISCV_INS_CSRRWI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADD, RISCV_INS_C_ADD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDI, RISCV_INS_C_ADDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDI16SP, RISCV_INS_C_ADDI16SP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDI4SPN, RISCV_INS_C_ADDI4SPN, -#ifndef CAPSTONE_DIET - { RISCV_REG_X2, 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDIW, RISCV_INS_C_ADDIW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ADDW, RISCV_INS_C_ADDW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_AND, RISCV_INS_C_AND, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_ANDI, RISCV_INS_C_ANDI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_BEQZ, RISCV_INS_C_BEQZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0 -#endif -}, -{ - RISCV_C_BNEZ, RISCV_INS_C_BNEZ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_BRANCH_RELATIVE, 0 }, 1, 0 -#endif -}, -{ - RISCV_C_EBREAK, RISCV_INS_C_EBREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FLD, RISCV_INS_C_FLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FLDSP, RISCV_INS_C_FLDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FLW, RISCV_INS_C_FLW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FLWSP, RISCV_INS_C_FLWSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FSD, RISCV_INS_C_FSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FSDSP, RISCV_INS_C_FSDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FSW, RISCV_INS_C_FSW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_FSWSP, RISCV_INS_C_FSWSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_J, RISCV_INS_C_J, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 0 -#endif -}, -{ - RISCV_C_JAL, RISCV_INS_C_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, RISCV_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_JALR, RISCV_INS_C_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { RISCV_REG_X1, 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_JR, RISCV_INS_C_JR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 1, 1 -#endif -}, -{ - RISCV_C_LD, RISCV_INS_C_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LDSP, RISCV_INS_C_LDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LI, RISCV_INS_C_LI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LUI, RISCV_INS_C_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LW, RISCV_INS_C_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_LWSP, RISCV_INS_C_LWSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_MV, RISCV_INS_C_MV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_NOP, RISCV_INS_C_NOP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_OR, RISCV_INS_C_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SD, RISCV_INS_C_SD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SDSP, RISCV_INS_C_SDSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SLLI, RISCV_INS_C_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SRAI, RISCV_INS_C_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SRLI, RISCV_INS_C_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SUB, RISCV_INS_C_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SUBW, RISCV_INS_C_SUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SW, RISCV_INS_C_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_SWSP, RISCV_INS_C_SWSP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_UNIMP, RISCV_INS_C_UNIMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_C_XOR, RISCV_INS_C_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTC, 0 }, 0, 0 -#endif -}, -{ - RISCV_DIV, RISCV_INS_DIV, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_DIVU, RISCV_INS_DIVU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_DIVUW, RISCV_INS_DIVUW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_DIVW, RISCV_INS_DIVW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_EBREAK, RISCV_INS_EBREAK, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ECALL, RISCV_INS_ECALL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_INT, 0 }, 0, 0 -#endif -}, -{ - RISCV_FADD_D, RISCV_INS_FADD_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FADD_S, RISCV_INS_FADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCLASS_D, RISCV_INS_FCLASS_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCLASS_S, RISCV_INS_FCLASS_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_L, RISCV_INS_FCVT_D_L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_LU, RISCV_INS_FCVT_D_LU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_S, RISCV_INS_FCVT_D_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_W, RISCV_INS_FCVT_D_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_D_WU, RISCV_INS_FCVT_D_WU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_LU_D, RISCV_INS_FCVT_LU_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_LU_S, RISCV_INS_FCVT_LU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_L_D, RISCV_INS_FCVT_L_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_L_S, RISCV_INS_FCVT_L_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_D, RISCV_INS_FCVT_S_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_L, RISCV_INS_FCVT_S_L, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_LU, RISCV_INS_FCVT_S_LU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_W, RISCV_INS_FCVT_S_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_S_WU, RISCV_INS_FCVT_S_WU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_WU_D, RISCV_INS_FCVT_WU_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_WU_S, RISCV_INS_FCVT_WU_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_W_D, RISCV_INS_FCVT_W_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FCVT_W_S, RISCV_INS_FCVT_W_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FDIV_D, RISCV_INS_FDIV_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FDIV_S, RISCV_INS_FDIV_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FENCE, RISCV_INS_FENCE, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_FENCE_I, RISCV_INS_FENCE_I, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_FENCE_TSO, RISCV_INS_FENCE_TSO, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_FEQ_D, RISCV_INS_FEQ_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FEQ_S, RISCV_INS_FEQ_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLD, RISCV_INS_FLD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLE_D, RISCV_INS_FLE_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLE_S, RISCV_INS_FLE_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLT_D, RISCV_INS_FLT_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLT_S, RISCV_INS_FLT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FLW, RISCV_INS_FLW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMADD_D, RISCV_INS_FMADD_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMADD_S, RISCV_INS_FMADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMAX_D, RISCV_INS_FMAX_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMAX_S, RISCV_INS_FMAX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMIN_D, RISCV_INS_FMIN_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMIN_S, RISCV_INS_FMIN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMSUB_D, RISCV_INS_FMSUB_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMSUB_S, RISCV_INS_FMSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMUL_D, RISCV_INS_FMUL_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMUL_S, RISCV_INS_FMUL_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMV_D_X, RISCV_INS_FMV_D_X, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMV_W_X, RISCV_INS_FMV_W_X, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMV_X_D, RISCV_INS_FMV_X_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_FMV_X_W, RISCV_INS_FMV_X_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FNMADD_D, RISCV_INS_FNMADD_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FNMADD_S, RISCV_INS_FNMADD_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FNMSUB_D, RISCV_INS_FNMSUB_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FNMSUB_S, RISCV_INS_FNMSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSD, RISCV_INS_FSD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJN_D, RISCV_INS_FSGNJN_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJN_S, RISCV_INS_FSGNJN_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJX_D, RISCV_INS_FSGNJX_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJX_S, RISCV_INS_FSGNJX_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJ_D, RISCV_INS_FSGNJ_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSGNJ_S, RISCV_INS_FSGNJ_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSQRT_D, RISCV_INS_FSQRT_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSQRT_S, RISCV_INS_FSQRT_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSUB_D, RISCV_INS_FSUB_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTD, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSUB_S, RISCV_INS_FSUB_S, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_FSW, RISCV_INS_FSW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTF, 0 }, 0, 0 -#endif -}, -{ - RISCV_JAL, RISCV_INS_JAL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - RISCV_JALR, RISCV_INS_JALR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_CALL, 0 }, 0, 0 -#endif -}, -{ - RISCV_LB, RISCV_INS_LB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LBU, RISCV_INS_LBU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LD, RISCV_INS_LD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LH, RISCV_INS_LH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LHU, RISCV_INS_LHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_D, RISCV_INS_LR_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_D_AQ, RISCV_INS_LR_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_D_AQ_RL, RISCV_INS_LR_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_D_RL, RISCV_INS_LR_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_W, RISCV_INS_LR_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_W_AQ, RISCV_INS_LR_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_W_AQ_RL, RISCV_INS_LR_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_LR_W_RL, RISCV_INS_LR_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_LUI, RISCV_INS_LUI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LW, RISCV_INS_LW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_LWU, RISCV_INS_LWU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_MRET, RISCV_INS_MRET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_MUL, RISCV_INS_MUL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_MULH, RISCV_INS_MULH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_MULHSU, RISCV_INS_MULHSU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_MULHU, RISCV_INS_MULHU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_MULW, RISCV_INS_MULW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_OR, RISCV_INS_OR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_ORI, RISCV_INS_ORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_REM, RISCV_INS_REM, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_REMU, RISCV_INS_REMU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, 0 }, 0, 0 -#endif -}, -{ - RISCV_REMUW, RISCV_INS_REMUW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_REMW, RISCV_INS_REMW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SB, RISCV_INS_SB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_D, RISCV_INS_SC_D, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_D_AQ, RISCV_INS_SC_D_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_D_AQ_RL, RISCV_INS_SC_D_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_D_RL, RISCV_INS_SC_D_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_W, RISCV_INS_SC_W, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_W_AQ, RISCV_INS_SC_W_AQ, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_W_AQ_RL, RISCV_INS_SC_W_AQ_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_SC_W_RL, RISCV_INS_SC_W_RL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_HASSTDEXTA, 0 }, 0, 0 -#endif -}, -{ - RISCV_SD, RISCV_INS_SD, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SFENCE_VMA, RISCV_INS_SFENCE_VMA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SH, RISCV_INS_SH, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLL, RISCV_INS_SLL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLLI, RISCV_INS_SLLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLLIW, RISCV_INS_SLLIW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SLLW, RISCV_INS_SLLW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SLT, RISCV_INS_SLT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLTI, RISCV_INS_SLTI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLTIU, RISCV_INS_SLTIU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SLTU, RISCV_INS_SLTU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SRA, RISCV_INS_SRA, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SRAI, RISCV_INS_SRAI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SRAIW, RISCV_INS_SRAIW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SRAW, RISCV_INS_SRAW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SRET, RISCV_INS_SRET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SRL, RISCV_INS_SRL, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SRLI, RISCV_INS_SRLI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SRLIW, RISCV_INS_SRLIW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SRLW, RISCV_INS_SRLW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SUB, RISCV_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_SUBW, RISCV_INS_SUBW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { RISCV_GRP_ISRV64, 0 }, 0, 0 -#endif -}, -{ - RISCV_SW, RISCV_INS_SW, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_UNIMP, RISCV_INS_UNIMP, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_URET, RISCV_INS_URET, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_WFI, RISCV_INS_WFI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_XOR, RISCV_INS_XOR, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, -{ - RISCV_XORI, RISCV_INS_XORI, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 -#endif -}, diff --git a/arch/RISCV/RISCVMappingInsnOp.inc b/arch/RISCV/RISCVMappingInsnOp.inc deleted file mode 100644 index fc67f0834b..0000000000 --- a/arch/RISCV/RISCVMappingInsnOp.inc +++ /dev/null @@ -1,2438 +0,0 @@ -/* Capstone Disassembly Engine, https://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2022, */ -/* Rot127 2022-2023 */ - -{{{ /* RISCV_PHI (0) */ - 0 -}}}, -{{{ /* RISCV_INLINEASM (1) */ - 0 -}}}, -{{{ /* RISCV_INLINEASM_BR (2) */ - 0 -}}}, -{{{ /* RISCV_CFI_INSTRUCTION (3) */ - 0 -}}}, -{{{ /* RISCV_EH_LABEL (4) */ - 0 -}}}, -{{{ /* RISCV_GC_LABEL (5) */ - 0 -}}}, -{{{ /* RISCV_ANNOTATION_LABEL (6) */ - 0 -}}}, -{{{ /* RISCV_KILL (7) */ - 0 -}}}, -{{{ /* RISCV_EXTRACT_SUBREG (8) */ - 0 -}}}, -{{{ /* RISCV_INSERT_SUBREG (9) */ - 0 -}}}, -{{{ /* RISCV_IMPLICIT_DEF (10) */ - 0 -}}}, -{{{ /* RISCV_SUBREG_TO_REG (11) */ - 0 -}}}, -{{{ /* RISCV_COPY_TO_REGCLASS (12) */ - 0 -}}}, -{{{ /* RISCV_DBG_VALUE (13) */ - 0 -}}}, -{{{ /* RISCV_DBG_LABEL (14) */ - 0 -}}}, -{{{ /* RISCV_REG_SEQUENCE (15) */ - 0 -}}}, -{{{ /* RISCV_COPY (16) */ - 0 -}}}, -{{{ /* RISCV_BUNDLE (17) */ - 0 -}}}, -{{{ /* RISCV_LIFETIME_START (18) */ - 0 -}}}, -{{{ /* RISCV_LIFETIME_END (19) */ - 0 -}}}, -{{{ /* RISCV_STACKMAP (20) */ - 0 -}}}, -{{{ /* RISCV_FENTRY_CALL (21) */ - 0 -}}}, -{{{ /* RISCV_PATCHPOINT (22) */ - 0 -}}}, -{{{ /* RISCV_LOAD_STACK_GUARD (23) */ - 0 -}}}, -{{{ /* RISCV_STATEPOINT (24) */ - 0 -}}}, -{{{ /* RISCV_LOCAL_ESCAPE (25) */ - 0 -}}}, -{{{ /* RISCV_FAULTING_OP (26) */ - 0 -}}}, -{{{ /* RISCV_PATCHABLE_OP (27) */ - 0 -}}}, -{{{ /* RISCV_PATCHABLE_FUNCTION_ENTER (28) */ - 0 -}}}, -{{{ /* RISCV_PATCHABLE_RET (29) */ - 0 -}}}, -{{{ /* RISCV_PATCHABLE_FUNCTION_EXIT (30) */ - 0 -}}}, -{{{ /* RISCV_PATCHABLE_TAIL_CALL (31) */ - 0 -}}}, -{{{ /* RISCV_PATCHABLE_EVENT_CALL (32) */ - 0 -}}}, -{{{ /* RISCV_PATCHABLE_TYPED_EVENT_CALL (33) */ - 0 -}}}, -{{{ /* RISCV_ICALL_BRANCH_FUNNEL (34) */ - 0 -}}}, -{{{ /* RISCV_G_ADD (35) */ - 0 -}}}, -{{{ /* RISCV_G_SUB (36) */ - 0 -}}}, -{{{ /* RISCV_G_MUL (37) */ - 0 -}}}, -{{{ /* RISCV_G_SDIV (38) */ - 0 -}}}, -{{{ /* RISCV_G_UDIV (39) */ - 0 -}}}, -{{{ /* RISCV_G_SREM (40) */ - 0 -}}}, -{{{ /* RISCV_G_UREM (41) */ - 0 -}}}, -{{{ /* RISCV_G_AND (42) */ - 0 -}}}, -{{{ /* RISCV_G_OR (43) */ - 0 -}}}, -{{{ /* RISCV_G_XOR (44) */ - 0 -}}}, -{{{ /* RISCV_G_IMPLICIT_DEF (45) */ - 0 -}}}, -{{{ /* RISCV_G_PHI (46) */ - 0 -}}}, -{{{ /* RISCV_G_FRAME_INDEX (47) */ - 0 -}}}, -{{{ /* RISCV_G_GLOBAL_VALUE (48) */ - 0 -}}}, -{{{ /* RISCV_G_EXTRACT (49) */ - 0 -}}}, -{{{ /* RISCV_G_UNMERGE_VALUES (50) */ - 0 -}}}, -{{{ /* RISCV_G_INSERT (51) */ - 0 -}}}, -{{{ /* RISCV_G_MERGE_VALUES (52) */ - 0 -}}}, -{{{ /* RISCV_G_BUILD_VECTOR (53) */ - 0 -}}}, -{{{ /* RISCV_G_BUILD_VECTOR_TRUNC (54) */ - 0 -}}}, -{{{ /* RISCV_G_CONCAT_VECTORS (55) */ - 0 -}}}, -{{{ /* RISCV_G_PTRTOINT (56) */ - 0 -}}}, -{{{ /* RISCV_G_INTTOPTR (57) */ - 0 -}}}, -{{{ /* RISCV_G_BITCAST (58) */ - 0 -}}}, -{{{ /* RISCV_G_INTRINSIC_TRUNC (59) */ - 0 -}}}, -{{{ /* RISCV_G_INTRINSIC_ROUND (60) */ - 0 -}}}, -{{{ /* RISCV_G_LOAD (61) */ - 0 -}}}, -{{{ /* RISCV_G_SEXTLOAD (62) */ - 0 -}}}, -{{{ /* RISCV_G_ZEXTLOAD (63) */ - 0 -}}}, -{{{ /* RISCV_G_STORE (64) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMIC_CMPXCHG_WITH_SUCCESS (65) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMIC_CMPXCHG (66) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_XCHG (67) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_ADD (68) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_SUB (69) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_AND (70) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_NAND (71) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_OR (72) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_XOR (73) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_MAX (74) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_MIN (75) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_UMAX (76) */ - 0 -}}}, -{{{ /* RISCV_G_ATOMICRMW_UMIN (77) */ - 0 -}}}, -{{{ /* RISCV_G_BRCOND (78) */ - 0 -}}}, -{{{ /* RISCV_G_BRINDIRECT (79) */ - 0 -}}}, -{{{ /* RISCV_G_INTRINSIC (80) */ - 0 -}}}, -{{{ /* RISCV_G_INTRINSIC_W_SIDE_EFFECTS (81) */ - 0 -}}}, -{{{ /* RISCV_G_ANYEXT (82) */ - 0 -}}}, -{{{ /* RISCV_G_TRUNC (83) */ - 0 -}}}, -{{{ /* RISCV_G_CONSTANT (84) */ - 0 -}}}, -{{{ /* RISCV_G_FCONSTANT (85) */ - 0 -}}}, -{{{ /* RISCV_G_VASTART (86) */ - 0 -}}}, -{{{ /* RISCV_G_VAARG (87) */ - 0 -}}}, -{{{ /* RISCV_G_SEXT (88) */ - 0 -}}}, -{{{ /* RISCV_G_ZEXT (89) */ - 0 -}}}, -{{{ /* RISCV_G_SHL (90) */ - 0 -}}}, -{{{ /* RISCV_G_LSHR (91) */ - 0 -}}}, -{{{ /* RISCV_G_ASHR (92) */ - 0 -}}}, -{{{ /* RISCV_G_ICMP (93) */ - 0 -}}}, -{{{ /* RISCV_G_FCMP (94) */ - 0 -}}}, -{{{ /* RISCV_G_SELECT (95) */ - 0 -}}}, -{{{ /* RISCV_G_UADDO (96) */ - 0 -}}}, -{{{ /* RISCV_G_UADDE (97) */ - 0 -}}}, -{{{ /* RISCV_G_USUBO (98) */ - 0 -}}}, -{{{ /* RISCV_G_USUBE (99) */ - 0 -}}}, -{{{ /* RISCV_G_SADDO (100) */ - 0 -}}}, -{{{ /* RISCV_G_SADDE (101) */ - 0 -}}}, -{{{ /* RISCV_G_SSUBO (102) */ - 0 -}}}, -{{{ /* RISCV_G_SSUBE (103) */ - 0 -}}}, -{{{ /* RISCV_G_UMULO (104) */ - 0 -}}}, -{{{ /* RISCV_G_SMULO (105) */ - 0 -}}}, -{{{ /* RISCV_G_UMULH (106) */ - 0 -}}}, -{{{ /* RISCV_G_SMULH (107) */ - 0 -}}}, -{{{ /* RISCV_G_FADD (108) */ - 0 -}}}, -{{{ /* RISCV_G_FSUB (109) */ - 0 -}}}, -{{{ /* RISCV_G_FMUL (110) */ - 0 -}}}, -{{{ /* RISCV_G_FMA (111) */ - 0 -}}}, -{{{ /* RISCV_G_FDIV (112) */ - 0 -}}}, -{{{ /* RISCV_G_FREM (113) */ - 0 -}}}, -{{{ /* RISCV_G_FPOW (114) */ - 0 -}}}, -{{{ /* RISCV_G_FEXP (115) */ - 0 -}}}, -{{{ /* RISCV_G_FEXP2 (116) */ - 0 -}}}, -{{{ /* RISCV_G_FLOG (117) */ - 0 -}}}, -{{{ /* RISCV_G_FLOG2 (118) */ - 0 -}}}, -{{{ /* RISCV_G_FLOG10 (119) */ - 0 -}}}, -{{{ /* RISCV_G_FNEG (120) */ - 0 -}}}, -{{{ /* RISCV_G_FPEXT (121) */ - 0 -}}}, -{{{ /* RISCV_G_FPTRUNC (122) */ - 0 -}}}, -{{{ /* RISCV_G_FPTOSI (123) */ - 0 -}}}, -{{{ /* RISCV_G_FPTOUI (124) */ - 0 -}}}, -{{{ /* RISCV_G_SITOFP (125) */ - 0 -}}}, -{{{ /* RISCV_G_UITOFP (126) */ - 0 -}}}, -{{{ /* RISCV_G_FABS (127) */ - 0 -}}}, -{{{ /* RISCV_G_FCANONICALIZE (128) */ - 0 -}}}, -{{{ /* RISCV_G_GEP (129) */ - 0 -}}}, -{{{ /* RISCV_G_PTR_MASK (130) */ - 0 -}}}, -{{{ /* RISCV_G_BR (131) */ - 0 -}}}, -{{{ /* RISCV_G_INSERT_VECTOR_ELT (132) */ - 0 -}}}, -{{{ /* RISCV_G_EXTRACT_VECTOR_ELT (133) */ - 0 -}}}, -{{{ /* RISCV_G_SHUFFLE_VECTOR (134) */ - 0 -}}}, -{{{ /* RISCV_G_CTTZ (135) */ - 0 -}}}, -{{{ /* RISCV_G_CTTZ_ZERO_UNDEF (136) */ - 0 -}}}, -{{{ /* RISCV_G_CTLZ (137) */ - 0 -}}}, -{{{ /* RISCV_G_CTLZ_ZERO_UNDEF (138) */ - 0 -}}}, -{{{ /* RISCV_G_CTPOP (139) */ - 0 -}}}, -{{{ /* RISCV_G_BSWAP (140) */ - 0 -}}}, -{{{ /* RISCV_G_FCEIL (141) */ - 0 -}}}, -{{{ /* RISCV_G_FCOS (142) */ - 0 -}}}, -{{{ /* RISCV_G_FSIN (143) */ - 0 -}}}, -{{{ /* RISCV_G_FSQRT (144) */ - 0 -}}}, -{{{ /* RISCV_G_FFLOOR (145) */ - 0 -}}}, -{{{ /* RISCV_G_ADDRSPACE_CAST (146) */ - 0 -}}}, -{{{ /* RISCV_G_BLOCK_ADDR (147) */ - 0 -}}}, -{{{ /* RISCV_ADJCALLSTACKDOWN (148) */ - 0 -}}}, -{{{ /* RISCV_ADJCALLSTACKUP (149) */ - 0 -}}}, -{{{ /* RISCV_BuildPairF64Pseudo (150) */ - 0 -}}}, -{{{ /* RISCV_PseudoAtomicLoadNand32 (151) */ - 0 -}}}, -{{{ /* RISCV_PseudoAtomicLoadNand64 (152) */ - 0 -}}}, -{{{ /* RISCV_PseudoBR (153) */ - 0 -}}}, -{{{ /* RISCV_PseudoBRIND (154) */ - 0 -}}}, -{{{ /* RISCV_PseudoCALL (155) */ - 0 -}}}, -{{{ /* RISCV_PseudoCALLIndirect (156) */ - 0 -}}}, -{{{ /* RISCV_PseudoCmpXchg32 (157) */ - 0 -}}}, -{{{ /* RISCV_PseudoCmpXchg64 (158) */ - 0 -}}}, -{{{ /* RISCV_PseudoLA (159) */ - 0 -}}}, -{{{ /* RISCV_PseudoLI (160) */ - 0 -}}}, -{{{ /* RISCV_PseudoLLA (161) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedAtomicLoadAdd32 (162) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedAtomicLoadMax32 (163) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedAtomicLoadMin32 (164) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedAtomicLoadNand32 (165) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedAtomicLoadSub32 (166) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedAtomicLoadUMax32 (167) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedAtomicLoadUMin32 (168) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedAtomicSwap32 (169) */ - 0 -}}}, -{{{ /* RISCV_PseudoMaskedCmpXchg32 (170) */ - 0 -}}}, -{{{ /* RISCV_PseudoRET (171) */ - 0 -}}}, -{{{ /* RISCV_PseudoTAIL (172) */ - 0 -}}}, -{{{ /* RISCV_PseudoTAILIndirect (173) */ - 0 -}}}, -{{{ /* RISCV_Select_FPR32_Using_CC_GPR (174) */ - 0 -}}}, -{{{ /* RISCV_Select_FPR64_Using_CC_GPR (175) */ - 0 -}}}, -{{{ /* RISCV_Select_GPR_Using_CC_GPR (176) */ - 0 -}}}, -{{{ /* RISCV_SplitF64Pseudo (177) */ - 0 -}}}, -{ /* RISCV_ADD (178) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_ADDI (179) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_ADDIW (180) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_ADDW (181) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOADD_D (182) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOADD_D_AQ (183) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOADD_D_AQ_RL (184) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOADD_D_RL (185) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOADD_W (186) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOADD_W_AQ (187) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOADD_W_AQ_RL (188) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOADD_W_RL (189) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOAND_D (190) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOAND_D_AQ (191) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOAND_D_AQ_RL (192) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOAND_D_RL (193) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOAND_W (194) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOAND_W_AQ (195) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOAND_W_AQ_RL (196) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOAND_W_RL (197) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAXU_D (198) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAXU_D_AQ (199) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAXU_D_AQ_RL (200) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAXU_D_RL (201) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAXU_W (202) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAXU_W_AQ (203) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAXU_W_AQ_RL (204) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAXU_W_RL (205) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAX_D (206) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAX_D_AQ (207) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAX_D_AQ_RL (208) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAX_D_RL (209) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAX_W (210) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAX_W_AQ (211) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAX_W_AQ_RL (212) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMAX_W_RL (213) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMINU_D (214) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMINU_D_AQ (215) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMINU_D_AQ_RL (216) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMINU_D_RL (217) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMINU_W (218) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMINU_W_AQ (219) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMINU_W_AQ_RL (220) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMINU_W_RL (221) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMIN_D (222) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMIN_D_AQ (223) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMIN_D_AQ_RL (224) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMIN_D_RL (225) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMIN_W (226) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMIN_W_AQ (227) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMIN_W_AQ_RL (228) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOMIN_W_RL (229) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOOR_D (230) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOOR_D_AQ (231) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOOR_D_AQ_RL (232) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOOR_D_RL (233) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOOR_W (234) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOOR_W_AQ (235) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOOR_W_AQ_RL (236) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOOR_W_RL (237) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOSWAP_D (238) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOSWAP_D_AQ (239) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOSWAP_D_AQ_RL (240) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOSWAP_D_RL (241) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOSWAP_W (242) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOSWAP_W_AQ (243) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOSWAP_W_AQ_RL (244) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOSWAP_W_RL (245) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOXOR_D (246) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOXOR_D_AQ (247) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOXOR_D_AQ_RL (248) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOXOR_D_RL (249) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOXOR_W (250) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOXOR_W_AQ (251) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOXOR_W_AQ_RL (252) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AMOXOR_W_RL (253) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AND (254) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_ANDI (255) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_AUIPC (256) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_BEQ (257) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_BGE (258) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_BGEU (259) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_BLT (260) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_BLTU (261) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_BNE (262) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_CSRRC (263) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_CSRRCI (264) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_CSRRS (265) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_CSRRSI (266) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_CSRRW (267) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_CSRRWI (268) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_ADD (269) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_ADDI (270) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_ADDI16SP (271) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_ADDI4SPN (272) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_ADDIW (273) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_ADDW (274) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_AND (275) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_ANDI (276) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_BEQZ (277) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_BNEZ (278) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_EBREAK (279) */ -{ - { 0 } -}}, -{ /* RISCV_C_FLD (280) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_FLDSP (281) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_FLW (282) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_FLWSP (283) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_FSD (284) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_FSDSP (285) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_FSW (286) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_FSWSP (287) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_J (288) */ -{ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_JAL (289) */ -{ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_JALR (290) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_JR (291) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_LD (292) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_LDSP (293) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_LI (294) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_LUI (295) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_LW (296) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_LWSP (297) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_MV (298) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_NOP (299) */ -{ - { 0 } -}}, -{ /* RISCV_C_OR (300) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SD (301) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SDSP (302) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SLLI (303) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SRAI (304) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SRLI (305) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SUB (306) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SUBW (307) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SW (308) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_SWSP (309) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_C_UNIMP (310) */ -{ - { 0 } -}}, -{ /* RISCV_C_XOR (311) */ -{ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_DIV (312) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_DIVU (313) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_DIVUW (314) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_DIVW (315) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_EBREAK (316) */ -{ - { 0 } -}}, -{ /* RISCV_ECALL (317) */ -{ - { 0 } -}}, -{ /* RISCV_FADD_D (318) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FADD_S (319) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCLASS_D (320) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCLASS_S (321) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_D_L (322) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_D_LU (323) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_D_S (324) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_D_W (325) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_D_WU (326) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_LU_D (327) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_LU_S (328) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_L_D (329) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_L_S (330) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_S_D (331) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_S_L (332) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_S_LU (333) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_S_W (334) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_S_WU (335) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_WU_D (336) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_WU_S (337) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_W_D (338) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FCVT_W_S (339) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FDIV_D (340) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FDIV_S (341) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FENCE (342) */ -{ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FENCE_I (343) */ -{ - { 0 } -}}, -{ /* RISCV_FENCE_TSO (344) */ -{ - { 0 } -}}, -{ /* RISCV_FEQ_D (345) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FEQ_S (346) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FLD (347) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FLE_D (348) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FLE_S (349) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FLT_D (350) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FLT_S (351) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FLW (352) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMADD_D (353) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMADD_S (354) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMAX_D (355) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMAX_S (356) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMIN_D (357) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMIN_S (358) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMSUB_D (359) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMSUB_S (360) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMUL_D (361) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMUL_S (362) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMV_D_X (363) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMV_W_X (364) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMV_X_D (365) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FMV_X_W (366) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FNMADD_D (367) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FNMADD_S (368) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FNMSUB_D (369) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FNMSUB_S (370) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSD (371) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSGNJN_D (372) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSGNJN_S (373) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSGNJX_D (374) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSGNJX_S (375) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSGNJ_D (376) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSGNJ_S (377) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSQRT_D (378) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSQRT_S (379) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSUB_D (380) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSUB_S (381) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_FSW (382) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_JAL (383) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_JALR (384) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LB (385) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i8, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LBU (386) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i8, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LD (387) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LH (388) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i16, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LHU (389) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i16, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LR_D (390) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LR_D_AQ (391) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LR_D_AQ_RL (392) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LR_D_RL (393) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LR_W (394) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LR_W_AQ (395) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LR_W_AQ_RL (396) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LR_W_RL (397) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LUI (398) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LW (399) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_LWU (400) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_MRET (401) */ -{ - { 0 } -}}, -{ /* RISCV_MUL (402) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_MULH (403) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_MULHSU (404) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_MULHU (405) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_MULW (406) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_OR (407) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_ORI (408) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_REM (409) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_REMU (410) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_REMUW (411) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_REMW (412) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SB (413) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i8, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SC_D (414) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SC_D_AQ (415) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SC_D_AQ_RL (416) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SC_D_RL (417) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SC_W (418) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SC_W_AQ (419) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SC_W_AQ_RL (420) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SC_W_RL (421) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SD (422) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SFENCE_VMA (423) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SH (424) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i16, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SLL (425) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SLLI (426) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SLLIW (427) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SLLW (428) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SLT (429) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SLTI (430) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SLTIU (431) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SLTU (432) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SRA (433) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SRAI (434) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SRAIW (435) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SRAW (436) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SRET (437) */ -{ - { 0 } -}}, -{ /* RISCV_SRL (438) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SRLI (439) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SRLIW (440) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SRLW (441) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SUB (442) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SUBW (443) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_SW (444) */ -{ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_UNIMP (445) */ -{ - { 0 } -}}, -{ /* RISCV_URET (446) */ -{ - { 0 } -}}, -{ /* RISCV_WFI (447) */ -{ - { 0 } -}}, -{ /* RISCV_XOR (448) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_XORI (449) */ -{ - { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST }, }, /* */ - { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST }, }, /* */ - { 0 } -}}, -{ /* RISCV_INSTRUCTION_LIST_END (450) */ -{ - { 0 } -}}, diff --git a/arch/RISCV/RISCVModule.c b/arch/RISCV/RISCVModule.c index 62b2b3b982..bd8ea4b7bb 100644 --- a/arch/RISCV/RISCVModule.c +++ b/arch/RISCV/RISCVModule.c @@ -1,32 +1,43 @@ /* Capstone Disassembly Engine */ /* RISC-V Backend By Rodrigo Cortes Porto & Shawn Chang , HardenedLinux@2018 */ - #ifdef CAPSTONE_HAS_RISCV -#include "../../utils.h" -#include "../../MCRegisterInfo.h" -#include "RISCVDisassembler.h" -#include "RISCVInstPrinter.h" -#include "RISCVMapping.h" #include "RISCVModule.h" +const char *noop_getname(csh handle, unsigned int id) { + return ""; +} + +void noop_getid(cs_struct *h, cs_insn *insn, unsigned int id) { + +} + +const char *riscv_get_regname(csh handle, unsigned int id) { + if (IS_GEN_PURPOSE_REG(id)) { + return reg_names[INDEX_FROM_GEN_PURPOSE_REG(id)]; + } else if (IS_FLOAT_REG(id)) { + return freg_names[INDEX_FROM_FLOAT_REG(id)]; + } else if (IS_DOUBLE_REG(id)) { + return freg_names[INDEX_FROM_DOUBLE_REG(id)]; + } else if (IS_VECTOR_REG(id)) { + return vreg_names[INDEX_FROM_VECTOR_REG(id)]; + } + return ""; +} + cs_err RISCV_global_init(cs_struct * ud) { - MCRegisterInfo *mri; - mri = cs_mem_malloc(sizeof(*mri)); - - RISCV_init(mri); - ud->printer = RISCV_printInst; - ud->printer_info = mri; - ud->getinsn_info = mri; - ud->disasm = RISCV_getInstruction; + ud->printer = riscv_printer; + ud->printer_info = NULL; + ud->getinsn_info = NULL; + ud->disasm = riscv_get_instruction; ud->post_printer = NULL; - ud->reg_name = RISCV_reg_name; - ud->insn_id = RISCV_get_insn_id; - ud->insn_name = RISCV_insn_name; - ud->group_name = RISCV_group_name; + ud->reg_name = riscv_get_regname; + ud->insn_id = noop_getid; + ud->insn_name = noop_getname; + ud->group_name = noop_getname; return CS_ERR_OK; } diff --git a/arch/RISCV/RISCVModule.h b/arch/RISCV/RISCVModule.h index c250db554d..3362bd2e23 100644 --- a/arch/RISCV/RISCVModule.h +++ b/arch/RISCV/RISCVModule.h @@ -5,6 +5,10 @@ #define CS_RISCV_MODULE_H #include "../../utils.h" +#include "RISCVDisassembler.h" +#include "RISCVPrinter.h" +#include "RISCVOperandsHelpers.h" +#include "RISCVAst2StrHelpers.h" cs_err RISCV_global_init(cs_struct * ud); cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value); diff --git a/arch/RISCV/RISCVOperands.gen.inc b/arch/RISCV/RISCVOperands.gen.inc new file mode 100644 index 0000000000..d6847b57b4 --- /dev/null +++ b/arch/RISCV/RISCVOperands.gen.inc @@ -0,0 +1,3752 @@ +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ + +#ifndef __RISCVOPERANDS_GEN_INC__ +#define __RISCVOPERANDS_GEN_INC__ +#include +#include +#include + +#include "../../include/capstone/capstone.h" +#include "RISCVAst.gen.inc" +#include "RISCVOperandsHelpers.h" + +static void fill_operands(struct ast *tree, cs_riscv_op *ops, + uint8_t *op_count) { + switch (tree->ast_node_type) { + case RISCV_DIV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.div.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.div.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.div.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_SRAI_HINT: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_srai_hint); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_AES64ES: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64es.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64es.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64es.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FLTQ_D: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fltq_d.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fltq_d.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fltq_d.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_SWSP: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_swsp.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_swsp.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_C_FLW: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_flw.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_flw.rsc); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_flw.rdc); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_MVXTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.mvxtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.mvxtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.mvxtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VICMPTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vicmptype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.vicmptype.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vicmptype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FLEQ_H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fleq_h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fleq_h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fleq_h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA256SIG1: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha256sig1.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha256sig1.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VSHA2MS_VV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vsha2ms_vv.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vsha2ms_vv.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vsha2ms_vv.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VCPOP_M: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vcpop_m.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vcpop_m.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_ADDW: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_addw.rsd); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_addw.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_C_ADDI4SPN: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_addi4spn.rdc); + ops[0].access = CS_AC_WRITE; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.c_addi4spn.nzimm; + ops[1].access = CS_AC_READ; + break; + } + case RISCV_C_FSD: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_fsd.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_fsd.rsc1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_fsd.rsc2); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_VANDN_VV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vandn_vv.vs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vandn_vv.vs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vandn_vv.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_AES32DSMI: { + *op_count = 4; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.aes32dsmi.bs; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32dsmi.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32dsmi.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32dsmi.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_VCLMULH_VV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vclmulh_vv.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vclmulh_vv.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vclmulh_vv.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_BREV8: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_brev8.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_brev8.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ZIMOP_MOP_RR: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zimop_mop_rr.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zimop_mop_rr.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zimop_mop_rr.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VREV8_V: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vrev8_v.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vrev8_v.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_SHA256SIG0: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha256sig0.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha256sig0.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ILLEGAL: { + *op_count = 1; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.illegal; + ops[0].access = CS_AC_READ; + break; + } + case RISCV_VLSEGTYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vlsegtype.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vlsegtype.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VVCMPTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vvcmptype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vvcmptype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vvcmptype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SIG1L: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig1l.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig1l.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig1l.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VWSLL_VV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vwsll_vv.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vwsll_vv.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vwsll_vv.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_MULW: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.mulw.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.mulw.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.mulw.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_ZEXT_H: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_zext_h); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_WMVVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.wmvvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.wmvvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.wmvvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_MADD_TYPE_D: { + *op_count = 4; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_d.rs3); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_d.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_d.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_d.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_RTYPEW: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rtypew.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rtypew.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rtypew.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_LBU: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_lbu.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_lbu.rdc); + ops[1].access = CS_AC_WRITE; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_lbu.rs1c); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_FMVP_D_X: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fmvp_d_x.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fmvp_d_x.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmvp_d_x.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_LUI: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_lui.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_lui.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_RM_FF_TYPE_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_ff_type_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_ff_type_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_SRAI: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_srai.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_srai.rsd); + ops[1].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_F_BIN_X_TYPE_H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_x_type_h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_x_type_h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_bin_x_type_h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_EBREAK: { + *op_count = 0; + break; + } + case RISCV_C_LI: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_li.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_li.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VEXT2TYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vext2type.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vext2type.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_AES64DSM: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64dsm.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64dsm.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64dsm.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FVVMATYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fvvmatype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.fvvmatype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fvvmatype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VVMSTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vvmstype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vvmstype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vvmstype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VROL_VV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vrol_vv.vs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vrol_vv.vs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vrol_vv.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_LOAD_FP: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.load_fp.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.load_fp.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.load_fp.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_BIN_TYPE_F_S: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_type_f_s.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_type_f_s.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_bin_type_f_s.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_WVVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.wvvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.wvvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.wvvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_AMO: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.amo.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.amo.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.amo.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SIG0H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig0h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig0h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig0h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_SLLI_HINT: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_slli_hint.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_slli_hint.rsd); + ops[1].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_VSRETYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsretype.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vsretype.vs3); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_RFVVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.rfvvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.rfvvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.rfvvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_SRLI: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_srli.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_srli.rsd); + ops[1].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_FCVTMOD_W_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fcvtmod_w_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fcvtmod_w_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ZBA_RTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zba_rtype.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zba_rtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zba_rtype.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FWVFTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fwvftype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.fwvftype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fwvftype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VWSLL_VI: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vwsll_vi.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.vwsll_vi.uimm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vwsll_vi.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VFUNARY1: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vfunary1.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vfunary1.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_MOVETYPEV: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.movetypev.vs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.movetypev.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VFWUNARY0: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vfwunary0.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vfwunary0.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VFNUNARY0: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vfnunary0.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vfnunary0.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_MV_HINT: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_mv_hint); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_C_FLDSP: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_fldsp.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.c_fldsp.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ZBB_RTYPEW: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbb_rtypew.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbb_rtypew.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbb_rtypew.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_SB: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_sb.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sb.rs1c); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sb.rs2c); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_FLI_S: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.riscv_fli_s.constantidx; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fli_s.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_AES64ESM: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64esm.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64esm.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64esm.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SIG0: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig0.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig0.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FENCE_TSO: { + *op_count = 0; + break; + } + case RISCV_C_EBREAK: { + *op_count = 0; + break; + } + case RISCV_REM: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rem.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rem.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rem.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_CLZW: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clzw.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clzw.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_RM_XF_TYPE_S: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_rm_xf_type_s.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_xf_type_s.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_RMVVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.rmvvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.rmvvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.rmvvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_JALR: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_jalr); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_STORE_FP: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.store_fp.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.store_fp.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.store_fp.rs1); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_F_BIN_X_TYPE_D: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_x_type_d.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_x_type_d.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_bin_x_type_d.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_AES64KS1I: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.aes64ks1i.rnum; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64ks1i.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64ks1i.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FWVVMATYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fwvvmatype.vs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.fwvvmatype.vs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fwvvmatype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SRET: { + *op_count = 0; + break; + } + case RISCV_C_BNEZ: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_bnez.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_bnez.rs); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_C_FSDSP: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_fsdsp.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.c_fsdsp.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_VCLMULH_VX: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vclmulh_vx.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vclmulh_vx.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vclmulh_vx.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VCPOP_V: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vcpop_v.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vcpop_v.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ZICOND_RTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zicond_rtype.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zicond_rtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zicond_rtype.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_MOVETYPEX: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.movetypex.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.movetypex.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_SINVAL_VMA: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sinval_vma.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sinval_vma.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_VSSEGTYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vssegtype.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vssegtype.vs3); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_F_BIN_RM_TYPE_S: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_s.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_s.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_s.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_RM_XF_TYPE_H: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_rm_xf_type_h.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_xf_type_h.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VVMCTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vvmctype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vvmctype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vvmctype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VBREV8_V: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vbrev8_v.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vbrev8_v.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_LUI_HINT: { + *op_count = 1; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_lui_hint; + ops[0].access = CS_AC_READ; + break; + } + case RISCV_FMINM_H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_STORE: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.store.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.store.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.store.rs1); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_C_FLWSP: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_flwsp.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.c_flwsp.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FENCE: { + *op_count = 0; + break; + } + case RISCV_VID_V: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vid_v.vd); + ops[0].access = CS_AC_WRITE; + break; + } + case RISCV_ZIMOP_MOP_R: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zimop_mop_r.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zimop_mop_r.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_XOR: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_xor.rsd); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_xor.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_ZBS_IOP: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.zbs_iop.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbs_iop.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbs_iop.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VCLZ_V: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vclz_v.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vclz_v.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_SHA256SUM0: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha256sum0.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha256sum0.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_F_TYPE_H: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_f_type_h.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_f_type_h.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FMAXM_H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VCLMUL_VV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vclmul_vv.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vclmul_vv.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vclmul_vv.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_ITYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.itype.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.itype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.itype.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_XPERM8: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_xperm8.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_xperm8.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_xperm8.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_CTZW: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_ctzw.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_ctzw.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FVFMATYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fvfmatype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.fvfmatype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fvfmatype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_LD: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_ld.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_ld.rsc); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_ld.rdc); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_ADDIW: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_addiw.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_addiw.rsd); + ops[1].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_MVVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.mvvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.mvvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.mvvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_ZBB_EXTOP: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbb_extop.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbb_extop.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_NOT: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_not); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_NXTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.nxtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.nxtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.nxtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_TYPE_X_S: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_type_x_s.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_type_x_s.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_JR: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_jr); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_SFENCE_W_INVAL: { + *op_count = 0; + break; + } + case RISCV_RORIW: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.riscv_roriw.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_roriw.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_roriw.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SM4KS: { + *op_count = 4; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.sm4ks.bs; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm4ks.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm4ks.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm4ks.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_ZICBOZ: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_zicboz); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_ZBB_RTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbb_rtype.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbb_rtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbb_rtype.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FROUNDNX_S: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_froundnx_s.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_froundnx_s.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FWVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fwvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.fwvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fwvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VFUNARY0: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vfunary0.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vfunary0.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_SUB: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sub.rsd); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sub.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_FWFTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fwftype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.fwftype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fwftype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_BIN_TYPE_X_S: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_type_x_s.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_type_x_s.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_bin_type_x_s.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_ZBS_RTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbs_rtype.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbs_rtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbs_rtype.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_SW: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_sw.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sw.rsc1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sw.rsc2); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_C_FSW: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_fsw.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_fsw.rsc1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_fsw.rsc2); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_CPOP: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_cpop.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_cpop.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VBREV_V: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vbrev_v.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vbrev_v.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_LDSP: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_ldsp.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_ldsp.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_WMVXTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.wmvxtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.wmvxtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.wmvxtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VROR_VI: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vror_vi.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.vror_vi.uimm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vror_vi.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SUM1: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum1.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum1.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_SEXT_H: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sext_h); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_ZIP: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_zip.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_zip.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VFMV: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.vfmv.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vfmv.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_REMW: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.remw.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.remw.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.remw.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_MADD_TYPE_S: { + *op_count = 4; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_s.rs3); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_s.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_s.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_s.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_C_ADD_HINT: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_add_hint); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_F_BIN_RM_TYPE_D: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_d.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_d.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_d.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SUM0R: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum0r.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum0r.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum0r.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_ZBA_RTYPEUW: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zba_rtypeuw.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zba_rtypeuw.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zba_rtypeuw.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FMINM_S: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_s.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_s.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_s.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SUM0: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum0.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum0.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ZCMOP: { + *op_count = 0; + break; + } + case RISCV_C_BEQZ: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_beqz.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_beqz.rs); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_SLLIUW: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.riscv_slliuw.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_slliuw.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_slliuw.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FMVH_X_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmvh_x_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fmvh_x_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_AES32ESI: { + *op_count = 4; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.aes32esi.bs; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32esi.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32esi.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32esi.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_C_J: { + *op_count = 1; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_j; + ops[0].access = CS_AC_READ; + break; + } + case RISCV_CTZ: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_ctz.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_ctz.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_LOADRES: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.loadres.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.loadres.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_RM_FF_TYPE_H: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_ff_type_h.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_ff_type_h.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VFMVFS: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vfmvfs.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.vfmvfs.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VIMTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vimtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.vimtype.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vimtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_MV: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_mv.rd); + ops[0].access = CS_AC_WRITE; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_mv.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_C_ZEXT_B: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_zext_b); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_VLRETYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vlretype.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vlretype.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_DIVW: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.divw.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.divw.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.divw.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_AES64IM: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64im.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64im.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_SHIFTIOP: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.shiftiop.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.shiftiop.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.shiftiop.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FMINM_D: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_d.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_d.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.riscv_fminm_d.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SM4ED: { + *op_count = 4; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.sm4ed.bs; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm4ed.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm4ed.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm4ed.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_SM3P0: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm3p0.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm3p0.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SIG0L: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig0l.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig0l.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig0l.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_CSRReg: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.csrreg.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.csrreg.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_ADDI16SP: { + *op_count = 1; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_addi16sp; + ops[0].access = CS_AC_READ; + break; + } + case RISCV_C_LWSP: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_lwsp.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_lwsp.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FWVFMATYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.fwvfmatype.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.fwvfmatype.vs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fwvfmatype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_LW: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_lw.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_lw.rsc); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_lw.rdc); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_OR: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_or.rsd); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_or.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_VEXT8TYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vext8type.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vext8type.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FLTQ_H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fltq_h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fltq_h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fltq_h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_MOVETYPEI: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.movetypei.vd); + ops[0].access = CS_AC_WRITE; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.movetypei.simm; + ops[1].access = CS_AC_READ; + break; + } + case RISCV_VFMVSF: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.vfmvsf.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vfmvsf.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_F_TYPE_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_f_type_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_f_type_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FROUNDNX_H: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_froundnx_h.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_froundnx_h.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FENCEI: { + *op_count = 0; + break; + } + case RISCV_F_MADD_TYPE_H: { + *op_count = 4; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_h.rs3); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_h.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_h.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_FLOAT_REG(tree->ast_node.f_madd_type_h.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_VXMTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vxmtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vxmtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vxmtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_AES32ESMI: { + *op_count = 4; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.aes32esmi.bs; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32esmi.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32esmi.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32esmi.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_C_SLLI: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_slli.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_slli.rsd); + ops[1].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_NISTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.nistype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.nistype.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.nistype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FROUND_S: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fround_s.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fround_s.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_NVSTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.nvstype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.nvstype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.nvstype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_STOP_FETCHING: { + *op_count = 0; + break; + } + case RISCV_F_BIN_F_TYPE_D: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_f_type_d.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_f_type_d.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_bin_f_type_d.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_AES64KS2: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64ks2.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64ks2.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64ks2.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_NVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.nvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.nvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.nvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SFENCE_VMA: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sfence_vma.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sfence_vma.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_C_JAL: { + *op_count = 1; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_jal; + ops[0].access = CS_AC_READ; + break; + } + case RISCV_FROUND_H: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fround_h.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fround_h.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VMTYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vmtype.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vmtype.vd_or_vs3); + ops[1].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_FWVVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fwvvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.fwvvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fwvvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_MVVCOMPRESS: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.mvvcompress.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.mvvcompress.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.mvvcompress.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_SH: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_sh.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sh.rs1c); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sh.rs2c); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_VSETVL: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsetvl.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsetvl.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsetvl.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VEXT4TYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vext4type.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vext4type.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_SUBW: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_subw.rsd); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_subw.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_MMTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.mmtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.mmtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.mmtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VXMCTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vxmctype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vxmctype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vxmctype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_NOP: { + *op_count = 0; + break; + } + case RISCV_C_SDSP: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_sdsp.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_sdsp.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_WVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.wvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.wvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.wvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VSOXSEGTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vsoxsegtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsoxsegtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vsoxsegtype.vs3); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_NXSTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.nxstype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.nxstype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.nxstype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_ANDI: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_andi.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_andi.rsd); + ops[1].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_VLSEGFFTYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vlsegfftype.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vlsegfftype.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_ILLEGAL: { + *op_count = 1; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_illegal; + ops[0].access = CS_AC_READ; + break; + } + case RISCV_FMAXM_S: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_s.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_s.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_s.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_WVXTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.wvxtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.wvxtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.wvxtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_MRET: { + *op_count = 0; + break; + } + case RISCV_F_UN_RM_FF_TYPE_S: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_ff_type_s.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_ff_type_s.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FLEQ_S: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fleq_s.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fleq_s.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fleq_s.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_ADDIW: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.addiw.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.addiw.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.addiw.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_CLMUL: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmul.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmul.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmul.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SM3P1: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm3p1.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sm3p1.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FVFMTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fvfmtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.fvfmtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fvfmtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_THREAD_START: { + *op_count = 0; + break; + } + case RISCV_C_MUL: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_mul.rsdc); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_mul.rs2c); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_MASKTYPEV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.masktypev.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.masktypev.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.masktypev.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VIMSTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vimstype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.vimstype.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vimstype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VIMCTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vimctype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.vimctype.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vimctype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_ORCB: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_orcb.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_orcb.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VMVSX: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vmvsx.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vmvsx.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FVVMTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fvvmtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.fvvmtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fvvmtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_RM_XF_TYPE_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_rm_xf_type_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_xf_type_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VCTZ_V: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vctz_v.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vctz_v.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ZBKB_PACKW: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbkb_packw.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbkb_packw.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbkb_packw.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VANDN_VX: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vandn_vx.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vandn_vx.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vandn_vx.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VSUXSEGTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vsuxsegtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsuxsegtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vsuxsegtype.vs3); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_SHA256SUM1: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha256sum1.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha256sum1.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_LI_HINT: { + *op_count = 1; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_li_hint; + ops[0].access = CS_AC_READ; + break; + } + case RISCV_C_SD: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_sd.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sd.rsc1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sd.rsc2); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_FMAXM_D: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_d.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_d.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.riscv_fmaxm_d.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_CPOPW: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_cpopw.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_cpopw.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FVVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fvvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.fvvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fvvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VSETIVLI: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.vsetivli.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsetivli.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_MASKTYPEI: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.masktypei.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.masktypei.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.masktypei.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FENCE_RESERVED: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.fence_reserved.fm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.fence_reserved.rs); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.fence_reserved.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FROUND_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fround_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fround_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FROUNDNX_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_froundnx_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_froundnx_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_MASKTYPEX: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.masktypex.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.masktypex.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.masktypex.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_ADDI_HINT: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_addi_hint); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_F_UN_RM_FX_TYPE_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_fx_type_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_rm_fx_type_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_FLI_D: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.riscv_fli_d.constantidx; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fli_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_MVXMATYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.mvxmatype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.mvxmatype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.mvxmatype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VVMTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vvmtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vvmtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vvmtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_WFI: { + *op_count = 0; + break; + } + case RISCV_FVFTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.fvftype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.fvftype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.fvftype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_ADD: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_add.rsd); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_add.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_NITYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.nitype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.nitype.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.nitype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SIG1: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig1.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig1.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ZICBOM: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_zicbom.rs1); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_VCLMUL_VX: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vclmul_vx.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vclmul_vx.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vclmul_vx.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_UNZIP: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_unzip.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_unzip.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_SHIFTIWOP: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.shiftiwop.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.shiftiwop.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.shiftiwop.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_FLD: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_fld.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_fld.rsc); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_fld.rdc); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VISG: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.visg.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.visg.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.visg.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_RM_FX_TYPE_H: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_fx_type_h.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_rm_fx_type_h.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_ZVKSHA2TYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.zvksha2type.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.zvksha2type.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.zvksha2type.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VWSLL_VX: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vwsll_vx.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vwsll_vx.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vwsll_vx.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_ZBKB_RTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbkb_rtype.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbkb_rtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.zbkb_rtype.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VMVXS: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vmvxs.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vmvxs.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VMVRTYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vmvrtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vmvrtype.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_STORECON: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.storecon.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.storecon.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.storecon.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VITYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vitype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_IMM; + ops[1].imm = tree->ast_node.vitype.simm; + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vitype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_FSWSP: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_fswsp.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.c_fswsp.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_F_UN_X_TYPE_D: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_x_type_d.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_x_type_d.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SUM1R: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum1r.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum1r.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sum1r.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VLUXSEGTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vluxsegtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vluxsegtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vluxsegtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_ECALL: { + *op_count = 0; + break; + } + case RISCV_C_SEXT_B: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_sext_b); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_JAL: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.riscv_jal.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_jal.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_RM_FX_TYPE_S: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_rm_fx_type_s.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_rm_fx_type_s.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_LHU: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_lhu.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_lhu.rdc); + ops[1].access = CS_AC_WRITE; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_lhu.rs1c); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_VSETVLI: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsetvli.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsetvli.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_F_BIN_RM_TYPE_H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_bin_rm_type_h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_F_UN_X_TYPE_H: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_un_x_type_h.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_x_type_h.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VXCMPTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vxcmptype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vxcmptype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vxcmptype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FLI_H: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.riscv_fli_h.constantidx; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fli_h.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_CLMULH: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmulh.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmulh.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmulh.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_UTYPE: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.utype.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.utype.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VXSG: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vxsg.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vxsg.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vxsg.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_CLZ: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clz.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clz.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VXMSTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vxmstype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vxmstype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vxmstype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VROR_VV: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vror_vv.vs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vror_vv.vs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vror_vv.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FLTQ_S: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fltq_s.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fltq_s.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fltq_s.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_CLMULR: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmulr.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmulr.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_clmulr.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SHA512SIG1H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig1h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig1h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.sha512sig1h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VROL_VX: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vrol_vx.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vrol_vx.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vrol_vx.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VIOTA_M: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.viota_m.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.viota_m.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VLSSEGTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vlssegtype.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vlssegtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vlssegtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_CSRImm: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.csrimm.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.csrimm.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_LOAD: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.load.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.load.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.load.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VMSIF_M: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vmsif_m.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vmsif_m.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VROR_VX: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vror_vx.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vror_vx.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vror_vx.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_BTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.btype.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.btype.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.btype.rs1); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_VXTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vxtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vxtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vxtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VSSSEGTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsssegtype.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vsssegtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vsssegtype.vs3); + ops[2].access = CS_AC_READ; + break; + } + case RISCV_RORI: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.riscv_rori.shamt; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_rori.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_rori.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_JALR: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.riscv_jalr.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_jalr.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_jalr.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_FLEQ_D: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.riscv_fleq_d.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.riscv_fleq_d.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_fleq_d.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_AES32DSI: { + *op_count = 4; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.aes32dsi.bs; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32dsi.rs2); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32dsi.rs1); + ops[2].access = CS_AC_READ; + ops[3].type = RISCV_OP_REG; + ops[3].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes32dsi.rd); + ops[3].access = CS_AC_WRITE; + break; + } + case RISCV_C_AND: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_and.rsd); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_and.rs2); + ops[1].access = CS_AC_READ; + break; + } + case RISCV_F_UN_TYPE_F_S: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.f_un_type_f_s.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_un_type_f_s.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_VMSOF_M: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vmsof_m.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vmsof_m.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_XPERM4: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_xperm4.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_xperm4.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_xperm4.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_SFENCE_INVAL_IR: { + *op_count = 0; + break; + } + case RISCV_C_ZEXT_W: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_zext_w); + ops[0].access = CS_AC_READ; + break; + } + case RISCV_F_BIN_F_TYPE_H: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_FLOAT_REG(tree->ast_node.f_bin_f_type_h.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.f_bin_f_type_h.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_FLOAT_REG(tree->ast_node.f_bin_f_type_h.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_MUL: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.mul.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.mul.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.mul.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_RIVVTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.rivvtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.rivvtype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.rivvtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VFMERGE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vfmerge.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_FLOAT_REG(tree->ast_node.vfmerge.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vfmerge.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_RTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rtype.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.rtype.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VLOXSEGTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vloxsegtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vloxsegtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.vloxsegtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_VMSBF_M: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vmsbf_m.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.vmsbf_m.vd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_ADDI: { + *op_count = 2; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_addi.nzi; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.c_addi.rsd); + ops[1].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_FENCEI_RESERVED: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.fencei_reserved.imm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.fencei_reserved.rs); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.fencei_reserved.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_AES64DS: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64ds.rs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64ds.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_GEN_PURPOSE_REG(tree->ast_node.aes64ds.rd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_MVVMATYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.mvvmatype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_VECTOR_REG(tree->ast_node.mvvmatype.vs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.mvvmatype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_SRLI_HINT: { + *op_count = 1; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_srli_hint); + ops[0].access = CS_AC_READ | CS_AC_WRITE; + break; + } + case RISCV_VFIRST_M: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.vfirst_m.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.vfirst_m.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_WXTYPE: { + *op_count = 3; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_VECTOR_REG(tree->ast_node.wxtype.vs2); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.wxtype.rs1); + ops[1].access = CS_AC_READ; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_VECTOR_REG(tree->ast_node.wxtype.vd); + ops[2].access = CS_AC_WRITE; + break; + } + case RISCV_C_NOP_HINT: { + *op_count = 1; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_nop_hint; + ops[0].access = CS_AC_READ; + break; + } + case RISCV_REV8: { + *op_count = 2; + ops[0].type = RISCV_OP_REG; + ops[0].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_rev8.rs1); + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_GEN_PURPOSE_REG(tree->ast_node.riscv_rev8.rd); + ops[1].access = CS_AC_WRITE; + break; + } + case RISCV_C_LH: { + *op_count = 3; + ops[0].type = RISCV_OP_IMM; + ops[0].imm = tree->ast_node.c_lh.uimm; + ops[0].access = CS_AC_READ; + ops[1].type = RISCV_OP_REG; + ops[1].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_lh.rdc); + ops[1].access = CS_AC_WRITE; + ops[2].type = RISCV_OP_REG; + ops[2].reg = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_lh.rs1c); + ops[2].access = CS_AC_READ; + break; + } + } +} +#endif diff --git a/arch/RISCV/RISCVOperandsHelpers.h b/arch/RISCV/RISCVOperandsHelpers.h new file mode 100644 index 0000000000..c51021593d --- /dev/null +++ b/arch/RISCV/RISCVOperandsHelpers.h @@ -0,0 +1,234 @@ +#ifndef __RISCV_OPERANDS_HELPERS_H__ +#define __RISCV_OPERANDS_HELPERS_H__ + +#include "../../include/capstone/capstone.h" +#include "RISCVAst.gen.inc" + +#include "RISCVRVContextHelpers.h" + +// Those macros are hand-written helpers to transform register values +// to the enum values exposed by the capstone module +// The generated disassembler uses 0..31 indices to refer to all registers of +// any type but the capstone module gives all the register flat sequential enum +// values i.e. enum {, = 34 && (r) <= 127 && ((r) % 3 == 1)) +#define INDEX_FROM_FLOAT_REG(r) (((r) - 34)/3) + +// and double enum values are 35, 38, 41, ... +#define AS_DOUBLE_REG(r) ((3 * (r)) + 35) +#define IS_DOUBLE_REG(r) ((r) >= 35 && (r) <= 128 && ((r) % 3 == 2)) +#define INDEX_FROM_DOUBLE_REG(r) (((r) - 35)/3) + +// vector registers are 129, ..., 160 +#define AS_VECTOR_REG(r) ((r) + 129) +#define IS_VECTOR_REG(r) ((r) >= 129) +#define INDEX_FROM_VECTOR_REG(r) ((r) - 129) + +#define AS_COMPRESSED_GEN_PURPOSE_REG(r) AS_GEN_PURPOSE_REG((r) + 8) +#define AS_COMPRESSED_FLOAT_REG(r) AS_FLOAT_REG((r) + 8) + +#define FLOAT_REG_TO_HALF_FLOAT_REG(r) ((r)-1) +#define FLOAT_REG_TO_DOUBLE_REG(r) ((r) + 1) + +// TODO: implement sign and zero extension as in the Sail stdlib +#define ZERO_EXTEND(i) (i) +#define SIGN_EXTEND(i) (i) + +// memory operands is harder to infer than register operands due to their +// deceptive apperance as regular immediates (who just happen to get added to +// base registers and result in addresses) +// +// For those instructions, we simply detect the relevant instruction and +// manually fill its operands +// This shouldn't be too hard, as the RISC-V is a riscv architecture that has +// dedicated instructions for accessing memory and it doesn't access memory +// outside of those instructions (unlike, say, x86) Additionally, some registers +// are inferred wrong for some special instructions, we also manually edit those +static inline void patch_operands(struct ast *tree, cs_riscv_op *ops, uint8_t *op_count, + RVContext *ctx) { + switch (tree->ast_node_type) { + case RISCV_LOADRES: { + // the read from rs1 is falsely inferred as a register read + // but it's actually a memory read with displacement 0 + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = AS_GEN_PURPOSE_REG(tree->ast_node.loadres.rs1); + ops[0].mem.disp = 0; + ops[0].access = CS_AC_READ; + break; + } + // same as loadres + case RISCV_STORECON: { + ops[1].type = RISCV_OP_MEM; + ops[1].mem.base = AS_GEN_PURPOSE_REG(tree->ast_node.storecon.rs1); + ops[1].mem.disp = 0; + ops[1].access = CS_AC_WRITE; + break; + } + // same as loadres + case RISCV_AMO: { + ops[1].type = RISCV_OP_MEM; + ops[1].mem.base = AS_GEN_PURPOSE_REG(tree->ast_node.amo.rs1); + ops[1].mem.disp = 0; + ops[1].access = CS_AC_READ; + break; + } + + // the immediate and rs1 are falsely inferred as an + // immediate operand and a register acccess + // correct them to a memory operand + case RISCV_LOAD: { + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = AS_GEN_PURPOSE_REG(tree->ast_node.load.rs1); + ops[0].mem.disp = SIGN_EXTEND(tree->ast_node.load.imm); + ops[0].access = CS_AC_READ; + // shift the destination operand + ops[1] = ops[2]; + *op_count = *op_count - 1; + break; + } + + case RISCV_STORE: { + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = AS_GEN_PURPOSE_REG(tree->ast_node.store.rs1); + ops[0].mem.disp = SIGN_EXTEND(tree->ast_node.store.imm); + ops[0].access = CS_AC_WRITE; + // no need to shift anything, ops[1] is already the third operand + // "delete" the false register operand containing rs1 + *op_count = *op_count - 1; + break; + } + + case RISCV_LOAD_FP: { + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = AS_GEN_PURPOSE_REG(tree->ast_node.load_fp.rs1); + ops[0].mem.disp = SIGN_EXTEND(tree->ast_node.load_fp.imm); + ops[0].access = CS_AC_READ; + // shift the destination operand + ops[1] = ops[2]; + *op_count = *op_count - 1; + break; + } + + case RISCV_STORE_FP: { + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = AS_GEN_PURPOSE_REG(tree->ast_node.store_fp.rs1); + ops[0].mem.disp = SIGN_EXTEND(tree->ast_node.store_fp.imm); + ops[0].access = CS_AC_WRITE; + // no need to shift anything, ops[1] is already the third operand + // "delete" the false register operand containing rs1 + *op_count = *op_count - 1; + break; + } + + // TODO: figure out a more detailed way of representing this instructions' addressing mode + case RISCV_ZICBOZ: + case RISCV_ZICBOM: + case RISCV_VLSEGTYPE: + case RISCV_VLSEGFFTYPE: + case RISCV_VSSEGTYPE: + case RISCV_VLSSEGTYPE: + case RISCV_VSSSEGTYPE: + case RISCV_VLUXSEGTYPE: + case RISCV_VLOXSEGTYPE: + case RISCV_VSUXSEGTYPE: + case RISCV_VLRETYPE: + case RISCV_VSRETYPE: + case RISCV_VMTYPE: { + // for now we just give up and say that the offset is unknown, + // but it's possible to write parameters for a symbolic formula for each instruction type + // (for example if an instructions performs memory accesses according to the formula a*X+b, we could + // a, b, and the lower and upper bounds for X are assembly-time parameters that could be extracted) + for (uint32_t i = 0; i < *op_count; i++) { + if (ops[i].type == RISCV_OP_MEM) { + ops[i].mem.type = RISCV_OP_MEM_RUNTIME; + } + } + break; + } + + default: break; + } + + // fix up special compressed instructions, which are assumed by the generator + // to always reference integer registers + // this assumption is mostly true, but few reference FP registers, + // and some also have memory operands + uint8_t sp = AS_GEN_PURPOSE_REG(2); // sp register + switch (tree->ast_node_type) { + // short synonym for a LOAD_FP with base sp + case RISCV_C_FLDSP: { + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = sp; + ops[0].mem.disp = SIGN_EXTEND(ZERO_EXTEND(tree->ast_node.c_fldsp.uimm << 3)); + ops[0].access = CS_AC_READ; + break; + } + // short synonym for a STORE_FP with base sp + case RISCV_C_FSDSP: { + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = sp; + ops[0].mem.disp = SIGN_EXTEND(ZERO_EXTEND(tree->ast_node.c_fsdsp.uimm << 3)); + ops[0].access = CS_AC_WRITE; + break; + } + + // short synonyms for arbitrary loads and stores + case RISCV_C_FLD: { + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_fld.rsc); + ops[0].mem.disp = SIGN_EXTEND(ZERO_EXTEND(tree->ast_node.c_fld.uimm << 3)); + ops[0].access = CS_AC_READ; + ops[1] = ops[2]; + ops[1].reg = AS_COMPRESSED_FLOAT_REG(tree->ast_node.c_fld.rdc); + *op_count = *op_count - 1; + break; + } + + case RISCV_C_FSD: { + ops[0].type = RISCV_OP_MEM; + ops[0].mem.base = AS_COMPRESSED_GEN_PURPOSE_REG(tree->ast_node.c_fsd.rsc1); + ops[0].mem.disp = SIGN_EXTEND(ZERO_EXTEND(tree->ast_node.c_fsd.uimm << 3)); + ops[0].access = CS_AC_WRITE; + ops[1] = ops[2]; + ops[1].reg = AS_COMPRESSED_FLOAT_REG(tree->ast_node.c_fsd.rsc2); + *op_count = *op_count - 1; + break; + } + default: break; + } + + // determine if the instruction has float operands but the FP width is 16 bits + // or 64 bits, in which case the FP register is patched up to the double or + // half-float equivalent + if (ctx->flen == 16 || ctx->flen == 64) { + for (uint32_t i = 0; i < *op_count; i++) { + if (ops[i].type == RISCV_OP_REG && IS_FLOAT_REG(ops[i].reg)) { + ops[i].reg = (ctx->flen == 16) ? FLOAT_REG_TO_HALF_FLOAT_REG(ops[i].reg) + : FLOAT_REG_TO_DOUBLE_REG(ops[i].reg); + } + } + } +} + +#endif \ No newline at end of file diff --git a/arch/RISCV/RISCVPrinter.c b/arch/RISCV/RISCVPrinter.c new file mode 100644 index 0000000000..2a40fc41c7 --- /dev/null +++ b/arch/RISCV/RISCVPrinter.c @@ -0,0 +1,14 @@ +#include "RISCVPrinter.h" +#include "RISCVAst2Str.gen.inc" + +void riscv_printer(MCInst *MI, SStream *OS, void *info) { + struct ast instruction; + + RVContext ctx; + riscv_init_riscv_context(&ctx); + + CS_ASSERT(sizeof(struct ast) < 160); + memcpy(&instruction, MI->flat_insn->op_str, sizeof(struct ast)); + + ast2str(&instruction, OS, &ctx); +} \ No newline at end of file diff --git a/arch/RISCV/RISCVPrinter.h b/arch/RISCV/RISCVPrinter.h new file mode 100644 index 0000000000..1dcbd2b42a --- /dev/null +++ b/arch/RISCV/RISCVPrinter.h @@ -0,0 +1,11 @@ +#ifndef __RISCV_PRINTER__H_ +#define __RISCV_PRINTER__H_ + +#include "../../cs_priv.h" + +#include "RISCVRVContextHelpers.h" +#include "RISCVHelpers.h" + +void riscv_printer(MCInst *MI, SStream *OS, void *info); + +#endif \ No newline at end of file diff --git a/arch/RISCV/RISCVRVContextHelpers.h b/arch/RISCV/RISCVRVContextHelpers.h new file mode 100644 index 0000000000..84751f69b0 --- /dev/null +++ b/arch/RISCV/RISCVRVContextHelpers.h @@ -0,0 +1,86 @@ +#ifndef __RISCV_CONTEXT_H__ +#define __RISCV_CONTEXT_H__ + +#include +#include + +// MISA fields +#define MISA_A (1UL << 0) // Atomic extension +#define MISA_B (1UL << 1) // Bit-Manipulation extension (tentative) +#define MISA_C (1UL << 2) // Compressed extension +#define MISA_D (1UL << 3) // Double-precision FP +#define MISA_E (1UL << 4) // RV32E base ISA +#define MISA_F (1UL << 5) // Single-precision FP +#define MISA_G (1UL << 6) // Reserved +#define MISA_H (1UL << 7) // Hypervisor extension +#define MISA_I (1UL << 8) // RV32I/64I/128I base ISA +#define MISA_J (1UL << 9) // Dynamically Translated Languages (tentative) +#define MISA_K (1UL << 10) // Reserved +#define MISA_L (1UL << 11) // Reserved +#define MISA_M (1UL << 12) // Multiply/Divide extension +#define MISA_N (1UL << 13) // User-Level Interrupts (tentative) +#define MISA_O (1UL << 14) // Reserved +#define MISA_P (1UL << 15) // Packed-SIMD (tentative) +#define MISA_Q (1UL << 16) // Quad-precision FP +#define MISA_R (1UL << 17) // Reserved +#define MISA_S (1UL << 18) // Supervisor mode +#define MISA_T (1UL << 19) // Reserved +#define MISA_U (1UL << 20) // User mode +#define MISA_V (1UL << 21) // Vector extension (tentative) +#define MISA_W (1UL << 22) // Reserved +#define MISA_X (1UL << 23) // Non-standard extensions +#define MISA_Y (1UL << 24) // Reserved +#define MISA_Z (1UL << 25) // Reserved + +#define MISA(e) (ctx->misa & MISA_##e) + +// MStatus fields +#define MSTATUS_SD_64 (1ULL << 63) +#define MSTATUS_MBE (1ULL << 37) +#define MSTATUS_SBE (1ULL << 36) +#define MSTATUS_SXL (3ULL << 34) +#define MSTATUS_UXL (3ULL << 32) +#define MSTATUS_SD_32 (1ULL << 31) +#define MSTATUS_TSR (1ULL << 22) +#define MSTATUS_TW (1ULL << 21) +#define MSTATUS_TVM (1ULL << 20) +#define MSTATUS_MXR (1ULL << 19) +#define MSTATUS_SUM (1ULL << 18) +#define MSTATUS_MPRV (1ULL << 17) +#define MSTATUS_XS (3ULL << 15) +#define MSTATUS_FS (3ULL << 13) +#define MSTATUS_MPP (3ULL << 11) +#define MSTATUS_VS (3ULL << 9) +#define MSTATUS_SPP (1ULL << 8) +#define MSTATUS_MPIE (1ULL << 7) +#define MSTATUS_SPIE (1ULL << 5) +#define MSTATUS_MIE (1ULL << 3) +#define MSTATUS_SIE (1ULL << 1) + +#define MSTATUS(e) (ctx->mstatus & MSTATUS_##e) + +#define VTYPE_VSEW (7ULL << 3) +#define VTYPE_VLMUL (7ULL << 0) + +#define VTYPE(e) (ctx->vtype & VTYPE_##e) + +typedef struct RVContext { + uint16_t xlen; + uint16_t xlen_bytes; + uint16_t flen; + + uint32_t misa; + uint64_t mstatus; + uint64_t extensionsSupported; + + uint64_t vtype; + uint64_t vl; + uint16_t vstart; + uint32_t vlen; + + // constants + uint8_t zreg; + uint8_t sp; +} RVContext; + +#endif \ No newline at end of file diff --git a/include/capstone/riscv.h b/include/capstone/riscv.h index 09b8fedd3b..074c56f240 100644 --- a/include/capstone/riscv.h +++ b/include/capstone/riscv.h @@ -14,7 +14,6 @@ extern "C" { #endif #include "platform.h" - // GCC MIPS toolchain has a default macro called "mips" which breaks // compilation //#undef riscv @@ -31,9 +30,16 @@ typedef enum riscv_op_type { RISCV_OP_MEM, // = CS_OP_MEM (Memory operand). } riscv_op_type; +typedef enum riscv_op_mem_type { + RISCV_OP_MEM_CONST = 0, // by default + // offset is a runtime value, and the constant displacement is invalid + RISCV_OP_MEM_RUNTIME +} riscv_op_mem_type; + // Instruction's operand referring to memory // This is associated with RISCV_OP_MEM operand type above typedef struct riscv_op_mem { + riscv_op_mem_type type; unsigned int base; // base register int64_t disp; // displacement/offset value } riscv_op_mem; @@ -132,353 +138,1192 @@ typedef enum riscv_reg { RISCV_REG_T6 = RISCV_REG_X31, // "t6" //> Floating-point registers + RISCV_REG_F0_16, // "ft0" RISCV_REG_F0_32, // "ft0" RISCV_REG_F0_64, // "ft0" + RISCV_REG_F1_16, // "ft1" RISCV_REG_F1_32, // "ft1" RISCV_REG_F1_64, // "ft1" + RISCV_REG_F2_16, // "ft2" RISCV_REG_F2_32, // "ft2" RISCV_REG_F2_64, // "ft2" + RISCV_REG_F3_16, // "ft3" RISCV_REG_F3_32, // "ft3" RISCV_REG_F3_64, // "ft3" + RISCV_REG_F4_16, // "ft4" RISCV_REG_F4_32, // "ft4" RISCV_REG_F4_64, // "ft4" + RISCV_REG_F5_16, // "ft5" RISCV_REG_F5_32, // "ft5" RISCV_REG_F5_64, // "ft5" + RISCV_REG_F6_16, // "ft6" RISCV_REG_F6_32, // "ft6" RISCV_REG_F6_64, // "ft6" + RISCV_REG_F7_16, // "ft7" RISCV_REG_F7_32, // "ft7" RISCV_REG_F7_64, // "ft7" + RISCV_REG_F8_16, // "fs0" RISCV_REG_F8_32, // "fs0" RISCV_REG_F8_64, // "fs0" + RISCV_REG_F9_16, // "fs1" RISCV_REG_F9_32, // "fs1" RISCV_REG_F9_64, // "fs1" + RISCV_REG_F10_16, // "fa0" RISCV_REG_F10_32, // "fa0" RISCV_REG_F10_64, // "fa0" + RISCV_REG_F11_16, // "fa1" RISCV_REG_F11_32, // "fa1" RISCV_REG_F11_64, // "fa1" + RISCV_REG_F12_16, // "fa2" RISCV_REG_F12_32, // "fa2" RISCV_REG_F12_64, // "fa2" + RISCV_REG_F13_16, // "fa3" RISCV_REG_F13_32, // "fa3" RISCV_REG_F13_64, // "fa3" + RISCV_REG_F14_16, // "fa4" RISCV_REG_F14_32, // "fa4" RISCV_REG_F14_64, // "fa4" + RISCV_REG_F15_16, // "fa5" RISCV_REG_F15_32, // "fa5" RISCV_REG_F15_64, // "fa5" + RISCV_REG_F16_16, // "fa6" RISCV_REG_F16_32, // "fa6" RISCV_REG_F16_64, // "fa6" + RISCV_REG_F17_16, // "fa7" RISCV_REG_F17_32, // "fa7" RISCV_REG_F17_64, // "fa7" + RISCV_REG_F18_16, // "fs2" RISCV_REG_F18_32, // "fs2" RISCV_REG_F18_64, // "fs2" + RISCV_REG_F19_16, // "fs3" RISCV_REG_F19_32, // "fs3" RISCV_REG_F19_64, // "fs3" + RISCV_REG_F20_16, // "fs4" RISCV_REG_F20_32, // "fs4" RISCV_REG_F20_64, // "fs4" + RISCV_REG_F21_16, // "fs5" RISCV_REG_F21_32, // "fs5" RISCV_REG_F21_64, // "fs5" + RISCV_REG_F22_16, // "fs6" RISCV_REG_F22_32, // "fs6" RISCV_REG_F22_64, // "fs6" + RISCV_REG_F23_16, // "fs7" RISCV_REG_F23_32, // "fs7" RISCV_REG_F23_64, // "fs7" + RISCV_REG_F24_16, // "fs8" RISCV_REG_F24_32, // "fs8" RISCV_REG_F24_64, // "fs8" + RISCV_REG_F25_16, // "fs9" RISCV_REG_F25_32, // "fs9" RISCV_REG_F25_64, // "fs9" + RISCV_REG_F26_16, // "fs10" RISCV_REG_F26_32, // "fs10" RISCV_REG_F26_64, // "fs10" + RISCV_REG_F27_16, // "fs11" RISCV_REG_F27_32, // "fs11" RISCV_REG_F27_64, // "fs11" + RISCV_REG_F28_16, // "ft8" RISCV_REG_F28_32, // "ft8" RISCV_REG_F28_64, // "ft8" + RISCV_REG_F29_16, // "ft9" RISCV_REG_F29_32, // "ft9" RISCV_REG_F29_64, // "ft9" + RISCV_REG_F30_16, // "ft10" RISCV_REG_F30_32, // "ft10" RISCV_REG_F30_64, // "ft10" + RISCV_REG_F31_16, // "ft11" RISCV_REG_F31_32, // "ft11" RISCV_REG_F31_64, // "ft11" - + + RISCV_REG_V0, + RISCV_REG_V1, + RISCV_REG_V2, + RISCV_REG_V3, + RISCV_REG_V4, + RISCV_REG_V5, + RISCV_REG_V6, + RISCV_REG_V7, + RISCV_REG_V8, + RISCV_REG_V9, + RISCV_REG_V10, + RISCV_REG_V11, + RISCV_REG_V12, + RISCV_REG_V13, + RISCV_REG_V14, + RISCV_REG_V15, + RISCV_REG_V16, + RISCV_REG_V17, + RISCV_REG_V18, + RISCV_REG_V19, + RISCV_REG_V20, + RISCV_REG_V21, + RISCV_REG_V22, + RISCV_REG_V23, + RISCV_REG_V24, + RISCV_REG_V25, + RISCV_REG_V26, + RISCV_REG_V27, + RISCV_REG_V28, + RISCV_REG_V29, + RISCV_REG_V30, + RISCV_REG_V31, + RISCV_REG_ENDING, // <-- mark the end of the list or registers } riscv_reg; //> RISCV instruction -typedef enum riscv_insn { - RISCV_INS_INVALID = 0, +/*=======================================================================*/ +/* This code was generated by the tool auto-sync-sail*/ +/* (see https://github.com/rizinorg/capstone-autosync-sail)*/ +/* from the sail model of RISC-V*/ +/* (see https://github.com/riscv/sail-riscv) @ version + * dc1155266a1cb6ba2342162601739881b58a1c4e.*/ +/* DO NOT MODIFY THIS CODE MANUALLY. ANY MANUAL EDITS ARE OVERWRITTEN.*/ +/* ------------------------------------------------------------------- */ +/* Copyright © 2024-2025 moste00 */ +/* SPDX-License-Identifier: BSD-3-Clause*/ +/*=======================================================================*/ - RISCV_INS_ADD, - RISCV_INS_ADDI, - RISCV_INS_ADDIW, - RISCV_INS_ADDW, - RISCV_INS_AMOADD_D, - RISCV_INS_AMOADD_D_AQ, - RISCV_INS_AMOADD_D_AQ_RL, - RISCV_INS_AMOADD_D_RL, - RISCV_INS_AMOADD_W, - RISCV_INS_AMOADD_W_AQ, - RISCV_INS_AMOADD_W_AQ_RL, - RISCV_INS_AMOADD_W_RL, - RISCV_INS_AMOAND_D, - RISCV_INS_AMOAND_D_AQ, - RISCV_INS_AMOAND_D_AQ_RL, - RISCV_INS_AMOAND_D_RL, - RISCV_INS_AMOAND_W, - RISCV_INS_AMOAND_W_AQ, - RISCV_INS_AMOAND_W_AQ_RL, - RISCV_INS_AMOAND_W_RL, - RISCV_INS_AMOMAXU_D, - RISCV_INS_AMOMAXU_D_AQ, - RISCV_INS_AMOMAXU_D_AQ_RL, - RISCV_INS_AMOMAXU_D_RL, - RISCV_INS_AMOMAXU_W, - RISCV_INS_AMOMAXU_W_AQ, - RISCV_INS_AMOMAXU_W_AQ_RL, - RISCV_INS_AMOMAXU_W_RL, - RISCV_INS_AMOMAX_D, - RISCV_INS_AMOMAX_D_AQ, - RISCV_INS_AMOMAX_D_AQ_RL, - RISCV_INS_AMOMAX_D_RL, - RISCV_INS_AMOMAX_W, - RISCV_INS_AMOMAX_W_AQ, - RISCV_INS_AMOMAX_W_AQ_RL, - RISCV_INS_AMOMAX_W_RL, - RISCV_INS_AMOMINU_D, - RISCV_INS_AMOMINU_D_AQ, - RISCV_INS_AMOMINU_D_AQ_RL, - RISCV_INS_AMOMINU_D_RL, - RISCV_INS_AMOMINU_W, - RISCV_INS_AMOMINU_W_AQ, - RISCV_INS_AMOMINU_W_AQ_RL, - RISCV_INS_AMOMINU_W_RL, - RISCV_INS_AMOMIN_D, - RISCV_INS_AMOMIN_D_AQ, - RISCV_INS_AMOMIN_D_AQ_RL, - RISCV_INS_AMOMIN_D_RL, - RISCV_INS_AMOMIN_W, - RISCV_INS_AMOMIN_W_AQ, - RISCV_INS_AMOMIN_W_AQ_RL, - RISCV_INS_AMOMIN_W_RL, - RISCV_INS_AMOOR_D, - RISCV_INS_AMOOR_D_AQ, - RISCV_INS_AMOOR_D_AQ_RL, - RISCV_INS_AMOOR_D_RL, - RISCV_INS_AMOOR_W, - RISCV_INS_AMOOR_W_AQ, - RISCV_INS_AMOOR_W_AQ_RL, - RISCV_INS_AMOOR_W_RL, - RISCV_INS_AMOSWAP_D, - RISCV_INS_AMOSWAP_D_AQ, - RISCV_INS_AMOSWAP_D_AQ_RL, - RISCV_INS_AMOSWAP_D_RL, - RISCV_INS_AMOSWAP_W, - RISCV_INS_AMOSWAP_W_AQ, - RISCV_INS_AMOSWAP_W_AQ_RL, - RISCV_INS_AMOSWAP_W_RL, - RISCV_INS_AMOXOR_D, - RISCV_INS_AMOXOR_D_AQ, - RISCV_INS_AMOXOR_D_AQ_RL, - RISCV_INS_AMOXOR_D_RL, - RISCV_INS_AMOXOR_W, - RISCV_INS_AMOXOR_W_AQ, - RISCV_INS_AMOXOR_W_AQ_RL, - RISCV_INS_AMOXOR_W_RL, - RISCV_INS_AND, - RISCV_INS_ANDI, - RISCV_INS_AUIPC, - RISCV_INS_BEQ, - RISCV_INS_BGE, - RISCV_INS_BGEU, - RISCV_INS_BLT, - RISCV_INS_BLTU, - RISCV_INS_BNE, - RISCV_INS_CSRRC, - RISCV_INS_CSRRCI, - RISCV_INS_CSRRS, - RISCV_INS_CSRRSI, - RISCV_INS_CSRRW, - RISCV_INS_CSRRWI, - RISCV_INS_C_ADD, - RISCV_INS_C_ADDI, - RISCV_INS_C_ADDI16SP, - RISCV_INS_C_ADDI4SPN, - RISCV_INS_C_ADDIW, - RISCV_INS_C_ADDW, - RISCV_INS_C_AND, - RISCV_INS_C_ANDI, - RISCV_INS_C_BEQZ, - RISCV_INS_C_BNEZ, - RISCV_INS_C_EBREAK, - RISCV_INS_C_FLD, - RISCV_INS_C_FLDSP, - RISCV_INS_C_FLW, - RISCV_INS_C_FLWSP, - RISCV_INS_C_FSD, - RISCV_INS_C_FSDSP, - RISCV_INS_C_FSW, - RISCV_INS_C_FSWSP, - RISCV_INS_C_J, - RISCV_INS_C_JAL, - RISCV_INS_C_JALR, - RISCV_INS_C_JR, - RISCV_INS_C_LD, - RISCV_INS_C_LDSP, - RISCV_INS_C_LI, - RISCV_INS_C_LUI, - RISCV_INS_C_LW, - RISCV_INS_C_LWSP, - RISCV_INS_C_MV, - RISCV_INS_C_NOP, - RISCV_INS_C_OR, - RISCV_INS_C_SD, - RISCV_INS_C_SDSP, - RISCV_INS_C_SLLI, - RISCV_INS_C_SRAI, - RISCV_INS_C_SRLI, - RISCV_INS_C_SUB, - RISCV_INS_C_SUBW, - RISCV_INS_C_SW, - RISCV_INS_C_SWSP, - RISCV_INS_C_UNIMP, - RISCV_INS_C_XOR, - RISCV_INS_DIV, - RISCV_INS_DIVU, - RISCV_INS_DIVUW, - RISCV_INS_DIVW, - RISCV_INS_EBREAK, - RISCV_INS_ECALL, - RISCV_INS_FADD_D, - RISCV_INS_FADD_S, - RISCV_INS_FCLASS_D, - RISCV_INS_FCLASS_S, - RISCV_INS_FCVT_D_L, - RISCV_INS_FCVT_D_LU, - RISCV_INS_FCVT_D_S, - RISCV_INS_FCVT_D_W, - RISCV_INS_FCVT_D_WU, - RISCV_INS_FCVT_LU_D, - RISCV_INS_FCVT_LU_S, - RISCV_INS_FCVT_L_D, - RISCV_INS_FCVT_L_S, - RISCV_INS_FCVT_S_D, - RISCV_INS_FCVT_S_L, - RISCV_INS_FCVT_S_LU, - RISCV_INS_FCVT_S_W, - RISCV_INS_FCVT_S_WU, - RISCV_INS_FCVT_WU_D, - RISCV_INS_FCVT_WU_S, - RISCV_INS_FCVT_W_D, - RISCV_INS_FCVT_W_S, - RISCV_INS_FDIV_D, - RISCV_INS_FDIV_S, - RISCV_INS_FENCE, - RISCV_INS_FENCE_I, - RISCV_INS_FENCE_TSO, - RISCV_INS_FEQ_D, - RISCV_INS_FEQ_S, - RISCV_INS_FLD, - RISCV_INS_FLE_D, - RISCV_INS_FLE_S, - RISCV_INS_FLT_D, - RISCV_INS_FLT_S, - RISCV_INS_FLW, - RISCV_INS_FMADD_D, - RISCV_INS_FMADD_S, - RISCV_INS_FMAX_D, - RISCV_INS_FMAX_S, - RISCV_INS_FMIN_D, - RISCV_INS_FMIN_S, - RISCV_INS_FMSUB_D, - RISCV_INS_FMSUB_S, - RISCV_INS_FMUL_D, - RISCV_INS_FMUL_S, - RISCV_INS_FMV_D_X, - RISCV_INS_FMV_W_X, - RISCV_INS_FMV_X_D, - RISCV_INS_FMV_X_W, - RISCV_INS_FNMADD_D, - RISCV_INS_FNMADD_S, - RISCV_INS_FNMSUB_D, - RISCV_INS_FNMSUB_S, - RISCV_INS_FSD, - RISCV_INS_FSGNJN_D, - RISCV_INS_FSGNJN_S, - RISCV_INS_FSGNJX_D, - RISCV_INS_FSGNJX_S, - RISCV_INS_FSGNJ_D, - RISCV_INS_FSGNJ_S, - RISCV_INS_FSQRT_D, - RISCV_INS_FSQRT_S, - RISCV_INS_FSUB_D, - RISCV_INS_FSUB_S, - RISCV_INS_FSW, - RISCV_INS_JAL, - RISCV_INS_JALR, - RISCV_INS_LB, - RISCV_INS_LBU, - RISCV_INS_LD, - RISCV_INS_LH, - RISCV_INS_LHU, - RISCV_INS_LR_D, - RISCV_INS_LR_D_AQ, - RISCV_INS_LR_D_AQ_RL, - RISCV_INS_LR_D_RL, - RISCV_INS_LR_W, - RISCV_INS_LR_W_AQ, - RISCV_INS_LR_W_AQ_RL, - RISCV_INS_LR_W_RL, - RISCV_INS_LUI, - RISCV_INS_LW, - RISCV_INS_LWU, - RISCV_INS_MRET, - RISCV_INS_MUL, - RISCV_INS_MULH, - RISCV_INS_MULHSU, - RISCV_INS_MULHU, - RISCV_INS_MULW, - RISCV_INS_OR, - RISCV_INS_ORI, - RISCV_INS_REM, - RISCV_INS_REMU, - RISCV_INS_REMUW, - RISCV_INS_REMW, - RISCV_INS_SB, - RISCV_INS_SC_D, - RISCV_INS_SC_D_AQ, - RISCV_INS_SC_D_AQ_RL, - RISCV_INS_SC_D_RL, - RISCV_INS_SC_W, - RISCV_INS_SC_W_AQ, - RISCV_INS_SC_W_AQ_RL, - RISCV_INS_SC_W_RL, - RISCV_INS_SD, - RISCV_INS_SFENCE_VMA, - RISCV_INS_SH, - RISCV_INS_SLL, - RISCV_INS_SLLI, - RISCV_INS_SLLIW, - RISCV_INS_SLLW, - RISCV_INS_SLT, - RISCV_INS_SLTI, - RISCV_INS_SLTIU, - RISCV_INS_SLTU, - RISCV_INS_SRA, - RISCV_INS_SRAI, - RISCV_INS_SRAIW, - RISCV_INS_SRAW, - RISCV_INS_SRET, - RISCV_INS_SRL, - RISCV_INS_SRLI, - RISCV_INS_SRLIW, - RISCV_INS_SRLW, - RISCV_INS_SUB, - RISCV_INS_SUBW, - RISCV_INS_SW, - RISCV_INS_UNIMP, - RISCV_INS_URET, - RISCV_INS_WFI, - RISCV_INS_XOR, - RISCV_INS_XORI, - - RISCV_INS_ENDING, -} riscv_insn; +#ifndef __RISCVINSN_GEN_INC__ +#define __RISCVINSN_GEN_INC__ +#include +#include +#include + +enum riscv_insn { + //--------------------- RISCV_REV8--------------------- + RISCV_INSN_REV8, + //--------------------- RISCV_WXTYPE--------------------- + RISCV_INSN_WX_VSUBU, + RISCV_INSN_WX_VSUB, + RISCV_INSN_WX_VADDU, + RISCV_INSN_WX_VADD, + //--------------------- RISCV_C_SRLI_HINT--------------------- + RISCV_INSN_C_SRLI_HINT, + //--------------------- RISCV_AES64DS--------------------- + RISCV_INSN_AES64DS, + //--------------------- RISCV_VMSBF_M--------------------- + RISCV_INSN_VMSBF_M, + //--------------------- RISCV_RTYPE--------------------- + RISCV_INSN_XOR, + RISCV_INSN_SUB, + RISCV_INSN_SRL, + RISCV_INSN_SRA, + RISCV_INSN_SLTU, + RISCV_INSN_SLT, + RISCV_INSN_SLL, + RISCV_INSN_OR, + RISCV_INSN_AND, + RISCV_INSN_ADD, + //--------------------- RISCV_VFMERGE--------------------- + RISCV_INSN_VFMERGE, + //--------------------- RISCV_RIVVTYPE--------------------- + RISCV_INSN_IVV_VWREDSUMU, + RISCV_INSN_IVV_VWREDSUM, + //--------------------- RISCV_F_BIN_F_TYPE_H--------------------- + RISCV_INSN_FSGNJ_H, + RISCV_INSN_FSGNJX_H, + RISCV_INSN_FSGNJN_H, + RISCV_INSN_FMIN_H, + RISCV_INSN_FMAX_H, + //--------------------- RISCV_C_ZEXT_W--------------------- + RISCV_INSN_C_ZEXT_W, + //--------------------- RISCV_SFENCE_INVAL_IR--------------------- + RISCV_INSN_SFENCE_INVAL_IR, + //--------------------- RISCV_XPERM4--------------------- + RISCV_INSN_XPERM4, + //--------------------- RISCV_F_UN_TYPE_F_S--------------------- + RISCV_INSN_FMV_W_X, + //--------------------- RISCV_C_AND--------------------- + RISCV_INSN_C_AND, + //--------------------- RISCV_AES32DSI--------------------- + RISCV_INSN_AES32DSI, + //--------------------- RISCV_RORI--------------------- + RISCV_INSN_RORI, + //--------------------- RISCV_JALR--------------------- + RISCV_INSN_JALR, + //--------------------- RISCV_VMSIF_M--------------------- + RISCV_INSN_VMSIF_M, + //--------------------- RISCV_CSRImm--------------------- + RISCV_INSN_CSRRW, + RISCV_INSN_CSRRS, + RISCV_INSN_CSRRC, + //--------------------- RISCV_VLSSEGTYPE--------------------- + RISCV_INSN_VLSSEGTYPE, + //--------------------- RISCV_SHA512SIG1H--------------------- + RISCV_INSN_SHA512SIG1H, + //--------------------- RISCV_FLTQ_S--------------------- + RISCV_INSN_FLTQ_S, + //--------------------- RISCV_VXSG--------------------- + RISCV_INSN_VX_VSLIDEUP, + RISCV_INSN_VX_VSLIDEDOWN, + RISCV_INSN_VX_VRGATHER, + //--------------------- RISCV_VXCMPTYPE--------------------- + RISCV_INSN_VXCMP_VMSNE, + RISCV_INSN_VXCMP_VMSLTU, + RISCV_INSN_VXCMP_VMSLT, + RISCV_INSN_VXCMP_VMSLEU, + RISCV_INSN_VXCMP_VMSLE, + RISCV_INSN_VXCMP_VMSGTU, + RISCV_INSN_VXCMP_VMSGT, + RISCV_INSN_VXCMP_VMSEQ, + //--------------------- RISCV_C_LHU--------------------- + RISCV_INSN_C_LHU, + //--------------------- RISCV_F_UN_RM_FX_TYPE_S--------------------- + RISCV_INSN_FCVT_W_S, + RISCV_INSN_FCVT_WU_S, + RISCV_INSN_FCVT_L_S, + RISCV_INSN_FCVT_LU_S, + //--------------------- RISCV_JAL--------------------- + RISCV_INSN_JAL, + //--------------------- RISCV_ECALL--------------------- + RISCV_INSN_ECALL, + //--------------------- RISCV_F_UN_X_TYPE_D--------------------- + RISCV_INSN_FMV_X_D, + RISCV_INSN_FCLASS_D, + //--------------------- RISCV_C_FSWSP--------------------- + RISCV_INSN_C_FSWSP, + //--------------------- RISCV_VMVXS--------------------- + RISCV_INSN_VMVXS, + //--------------------- RISCV_ZVKSHA2TYPE--------------------- + RISCV_INSN_ZVK_VSHA2CL, + RISCV_INSN_ZVK_VSHA2CH, + //--------------------- RISCV_C_FLD--------------------- + RISCV_INSN_C_FLD, + //--------------------- RISCV_SHIFTIWOP--------------------- + RISCV_INSN_SRLIW, + RISCV_INSN_SRAIW, + RISCV_INSN_SLLIW, + //--------------------- RISCV_UNZIP--------------------- + RISCV_INSN_UNZIP, + //--------------------- RISCV_ZICBOM--------------------- + RISCV_INSN_CBO_INVAL, + RISCV_INSN_CBO_FLUSH, + RISCV_INSN_CBO_CLEAN, + //--------------------- RISCV_SHA512SIG1--------------------- + RISCV_INSN_SHA512SIG1, + //--------------------- RISCV_NITYPE--------------------- + RISCV_INSN_NI_VNCLIPU, + RISCV_INSN_NI_VNCLIP, + //--------------------- RISCV_WFI--------------------- + RISCV_INSN_WFI, + //--------------------- RISCV_VVMTYPE--------------------- + RISCV_INSN_VVM_VMSBC, + RISCV_INSN_VVM_VMADC, + //--------------------- RISCV_MVXMATYPE--------------------- + RISCV_INSN_MVX_VNMSUB, + RISCV_INSN_MVX_VNMSAC, + RISCV_INSN_MVX_VMADD, + RISCV_INSN_MVX_VMACC, + //--------------------- RISCV_FLI_D--------------------- + RISCV_INSN_FLI_D, + //--------------------- RISCV_C_ADDI_HINT--------------------- + RISCV_INSN_C_ADDI_HINT, + //--------------------- RISCV_MASKTYPEX--------------------- + RISCV_INSN_MASKTYPEX, + //--------------------- RISCV_FROUNDNX_D--------------------- + RISCV_INSN_FROUNDNX_D, + //--------------------- RISCV_FROUND_D--------------------- + RISCV_INSN_FROUND_D, + //--------------------- RISCV_VSETIVLI--------------------- + RISCV_INSN_VSETIVLI, + //--------------------- RISCV_FMAXM_D--------------------- + RISCV_INSN_FMAXM_D, + //--------------------- RISCV_C_SD--------------------- + RISCV_INSN_C_SD, + //--------------------- RISCV_ZBKB_PACKW--------------------- + RISCV_INSN_ZBKB_PACKW, + //--------------------- RISCV_FVVMTYPE--------------------- + RISCV_INSN_FVVM_VMFNE, + RISCV_INSN_FVVM_VMFLT, + RISCV_INSN_FVVM_VMFLE, + RISCV_INSN_FVVM_VMFEQ, + //--------------------- RISCV_VMVSX--------------------- + RISCV_INSN_VMVSX, + //--------------------- RISCV_ORCB--------------------- + RISCV_INSN_ORCB, + //--------------------- RISCV_C_MUL--------------------- + RISCV_INSN_C_MUL, + //--------------------- RISCV_SM3P1--------------------- + RISCV_INSN_SM3P1, + //--------------------- RISCV_CLMUL--------------------- + RISCV_INSN_CLMUL, + //--------------------- RISCV_FLEQ_S--------------------- + RISCV_INSN_FLEQ_S, + //--------------------- RISCV_F_UN_RM_FF_TYPE_S--------------------- + RISCV_INSN_FSQRT_S, + //--------------------- RISCV_WVXTYPE--------------------- + RISCV_INSN_WVX_VWMULU, + RISCV_INSN_WVX_VWMULSU, + RISCV_INSN_WVX_VWMUL, + RISCV_INSN_WVX_VSUBU, + RISCV_INSN_WVX_VSUB, + RISCV_INSN_WVX_VADDU, + RISCV_INSN_WVX_VADD, + //--------------------- RISCV_FMAXM_S--------------------- + RISCV_INSN_FMAXM_S, + //--------------------- RISCV_C_ILLEGAL--------------------- + RISCV_INSN_C_ILLEGAL, + //--------------------- RISCV_NXSTYPE--------------------- + RISCV_INSN_NXS_VNSRL, + RISCV_INSN_NXS_VNSRA, + //--------------------- RISCV_VSOXSEGTYPE--------------------- + RISCV_INSN_VSOXSEGTYPE, + //--------------------- RISCV_C_NOP--------------------- + RISCV_INSN_C_NOP, + //--------------------- RISCV_VXMCTYPE--------------------- + RISCV_INSN_VXMC_VMSBC, + RISCV_INSN_VXMC_VMADC, + //--------------------- RISCV_MMTYPE--------------------- + RISCV_INSN_MM_VMXOR, + RISCV_INSN_MM_VMXNOR, + RISCV_INSN_MM_VMORN, + RISCV_INSN_MM_VMOR, + RISCV_INSN_MM_VMNOR, + RISCV_INSN_MM_VMNAND, + RISCV_INSN_MM_VMANDN, + RISCV_INSN_MM_VMAND, + //--------------------- RISCV_NVTYPE--------------------- + RISCV_INSN_NV_VNCLIPU, + RISCV_INSN_NV_VNCLIP, + //--------------------- RISCV_AES64KS2--------------------- + RISCV_INSN_AES64KS2, + //--------------------- RISCV_F_BIN_F_TYPE_D--------------------- + RISCV_INSN_FSGNJ_D, + RISCV_INSN_FSGNJX_D, + RISCV_INSN_FSGNJN_D, + RISCV_INSN_FMIN_D, + RISCV_INSN_FMAX_D, + //--------------------- RISCV_AES32ESMI--------------------- + RISCV_INSN_AES32ESMI, + //--------------------- RISCV_F_MADD_TYPE_H--------------------- + RISCV_INSN_FNMSUB_H, + RISCV_INSN_FNMADD_H, + RISCV_INSN_FMSUB_H, + RISCV_INSN_FMADD_H, + //--------------------- RISCV_FROUNDNX_H--------------------- + RISCV_INSN_FROUNDNX_H, + //--------------------- RISCV_MOVETYPEI--------------------- + RISCV_INSN_MOVETYPEI, + //--------------------- RISCV_FLTQ_H--------------------- + RISCV_INSN_FLTQ_H, + //--------------------- RISCV_C_LW--------------------- + RISCV_INSN_C_LW, + //--------------------- RISCV_C_LWSP--------------------- + RISCV_INSN_C_LWSP, + //--------------------- RISCV_C_ADDI16SP--------------------- + RISCV_INSN_C_ADDI16SP, + //--------------------- RISCV_CSRReg--------------------- + + //--------------------- RISCV_SHA512SIG0L--------------------- + RISCV_INSN_SHA512SIG0L, + //--------------------- RISCV_SM3P0--------------------- + RISCV_INSN_SM3P0, + //--------------------- RISCV_SM4ED--------------------- + RISCV_INSN_SM4ED, + //--------------------- RISCV_FMINM_D--------------------- + RISCV_INSN_FMINM_D, + //--------------------- RISCV_AES64IM--------------------- + RISCV_INSN_AES64IM, + //--------------------- RISCV_VLRETYPE--------------------- + RISCV_INSN_VLRETYPE, + //--------------------- RISCV_VFMVFS--------------------- + RISCV_INSN_VFMVFS, + //--------------------- RISCV_CTZ--------------------- + RISCV_INSN_CTZ, + //--------------------- RISCV_FMVH_X_D--------------------- + RISCV_INSN_FMVH_X_D, + //--------------------- RISCV_SLLIUW--------------------- + RISCV_INSN_SLLIUW, + //--------------------- RISCV_ZCMOP--------------------- + RISCV_INSN_ZCMOP, + //--------------------- RISCV_FMINM_S--------------------- + RISCV_INSN_FMINM_S, + //--------------------- RISCV_ZBA_RTYPEUW--------------------- + RISCV_INSN_SH3ADDUW, + RISCV_INSN_SH2ADDUW, + RISCV_INSN_SH1ADDUW, + RISCV_INSN_ADDUW, + //--------------------- RISCV_F_BIN_RM_TYPE_D--------------------- + RISCV_INSN_FSUB_D, + RISCV_INSN_FMUL_D, + RISCV_INSN_FDIV_D, + RISCV_INSN_FADD_D, + //--------------------- RISCV_C_ADD_HINT--------------------- + RISCV_INSN_C_ADD_HINT, + //--------------------- RISCV_F_MADD_TYPE_S--------------------- + RISCV_INSN_FNMSUB_S, + RISCV_INSN_FNMADD_S, + RISCV_INSN_FMSUB_S, + RISCV_INSN_FMADD_S, + //--------------------- RISCV_ZIP--------------------- + RISCV_INSN_ZIP, + //--------------------- RISCV_SHA512SUM1--------------------- + RISCV_INSN_SHA512SUM1, + //--------------------- RISCV_VROR_VI--------------------- + RISCV_INSN_VROR_VI, + //--------------------- RISCV_C_LDSP--------------------- + RISCV_INSN_C_LDSP, + //--------------------- RISCV_VBREV_V--------------------- + RISCV_INSN_VBREV_V, + //--------------------- RISCV_CPOP--------------------- + RISCV_INSN_CPOP, + //--------------------- RISCV_FWFTYPE--------------------- + RISCV_INSN_FWF_VSUB, + RISCV_INSN_FWF_VADD, + //--------------------- RISCV_FWVTYPE--------------------- + RISCV_INSN_FWV_VSUB, + RISCV_INSN_FWV_VADD, + //--------------------- RISCV_ZBB_RTYPE--------------------- + RISCV_INSN_XNOR, + RISCV_INSN_ROR, + RISCV_INSN_ROL, + RISCV_INSN_ORN, + RISCV_INSN_MINU, + RISCV_INSN_MIN, + RISCV_INSN_MAXU, + RISCV_INSN_MAX, + RISCV_INSN_ANDN, + //--------------------- RISCV_SM4KS--------------------- + RISCV_INSN_SM4KS, + //--------------------- RISCV_RORIW--------------------- + RISCV_INSN_RORIW, + //--------------------- RISCV_F_UN_TYPE_X_S--------------------- + RISCV_INSN_FMV_X_W, + RISCV_INSN_FCLASS_S, + //--------------------- RISCV_NXTYPE--------------------- + RISCV_INSN_NX_VNCLIPU, + RISCV_INSN_NX_VNCLIP, + //--------------------- RISCV_C_ADDIW--------------------- + RISCV_INSN_C_ADDIW, + //--------------------- RISCV_C_LD--------------------- + RISCV_INSN_C_LD, + //--------------------- RISCV_CTZW--------------------- + RISCV_INSN_CTZW, + //--------------------- RISCV_XPERM8--------------------- + RISCV_INSN_XPERM8, + //--------------------- RISCV_ITYPE--------------------- + RISCV_INSN_XORI, + RISCV_INSN_SLTIU, + RISCV_INSN_SLTI, + RISCV_INSN_ORI, + RISCV_INSN_ANDI, + RISCV_INSN_ADDI, + //--------------------- RISCV_VCLMUL_VV--------------------- + RISCV_INSN_VCLMUL_VV, + //--------------------- RISCV_F_UN_F_TYPE_H--------------------- + RISCV_INSN_FMV_H_X, + //--------------------- RISCV_VCLZ_V--------------------- + RISCV_INSN_VCLZ_V, + //--------------------- RISCV_VID_V--------------------- + RISCV_INSN_VID_V, + //--------------------- RISCV_FENCE--------------------- + RISCV_INSN_FENCE, + //--------------------- RISCV_C_FLWSP--------------------- + RISCV_INSN_C_FLWSP, + //--------------------- RISCV_STORE--------------------- + RISCV_INSN_STORE, + //--------------------- RISCV_VBREV8_V--------------------- + RISCV_INSN_VBREV8_V, + //--------------------- RISCV_VSSEGTYPE--------------------- + RISCV_INSN_VSSEGTYPE, + //--------------------- RISCV_ZICOND_RTYPE--------------------- + RISCV_INSN_CZERO_NEZ, + RISCV_INSN_CZERO_EQZ, + //--------------------- RISCV_VCLMULH_VX--------------------- + RISCV_INSN_VCLMULH_VX, + //--------------------- RISCV_C_FSDSP--------------------- + RISCV_INSN_C_FSDSP, + //--------------------- RISCV_SRET--------------------- + RISCV_INSN_SRET, + //--------------------- RISCV_STORE_FP--------------------- + RISCV_INSN_STORE_FP, + //--------------------- RISCV_C_JALR--------------------- + RISCV_INSN_C_JALR, + //--------------------- RISCV_FENCE_TSO--------------------- + RISCV_INSN_FENCE_TSO, + //--------------------- RISCV_SHA512SIG0--------------------- + RISCV_INSN_SHA512SIG0, + //--------------------- RISCV_FLI_S--------------------- + RISCV_INSN_FLI_S, + //--------------------- RISCV_C_SB--------------------- + RISCV_INSN_C_SB, + //--------------------- RISCV_ZBB_RTYPEW--------------------- + RISCV_INSN_RORW, + RISCV_INSN_ROLW, + //--------------------- RISCV_C_FLDSP--------------------- + RISCV_INSN_C_FLDSP, + //--------------------- RISCV_C_MV_HINT--------------------- + RISCV_INSN_C_MV_HINT, + //--------------------- RISCV_VWSLL_VI--------------------- + RISCV_INSN_VWSLL_VI, + //--------------------- RISCV_FCVTMOD_W_D--------------------- + RISCV_INSN_FCVTMOD_W_D, + //--------------------- RISCV_RFVVTYPE--------------------- + RISCV_INSN_FVV_VFWREDUSUM, + RISCV_INSN_FVV_VFWREDOSUM, + RISCV_INSN_FVV_VFREDUSUM, + RISCV_INSN_FVV_VFREDOSUM, + RISCV_INSN_FVV_VFREDMIN, + RISCV_INSN_FVV_VFREDMAX, + //--------------------- RISCV_SHA512SIG0H--------------------- + RISCV_INSN_SHA512SIG0H, + //--------------------- RISCV_AMO--------------------- + RISCV_INSN_AMOXOR, + RISCV_INSN_AMOSWAP, + RISCV_INSN_AMOOR, + RISCV_INSN_AMOMINU, + RISCV_INSN_AMOMIN, + RISCV_INSN_AMOMAXU, + RISCV_INSN_AMOMAX, + RISCV_INSN_AMOAND, + RISCV_INSN_AMOADD, + //--------------------- RISCV_LOAD_FP--------------------- + RISCV_INSN_LOAD_FP, + //--------------------- RISCV_VROL_VV--------------------- + RISCV_INSN_VROL_VV, + //--------------------- RISCV_VVMSTYPE--------------------- + RISCV_INSN_VVMS_VSBC, + RISCV_INSN_VVMS_VADC, + //--------------------- RISCV_FVVMATYPE--------------------- + RISCV_INSN_FVV_VNMSUB, + RISCV_INSN_FVV_VNMSAC, + RISCV_INSN_FVV_VNMADD, + RISCV_INSN_FVV_VNMACC, + RISCV_INSN_FVV_VMSUB, + RISCV_INSN_FVV_VMSAC, + RISCV_INSN_FVV_VMADD, + RISCV_INSN_FVV_VMACC, + //--------------------- RISCV_VEXT2TYPE--------------------- + RISCV_INSN_VEXT2_ZVF2, + RISCV_INSN_VEXT2_SVF2, + //--------------------- RISCV_EBREAK--------------------- + RISCV_INSN_EBREAK, + //--------------------- RISCV_C_LUI--------------------- + RISCV_INSN_C_LUI, + //--------------------- RISCV_F_MADD_TYPE_D--------------------- + RISCV_INSN_FNMSUB_D, + RISCV_INSN_FNMADD_D, + RISCV_INSN_FMSUB_D, + RISCV_INSN_FMADD_D, + //--------------------- RISCV_C_ZEXT_H--------------------- + RISCV_INSN_C_ZEXT_H, + //--------------------- RISCV_SHA512SIG1L--------------------- + RISCV_INSN_SHA512SIG1L, + //--------------------- RISCV_VLSEGTYPE--------------------- + RISCV_INSN_VLSEGTYPE, + //--------------------- RISCV_SHA256SIG0--------------------- + RISCV_INSN_SHA256SIG0, + //--------------------- RISCV_ZIMOP_MOP_RR--------------------- + RISCV_INSN_ZIMOP_MOP_RR, + //--------------------- RISCV_C_ADDI4SPN--------------------- + RISCV_INSN_C_ADDI4SPN, + //--------------------- RISCV_VVTYPE--------------------- + RISCV_INSN_VV_VXOR, + RISCV_INSN_VV_VSUB, + RISCV_INSN_VV_VSSUBU, + RISCV_INSN_VV_VSSUB, + RISCV_INSN_VV_VSSRL, + RISCV_INSN_VV_VSSRA, + RISCV_INSN_VV_VSRL, + RISCV_INSN_VV_VSRA, + RISCV_INSN_VV_VSMUL, + RISCV_INSN_VV_VSLL, + RISCV_INSN_VV_VSADDU, + RISCV_INSN_VV_VSADD, + RISCV_INSN_VV_VRGATHEREI16, + RISCV_INSN_VV_VRGATHER, + RISCV_INSN_VV_VOR, + RISCV_INSN_VV_VMINU, + RISCV_INSN_VV_VMIN, + RISCV_INSN_VV_VMAXU, + RISCV_INSN_VV_VMAX, + RISCV_INSN_VV_VAND, + RISCV_INSN_VV_VADD, + //--------------------- RISCV_VSHA2MS_VV--------------------- + RISCV_INSN_VSHA2MS_VV, + //--------------------- RISCV_FLEQ_H--------------------- + RISCV_INSN_FLEQ_H, + //--------------------- RISCV_VICMPTYPE--------------------- + RISCV_INSN_VICMP_VMSNE, + RISCV_INSN_VICMP_VMSLEU, + RISCV_INSN_VICMP_VMSLE, + RISCV_INSN_VICMP_VMSGTU, + RISCV_INSN_VICMP_VMSGT, + RISCV_INSN_VICMP_VMSEQ, + //--------------------- RISCV_C_FLW--------------------- + RISCV_INSN_C_FLW, + //--------------------- RISCV_C_SWSP--------------------- + RISCV_INSN_C_SWSP, + //--------------------- RISCV_FLTQ_D--------------------- + RISCV_INSN_FLTQ_D, + //--------------------- RISCV_AES64ES--------------------- + RISCV_INSN_AES64ES, + //--------------------- RISCV_C_SRAI_HINT--------------------- + RISCV_INSN_C_SRAI_HINT, + //--------------------- RISCV_DIV--------------------- + RISCV_INSN_DIV, + //--------------------- RISCV_C_LH--------------------- + RISCV_INSN_C_LH, + //--------------------- RISCV_C_NOP_HINT--------------------- + RISCV_INSN_C_NOP_HINT, + //--------------------- RISCV_VFIRST_M--------------------- + RISCV_INSN_VFIRST_M, + //--------------------- RISCV_MVVMATYPE--------------------- + RISCV_INSN_MVV_VNMSUB, + RISCV_INSN_MVV_VNMSAC, + RISCV_INSN_MVV_VMADD, + RISCV_INSN_MVV_VMACC, + //--------------------- RISCV_FENCEI_RESERVED--------------------- + RISCV_INSN_FENCEI_RESERVED, + //--------------------- RISCV_C_ADDI--------------------- + RISCV_INSN_C_ADDI, + //--------------------- RISCV_VLOXSEGTYPE--------------------- + RISCV_INSN_VLOXSEGTYPE, + //--------------------- RISCV_MUL--------------------- + RISCV_INSN_MUL, + //--------------------- RISCV_VMSOF_M--------------------- + RISCV_INSN_VMSOF_M, + //--------------------- RISCV_FLEQ_D--------------------- + RISCV_INSN_FLEQ_D, + //--------------------- RISCV_VSSSEGTYPE--------------------- + RISCV_INSN_VSSSEGTYPE, + //--------------------- RISCV_VXTYPE--------------------- + RISCV_INSN_VX_VXOR, + RISCV_INSN_VX_VSUB, + RISCV_INSN_VX_VSSUBU, + RISCV_INSN_VX_VSSUB, + RISCV_INSN_VX_VSSRL, + RISCV_INSN_VX_VSSRA, + RISCV_INSN_VX_VSRL, + RISCV_INSN_VX_VSRA, + RISCV_INSN_VX_VSMUL, + RISCV_INSN_VX_VSLL, + RISCV_INSN_VX_VSADDU, + RISCV_INSN_VX_VSADD, + RISCV_INSN_VX_VRSUB, + RISCV_INSN_VX_VOR, + RISCV_INSN_VX_VMINU, + RISCV_INSN_VX_VMIN, + RISCV_INSN_VX_VMAXU, + RISCV_INSN_VX_VMAX, + RISCV_INSN_VX_VAND, + RISCV_INSN_VX_VADD, + //--------------------- RISCV_BTYPE--------------------- + RISCV_INSN_BNE, + RISCV_INSN_BLTU, + RISCV_INSN_BLT, + RISCV_INSN_BGEU, + RISCV_INSN_BGE, + RISCV_INSN_BEQ, + //--------------------- RISCV_VROR_VX--------------------- + RISCV_INSN_VROR_VX, + //--------------------- RISCV_LOAD--------------------- + RISCV_INSN_LOAD, + //--------------------- RISCV_VIOTA_M--------------------- + RISCV_INSN_VIOTA_M, + //--------------------- RISCV_VROL_VX--------------------- + RISCV_INSN_VROL_VX, + //--------------------- RISCV_CLMULR--------------------- + RISCV_INSN_CLMULR, + //--------------------- RISCV_VROR_VV--------------------- + RISCV_INSN_VROR_VV, + //--------------------- RISCV_VXMSTYPE--------------------- + RISCV_INSN_VXMS_VSBC, + RISCV_INSN_VXMS_VADC, + //--------------------- RISCV_CLZ--------------------- + RISCV_INSN_CLZ, + //--------------------- RISCV_UTYPE--------------------- + RISCV_INSN_LUI, + RISCV_INSN_AUIPC, + //--------------------- RISCV_CLMULH--------------------- + RISCV_INSN_CLMULH, + //--------------------- RISCV_FLI_H--------------------- + RISCV_INSN_FLI_H, + //--------------------- RISCV_F_UN_X_TYPE_H--------------------- + RISCV_INSN_FMV_X_H, + RISCV_INSN_FCLASS_H, + //--------------------- RISCV_F_BIN_RM_TYPE_H--------------------- + RISCV_INSN_FSUB_H, + RISCV_INSN_FMUL_H, + RISCV_INSN_FDIV_H, + RISCV_INSN_FADD_H, + //--------------------- RISCV_VSETVLI--------------------- + RISCV_INSN_VSETVLI, + //--------------------- RISCV_C_SEXT_B--------------------- + RISCV_INSN_C_SEXT_B, + //--------------------- RISCV_VLUXSEGTYPE--------------------- + RISCV_INSN_VLUXSEGTYPE, + //--------------------- RISCV_SHA512SUM1R--------------------- + RISCV_INSN_SHA512SUM1R, + //--------------------- RISCV_VITYPE--------------------- + RISCV_INSN_VI_VXOR, + RISCV_INSN_VI_VSSRL, + RISCV_INSN_VI_VSSRA, + RISCV_INSN_VI_VSRL, + RISCV_INSN_VI_VSRA, + RISCV_INSN_VI_VSLL, + RISCV_INSN_VI_VSADDU, + RISCV_INSN_VI_VSADD, + RISCV_INSN_VI_VRSUB, + RISCV_INSN_VI_VOR, + RISCV_INSN_VI_VAND, + RISCV_INSN_VI_VADD, + //--------------------- RISCV_STORECON--------------------- + RISCV_INSN_STORECON, + //--------------------- RISCV_VMVRTYPE--------------------- + RISCV_INSN_VMVRTYPE, + //--------------------- RISCV_ZBKB_RTYPE--------------------- + RISCV_INSN_PACKH, + RISCV_INSN_PACK, + //--------------------- RISCV_VWSLL_VX--------------------- + RISCV_INSN_VWSLL_VX, + //--------------------- RISCV_F_UN_RM_FX_TYPE_H--------------------- + RISCV_INSN_FCVT_W_H, + RISCV_INSN_FCVT_WU_H, + RISCV_INSN_FCVT_L_H, + RISCV_INSN_FCVT_LU_H, + //--------------------- RISCV_VISG--------------------- + RISCV_INSN_VI_VSLIDEUP, + RISCV_INSN_VI_VSLIDEDOWN, + RISCV_INSN_VI_VRGATHER, + //--------------------- RISCV_VCLMUL_VX--------------------- + RISCV_INSN_VCLMUL_VX, + //--------------------- RISCV_C_ADD--------------------- + RISCV_INSN_C_ADD, + //--------------------- RISCV_FVFTYPE--------------------- + RISCV_INSN_VF_VSUB, + RISCV_INSN_VF_VSLIDE1UP, + RISCV_INSN_VF_VSLIDE1DOWN, + RISCV_INSN_VF_VSGNJX, + RISCV_INSN_VF_VSGNJN, + RISCV_INSN_VF_VSGNJ, + RISCV_INSN_VF_VRSUB, + RISCV_INSN_VF_VRDIV, + RISCV_INSN_VF_VMUL, + RISCV_INSN_VF_VMIN, + RISCV_INSN_VF_VMAX, + RISCV_INSN_VF_VDIV, + RISCV_INSN_VF_VADD, + //--------------------- RISCV_F_UN_RM_FX_TYPE_D--------------------- + RISCV_INSN_FCVT_W_D, + RISCV_INSN_FCVT_WU_D, + RISCV_INSN_FCVT_L_D, + RISCV_INSN_FCVT_LU_D, + //--------------------- RISCV_FENCE_RESERVED--------------------- + RISCV_INSN_FENCE_RESERVED, + //--------------------- RISCV_MASKTYPEI--------------------- + RISCV_INSN_MASKTYPEI, + //--------------------- RISCV_FVVTYPE--------------------- + RISCV_INSN_FVV_VSUB, + RISCV_INSN_FVV_VSGNJX, + RISCV_INSN_FVV_VSGNJN, + RISCV_INSN_FVV_VSGNJ, + RISCV_INSN_FVV_VMUL, + RISCV_INSN_FVV_VMIN, + RISCV_INSN_FVV_VMAX, + RISCV_INSN_FVV_VDIV, + RISCV_INSN_FVV_VADD, + //--------------------- RISCV_CPOPW--------------------- + RISCV_INSN_CPOPW, + //--------------------- RISCV_C_LI_HINT--------------------- + RISCV_INSN_C_LI_HINT, + //--------------------- RISCV_SHA256SUM1--------------------- + RISCV_INSN_SHA256SUM1, + //--------------------- RISCV_VSUXSEGTYPE--------------------- + RISCV_INSN_VSUXSEGTYPE, + //--------------------- RISCV_VANDN_VX--------------------- + RISCV_INSN_VANDN_VX, + //--------------------- RISCV_VCTZ_V--------------------- + RISCV_INSN_VCTZ_V, + //--------------------- RISCV_F_UN_RM_XF_TYPE_D--------------------- + RISCV_INSN_FCVT_D_WU, + RISCV_INSN_FCVT_D_W, + RISCV_INSN_FCVT_D_LU, + RISCV_INSN_FCVT_D_L, + //--------------------- RISCV_VIMCTYPE--------------------- + RISCV_INSN_VIMC_VMADC, + //--------------------- RISCV_VIMSTYPE--------------------- + RISCV_INSN_VIMS_VADC, + //--------------------- RISCV_MASKTYPEV--------------------- + RISCV_INSN_MASKTYPEV, + //--------------------- RISCV_THREAD_START--------------------- + RISCV_INSN_THREAD_START, + //--------------------- RISCV_FVFMTYPE--------------------- + RISCV_INSN_VFM_VMFNE, + RISCV_INSN_VFM_VMFLT, + RISCV_INSN_VFM_VMFLE, + RISCV_INSN_VFM_VMFGT, + RISCV_INSN_VFM_VMFGE, + RISCV_INSN_VFM_VMFEQ, + //--------------------- RISCV_ADDIW--------------------- + RISCV_INSN_ADDIW, + //--------------------- RISCV_MRET--------------------- + RISCV_INSN_MRET, + //--------------------- RISCV_VLSEGFFTYPE--------------------- + RISCV_INSN_VLSEGFFTYPE, + //--------------------- RISCV_C_ANDI--------------------- + RISCV_INSN_C_ANDI, + //--------------------- RISCV_WVTYPE--------------------- + RISCV_INSN_WV_VSUBU, + RISCV_INSN_WV_VSUB, + RISCV_INSN_WV_VADDU, + RISCV_INSN_WV_VADD, + //--------------------- RISCV_C_SDSP--------------------- + RISCV_INSN_C_SDSP, + //--------------------- RISCV_C_SUBW--------------------- + RISCV_INSN_C_SUBW, + //--------------------- RISCV_VEXT4TYPE--------------------- + RISCV_INSN_VEXT4_ZVF4, + RISCV_INSN_VEXT4_SVF4, + //--------------------- RISCV_VSETVL--------------------- + RISCV_INSN_VSETVL, + //--------------------- RISCV_C_SH--------------------- + RISCV_INSN_C_SH, + //--------------------- RISCV_MVVCOMPRESS--------------------- + RISCV_INSN_MVVCOMPRESS, + //--------------------- RISCV_FWVVTYPE--------------------- + RISCV_INSN_FWVV_VSUB, + RISCV_INSN_FWVV_VMUL, + RISCV_INSN_FWVV_VADD, + //--------------------- RISCV_VMTYPE--------------------- + RISCV_INSN_VSM, + RISCV_INSN_VLM, + //--------------------- RISCV_FROUND_H--------------------- + RISCV_INSN_FROUND_H, + //--------------------- RISCV_C_JAL--------------------- + RISCV_INSN_C_JAL, + //--------------------- RISCV_SFENCE_VMA--------------------- + RISCV_INSN_SFENCE_VMA, + //--------------------- RISCV_STOP_FETCHING--------------------- + RISCV_INSN_STOP_FETCHING, + //--------------------- RISCV_NVSTYPE--------------------- + RISCV_INSN_NVS_VNSRL, + RISCV_INSN_NVS_VNSRA, + //--------------------- RISCV_FROUND_S--------------------- + RISCV_INSN_FROUND_S, + //--------------------- RISCV_NISTYPE--------------------- + RISCV_INSN_NIS_VNSRL, + RISCV_INSN_NIS_VNSRA, + //--------------------- RISCV_C_SLLI--------------------- + RISCV_INSN_C_SLLI, + //--------------------- RISCV_VXMTYPE--------------------- + RISCV_INSN_VXM_VMSBC, + RISCV_INSN_VXM_VMADC, + //--------------------- RISCV_FENCEI--------------------- + RISCV_INSN_FENCEI, + //--------------------- RISCV_F_UN_F_TYPE_D--------------------- + RISCV_INSN_FMV_D_X, + //--------------------- RISCV_VFMVSF--------------------- + RISCV_INSN_VFMVSF, + //--------------------- RISCV_VEXT8TYPE--------------------- + RISCV_INSN_VEXT8_ZVF8, + RISCV_INSN_VEXT8_SVF8, + //--------------------- RISCV_C_OR--------------------- + RISCV_INSN_C_OR, + //--------------------- RISCV_FWVFMATYPE--------------------- + RISCV_INSN_FWVF_VNMSAC, + RISCV_INSN_FWVF_VNMACC, + RISCV_INSN_FWVF_VMSAC, + RISCV_INSN_FWVF_VMACC, + //--------------------- RISCV_SHIFTIOP--------------------- + RISCV_INSN_SRLI, + RISCV_INSN_SRAI, + RISCV_INSN_SLLI, + //--------------------- RISCV_DIVW--------------------- + RISCV_INSN_DIVW, + //--------------------- RISCV_C_ZEXT_B--------------------- + RISCV_INSN_C_ZEXT_B, + //--------------------- RISCV_C_MV--------------------- + RISCV_INSN_C_MV, + //--------------------- RISCV_VIMTYPE--------------------- + RISCV_INSN_VIM_VMADC, + //--------------------- RISCV_F_UN_RM_FF_TYPE_H--------------------- + RISCV_INSN_FSQRT_H, + RISCV_INSN_FCVT_S_H, + RISCV_INSN_FCVT_H_S, + RISCV_INSN_FCVT_H_D, + RISCV_INSN_FCVT_D_H, + //--------------------- RISCV_LOADRES--------------------- + RISCV_INSN_LOADRES, + //--------------------- RISCV_C_J--------------------- + RISCV_INSN_C_J, + //--------------------- RISCV_AES32ESI--------------------- + RISCV_INSN_AES32ESI, + //--------------------- RISCV_C_BEQZ--------------------- + RISCV_INSN_C_BEQZ, + //--------------------- RISCV_SHA512SUM0--------------------- + RISCV_INSN_SHA512SUM0, + //--------------------- RISCV_SHA512SUM0R--------------------- + RISCV_INSN_SHA512SUM0R, + //--------------------- RISCV_REMW--------------------- + RISCV_INSN_REMW, + //--------------------- RISCV_VFMV--------------------- + RISCV_INSN_VFMV, + //--------------------- RISCV_C_SEXT_H--------------------- + RISCV_INSN_C_SEXT_H, + //--------------------- RISCV_WMVXTYPE--------------------- + RISCV_INSN_WMVX_VWMACCUS, + RISCV_INSN_WMVX_VWMACCU, + RISCV_INSN_WMVX_VWMACCSU, + RISCV_INSN_WMVX_VWMACC, + //--------------------- RISCV_C_FSW--------------------- + RISCV_INSN_C_FSW, + //--------------------- RISCV_C_SW--------------------- + RISCV_INSN_C_SW, + //--------------------- RISCV_ZBS_RTYPE--------------------- + RISCV_INSN_BSET, + RISCV_INSN_BINV, + RISCV_INSN_BEXT, + RISCV_INSN_BCLR, + //--------------------- RISCV_F_BIN_TYPE_X_S--------------------- + RISCV_INSN_FLT_S, + RISCV_INSN_FLE_S, + RISCV_INSN_FEQ_S, + //--------------------- RISCV_C_SUB--------------------- + RISCV_INSN_C_SUB, + //--------------------- RISCV_VFUNARY0--------------------- + RISCV_INSN_FV_CVT_X_F, + RISCV_INSN_FV_CVT_XU_F, + RISCV_INSN_FV_CVT_RTZ_X_F, + RISCV_INSN_FV_CVT_RTZ_XU_F, + RISCV_INSN_FV_CVT_F_XU, + RISCV_INSN_FV_CVT_F_X, + //--------------------- RISCV_FROUNDNX_S--------------------- + RISCV_INSN_FROUNDNX_S, + //--------------------- RISCV_ZICBOZ--------------------- + RISCV_INSN_ZICBOZ, + //--------------------- RISCV_SFENCE_W_INVAL--------------------- + RISCV_INSN_SFENCE_W_INVAL, + //--------------------- RISCV_C_JR--------------------- + RISCV_INSN_C_JR, + //--------------------- RISCV_C_NOT--------------------- + RISCV_INSN_C_NOT, + //--------------------- RISCV_ZBB_EXTOP--------------------- + RISCV_INSN_ZEXTH, + RISCV_INSN_SEXTH, + RISCV_INSN_SEXTB, + //--------------------- RISCV_MVVTYPE--------------------- + RISCV_INSN_MVV_VREMU, + RISCV_INSN_MVV_VREM, + RISCV_INSN_MVV_VMULHU, + RISCV_INSN_MVV_VMULHSU, + RISCV_INSN_MVV_VMULH, + RISCV_INSN_MVV_VMUL, + RISCV_INSN_MVV_VDIVU, + RISCV_INSN_MVV_VDIV, + RISCV_INSN_MVV_VASUBU, + RISCV_INSN_MVV_VASUB, + RISCV_INSN_MVV_VAADDU, + RISCV_INSN_MVV_VAADD, + //--------------------- RISCV_FVFMATYPE--------------------- + RISCV_INSN_VF_VNMSUB, + RISCV_INSN_VF_VNMSAC, + RISCV_INSN_VF_VNMADD, + RISCV_INSN_VF_VNMACC, + RISCV_INSN_VF_VMSUB, + RISCV_INSN_VF_VMSAC, + RISCV_INSN_VF_VMADD, + RISCV_INSN_VF_VMACC, + //--------------------- RISCV_FMAXM_H--------------------- + RISCV_INSN_FMAXM_H, + //--------------------- RISCV_SHA256SUM0--------------------- + RISCV_INSN_SHA256SUM0, + //--------------------- RISCV_ZBS_IOP--------------------- + RISCV_INSN_BSETI, + RISCV_INSN_BINVI, + RISCV_INSN_BEXTI, + RISCV_INSN_BCLRI, + //--------------------- RISCV_C_XOR--------------------- + RISCV_INSN_C_XOR, + //--------------------- RISCV_ZIMOP_MOP_R--------------------- + RISCV_INSN_ZIMOP_MOP_R, + //--------------------- RISCV_FMINM_H--------------------- + RISCV_INSN_FMINM_H, + //--------------------- RISCV_C_LUI_HINT--------------------- + RISCV_INSN_C_LUI_HINT, + //--------------------- RISCV_VVMCTYPE--------------------- + RISCV_INSN_VVMC_VMSBC, + RISCV_INSN_VVMC_VMADC, + //--------------------- RISCV_F_UN_RM_XF_TYPE_H--------------------- + RISCV_INSN_FCVT_H_WU, + RISCV_INSN_FCVT_H_W, + RISCV_INSN_FCVT_H_LU, + RISCV_INSN_FCVT_H_L, + //--------------------- RISCV_F_BIN_RM_TYPE_S--------------------- + RISCV_INSN_FSUB_S, + RISCV_INSN_FMUL_S, + RISCV_INSN_FDIV_S, + RISCV_INSN_FADD_S, + //--------------------- RISCV_SINVAL_VMA--------------------- + RISCV_INSN_SINVAL_VMA, + //--------------------- RISCV_MOVETYPEX--------------------- + RISCV_INSN_MOVETYPEX, + //--------------------- RISCV_VCPOP_V--------------------- + RISCV_INSN_VCPOP_V, + //--------------------- RISCV_C_BNEZ--------------------- + RISCV_INSN_C_BNEZ, + //--------------------- RISCV_FWVVMATYPE--------------------- + RISCV_INSN_FWVV_VNMSAC, + RISCV_INSN_FWVV_VNMACC, + RISCV_INSN_FWVV_VMSAC, + RISCV_INSN_FWVV_VMACC, + //--------------------- RISCV_AES64KS1I--------------------- + RISCV_INSN_AES64KS1I, + //--------------------- RISCV_F_BIN_X_TYPE_D--------------------- + RISCV_INSN_FLT_D, + RISCV_INSN_FLE_D, + RISCV_INSN_FEQ_D, + //--------------------- RISCV_RMVVTYPE--------------------- + RISCV_INSN_MVV_VREDXOR, + RISCV_INSN_MVV_VREDSUM, + RISCV_INSN_MVV_VREDOR, + RISCV_INSN_MVV_VREDMINU, + RISCV_INSN_MVV_VREDMIN, + RISCV_INSN_MVV_VREDMAXU, + RISCV_INSN_MVV_VREDMAX, + RISCV_INSN_MVV_VREDAND, + //--------------------- RISCV_F_UN_RM_XF_TYPE_S--------------------- + RISCV_INSN_FCVT_S_WU, + RISCV_INSN_FCVT_S_W, + RISCV_INSN_FCVT_S_LU, + RISCV_INSN_FCVT_S_L, + //--------------------- RISCV_CLZW--------------------- + RISCV_INSN_CLZW, + //--------------------- RISCV_REM--------------------- + RISCV_INSN_REM, + //--------------------- RISCV_C_EBREAK--------------------- + RISCV_INSN_C_EBREAK, + //--------------------- RISCV_AES64ESM--------------------- + RISCV_INSN_AES64ESM, + //--------------------- RISCV_VFNUNARY0--------------------- + RISCV_INSN_FNV_CVT_X_F, + RISCV_INSN_FNV_CVT_XU_F, + RISCV_INSN_FNV_CVT_RTZ_X_F, + RISCV_INSN_FNV_CVT_RTZ_XU_F, + RISCV_INSN_FNV_CVT_ROD_F_F, + RISCV_INSN_FNV_CVT_F_XU, + RISCV_INSN_FNV_CVT_F_X, + RISCV_INSN_FNV_CVT_F_F, + //--------------------- RISCV_VFWUNARY0--------------------- + RISCV_INSN_FWV_CVT_X_F, + RISCV_INSN_FWV_CVT_XU_F, + RISCV_INSN_FWV_CVT_RTZ_X_F, + RISCV_INSN_FWV_CVT_RTZ_XU_F, + RISCV_INSN_FWV_CVT_F_XU, + RISCV_INSN_FWV_CVT_F_X, + RISCV_INSN_FWV_CVT_F_F, + //--------------------- RISCV_MOVETYPEV--------------------- + RISCV_INSN_MOVETYPEV, + //--------------------- RISCV_VFUNARY1--------------------- + RISCV_INSN_FVV_VSQRT, + RISCV_INSN_FVV_VRSQRT7, + RISCV_INSN_FVV_VREC7, + RISCV_INSN_FVV_VCLASS, + //--------------------- RISCV_FWVFTYPE--------------------- + RISCV_INSN_FWVF_VSUB, + RISCV_INSN_FWVF_VMUL, + RISCV_INSN_FWVF_VADD, + //--------------------- RISCV_ZBA_RTYPE--------------------- + RISCV_INSN_SH3ADD, + RISCV_INSN_SH2ADD, + RISCV_INSN_SH1ADD, + //--------------------- RISCV_C_SRLI--------------------- + RISCV_INSN_C_SRLI, + //--------------------- RISCV_VSRETYPE--------------------- + RISCV_INSN_VSRETYPE, + //--------------------- RISCV_C_SLLI_HINT--------------------- + RISCV_INSN_C_SLLI_HINT, + //--------------------- RISCV_WVVTYPE--------------------- + RISCV_INSN_WVV_VWMULU, + RISCV_INSN_WVV_VWMULSU, + RISCV_INSN_WVV_VWMUL, + RISCV_INSN_WVV_VSUBU, + RISCV_INSN_WVV_VSUB, + RISCV_INSN_WVV_VADDU, + RISCV_INSN_WVV_VADD, + //--------------------- RISCV_F_BIN_TYPE_F_S--------------------- + RISCV_INSN_FSGNJ_S, + RISCV_INSN_FSGNJX_S, + RISCV_INSN_FSGNJN_S, + RISCV_INSN_FMIN_S, + RISCV_INSN_FMAX_S, + //--------------------- RISCV_AES64DSM--------------------- + RISCV_INSN_AES64DSM, + //--------------------- RISCV_C_LI--------------------- + RISCV_INSN_C_LI, + //--------------------- RISCV_F_BIN_X_TYPE_H--------------------- + RISCV_INSN_FLT_H, + RISCV_INSN_FLE_H, + RISCV_INSN_FEQ_H, + //--------------------- RISCV_C_SRAI--------------------- + RISCV_INSN_C_SRAI, + //--------------------- RISCV_F_UN_RM_FF_TYPE_D--------------------- + RISCV_INSN_FSQRT_D, + RISCV_INSN_FCVT_S_D, + RISCV_INSN_FCVT_D_S, + //--------------------- RISCV_FMVP_D_X--------------------- + RISCV_INSN_FMVP_D_X, + //--------------------- RISCV_C_LBU--------------------- + RISCV_INSN_C_LBU, + //--------------------- RISCV_RTYPEW--------------------- + RISCV_INSN_SUBW, + RISCV_INSN_SRLW, + RISCV_INSN_SRAW, + RISCV_INSN_SLLW, + RISCV_INSN_ADDW, + //--------------------- RISCV_WMVVTYPE--------------------- + RISCV_INSN_WMVV_VWMACCU, + RISCV_INSN_WMVV_VWMACCSU, + RISCV_INSN_WMVV_VWMACC, + //--------------------- RISCV_MULW--------------------- + RISCV_INSN_MULW, + //--------------------- RISCV_VWSLL_VV--------------------- + RISCV_INSN_VWSLL_VV, + //--------------------- RISCV_VVCMPTYPE--------------------- + RISCV_INSN_VVCMP_VMSNE, + RISCV_INSN_VVCMP_VMSLTU, + RISCV_INSN_VVCMP_VMSLT, + RISCV_INSN_VVCMP_VMSLEU, + RISCV_INSN_VVCMP_VMSLE, + RISCV_INSN_VVCMP_VMSEQ, + //--------------------- RISCV_ILLEGAL--------------------- + RISCV_INSN_ILLEGAL, + //--------------------- RISCV_VREV8_V--------------------- + RISCV_INSN_VREV8_V, + //--------------------- RISCV_BREV8--------------------- + RISCV_INSN_BREV8, + //--------------------- RISCV_VCLMULH_VV--------------------- + RISCV_INSN_VCLMULH_VV, + //--------------------- RISCV_AES32DSMI--------------------- + RISCV_INSN_AES32DSMI, + //--------------------- RISCV_VANDN_VV--------------------- + RISCV_INSN_VANDN_VV, + //--------------------- RISCV_C_FSD--------------------- + RISCV_INSN_C_FSD, + //--------------------- RISCV_C_ADDW--------------------- + RISCV_INSN_C_ADDW, + //--------------------- RISCV_VCPOP_M--------------------- + RISCV_INSN_VCPOP_M, + //--------------------- RISCV_SHA256SIG1--------------------- + RISCV_INSN_SHA256SIG1, + //--------------------- RISCV_MVXTYPE--------------------- + RISCV_INSN_MVX_VSLIDE1UP, + RISCV_INSN_MVX_VSLIDE1DOWN, + RISCV_INSN_MVX_VREMU, + RISCV_INSN_MVX_VREM, + RISCV_INSN_MVX_VMULHU, + RISCV_INSN_MVX_VMULHSU, + RISCV_INSN_MVX_VMULH, + RISCV_INSN_MVX_VMUL, + RISCV_INSN_MVX_VDIVU, + RISCV_INSN_MVX_VDIV, + RISCV_INSN_MVX_VASUBU, + RISCV_INSN_MVX_VASUB, + RISCV_INSN_MVX_VAADDU, + RISCV_INSN_MVX_VAADD, +}; +#endif //> Group of RISCV instructions typedef enum riscv_insn_group { @@ -530,5 +1375,4 @@ typedef enum riscv_insn_group { } #endif -#endif - +#endif \ No newline at end of file