Wifi: switch tasks at interrupt level 1 (#3164)

* Pull up common code to save an instruction

* Simplify

* Tick at priority 1

* Rename timer handler

* Explain yielding

* Switch tasks at prio level 1

* Keep delegating to the SW interrupt on ESP32

* Changelog

Author: bugadani

esp-wifi/CHANGELOG.md

@@ -11,6 +11,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Changed
 
+- The scheduler now runs at interrupt priority 1 on Xtensa chips, too. (#3164)
+
 ### Fixed
 
 ### Removed

esp-wifi/src/preempt_builtin/timer/xtensa.rs

@@ -11,10 +11,18 @@ const TIMESLICE_FREQUENCY: Rate = Rate::from_hz(crate::CONFIG.tick_rate_hz);
 
 use super::TIMER;
 
+// ESP32 uses Software1 (priority 3) for task switching, because it reserves
+// Software0 for the Bluetooth stack.
+const SW_INTERRUPT: u32 = if cfg!(esp32) { 1 << 29 } else { 1 << 7 };
+
 pub(crate) fn setup_timer(mut timer1: TimeBase) {
+    // The timer needs to tick at Priority 1 to prevent accidentally interrupting
+    // priority 1 limited locks.
     timer1.set_interrupt_handler(InterruptHandler::new(
-        unsafe { core::mem::transmute::<*const (), extern "C" fn()>(handler as *const ()) },
-        interrupt::Priority::Priority2,
+        unsafe {
+            core::mem::transmute::<*const (), extern "C" fn()>(timer_tick_handler as *const ())
+        },
+        interrupt::Priority::Priority1,
     ));
     unwrap!(timer1.start(TIMESLICE_FREQUENCY.as_duration()));
     TIMER.with(|timer| {
@@ -35,7 +43,7 @@ pub(crate) fn setup_multitasking() {
     unsafe {
         let enabled = xtensa_lx::interrupt::disable();
         xtensa_lx::interrupt::enable_mask(
-            (1 << 29)
+            SW_INTERRUPT
                 | xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask()
                 | xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask()
                 | enabled,
@@ -44,38 +52,39 @@ pub(crate) fn setup_multitasking() {
 }
 
 pub(crate) fn disable_multitasking() {
-    xtensa_lx::interrupt::disable_mask(
-        1 << 29, // Disable Software1
-    );
+    xtensa_lx::interrupt::disable_mask(SW_INTERRUPT);
 }
 
-fn do_task_switch(context: &mut TrapFrame) {
+extern "C" fn timer_tick_handler(_context: &mut TrapFrame) {
     TIMER.with(|timer| {
         let timer = unwrap!(timer.as_mut());
         timer.clear_interrupt();
     });
 
-    task_switch(context);
-}
-
-extern "C" fn handler(context: &mut TrapFrame) {
-    do_task_switch(context);
+    // `task_switch` must be called on a single interrupt priority level only.
+    // Because on ESP32 the software interrupt is triggered at priority 3 but
+    // the timer interrupt is triggered at priority 1, we need to trigger the
+    // software interrupt manually.
+    cfg_if::cfg_if! {
+        if #[cfg(esp32)] {
+            yield_task();
+        } else {
+            task_switch(_context);
+        }
+    }
 }
 
 #[allow(non_snake_case)]
-#[no_mangle]
-fn Software1(_level: u32, context: &mut TrapFrame) {
-    let intr = 1 << 29;
-    unsafe {
-        core::arch::asm!("wsr.intclear  {0}", in(reg) intr, options(nostack));
-    }
+#[cfg_attr(not(esp32), export_name = "Software0")]
+#[cfg_attr(esp32, export_name = "Software1")]
+fn task_switch_interrupt(_level: u32, context: &mut TrapFrame) {
+    let intr = SW_INTERRUPT;
+    unsafe { core::arch::asm!("wsr.intclear  {0}", in(reg) intr, options(nostack)) };
 
-    do_task_switch(context);
+    task_switch(context);
 }
 
 pub(crate) fn yield_task() {
-    let intr = 1 << 29;
-    unsafe {
-        core::arch::asm!("wsr.intset  {0}", in(reg) intr, options(nostack));
-    }
+    let intr = SW_INTERRUPT;
+    unsafe { core::arch::asm!("wsr.intset  {0}", in(reg) intr, options(nostack)) };
 }

xtensa-lx-rt/src/exception/asm.rs

@@ -513,16 +513,16 @@ __default_naked_exception:
 .Ldefault_naked_exception_start:
     SAVE_CONTEXT 1
 
+    l32i    a6, sp, +XT_STK_EXCCAUSE  // put cause in a6 = a2 in callee
+    mov     a7, sp                    // put address of save frame in a7=a3 in callee
+
+    beqi    a6, 4, .Level1Interrupt   // Handle Level1 interrupt
+
     movi    a0, (PS_INTLEVEL_EXCM | PS_WOE)
     wsr     a0, PS
     rsync
 
-    l32i    a6, sp, +XT_STK_EXCCAUSE  // put cause in a6 = a2 in callee
-    beqi    a6, 4, .Level1Interrupt
-
-    mov     a7, sp                    // put address of save frame in a7=a3 in callee
     call4   __exception               // call handler <= actual call!
-
     j       .RestoreContext
 
 .Level1Interrupt:
@@ -531,7 +531,6 @@ __default_naked_exception:
     rsync
 
     movi    a6, 1                     // put interrupt level in a6 = a2 in callee
-    mov     a7, sp                    // put address of save frame in a7=a3 in callee
     call4   __level_1_interrupt       // call handler <= actual call!
 
 .RestoreContext: