@@ -306,6 +306,44 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
306306 Ops.push_back (emitScalarOrConstFoldImmArg (ICEArguments, i, E));
307307 }
308308
309+ // OG has unordered comparison as a form of optimization in addition to
310+ // ordered comparison, while CIR doesn't.
311+ //
312+ // This means that we can't encode the comparison code of UGT (unordered
313+ // greater than), at least not at the CIR level.
314+ //
315+ // The boolean shouldInvert compensates for this.
316+ // For example: to get to the comparison code UGT, we pass in
317+ // getVectorFCmpIR(OLE, shouldInvert = true) since OLE is the inverse of UGT.
318+
319+ // There are several ways to support this otherwise:
320+ // - register extra CmpOpKind for unordered comparison types and build the
321+ // translation code for
322+ // to go from CIR -> LLVM dialect. Notice we get this naturally with
323+ // shouldInvert, benefiting from existing infrastructure, albeit having to
324+ // generate an extra `not` at CIR).
325+ // - Just add extra comparison code to a new VecCmpOpKind instead of
326+ // cluttering CmpOpKind.
327+ // - Add a boolean in VecCmpOp to indicate if it's doing unordered or ordered
328+ // comparison
329+ // - Just emit the intrinsics call instead of calling this helper, see how the
330+ // LLVM lowering handles this.
331+ auto getVectorFCmpIR = [this , &Ops, &E](cir::CmpOpKind pred,
332+ bool shouldInvert, bool isSignaling) {
333+ assert (!cir::MissingFeatures::CGFPOptionsRAII ());
334+ auto loc = getLoc (E->getExprLoc ());
335+ mlir::Value cmp;
336+ if (builder.getIsFPConstrained ())
337+ // TODO: Add isSignaling boolean once emitConstrainedFPCall implemented
338+ assert (cir::MissingFeatures::emitConstrainedFPCall ());
339+ else
340+ cmp = builder.createVecCompare (loc, pred, Ops[0 ], Ops[1 ]);
341+
342+ mlir::Value bitCast = builder.createBitcast (
343+ shouldInvert ? builder.createNot (cmp) : cmp, Ops[0 ].getType ());
344+ return bitCast;
345+ };
346+
309347 switch (BuiltinID) {
310348 default :
311349 return nullptr ;
@@ -1702,10 +1740,12 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
17021740 llvm_unreachable (" cmpneqps NYI" );
17031741 case X86::BI__builtin_ia32_cmpnltps:
17041742 case X86::BI__builtin_ia32_cmpnltpd:
1705- llvm_unreachable (" cmpnltps NYI" );
1743+ return getVectorFCmpIR (cir::CmpOpKind::lt, /* shouldInvert=*/ true ,
1744+ /* isSignaling=*/ true );
17061745 case X86::BI__builtin_ia32_cmpnleps:
17071746 case X86::BI__builtin_ia32_cmpnlepd:
1708- llvm_unreachable (" cmpnleps NYI" );
1747+ return getVectorFCmpIR (cir::CmpOpKind::le, /* shouldInvert=*/ true ,
1748+ /* isSignaling=*/ true );
17091749 case X86::BI__builtin_ia32_cmpordps:
17101750 case X86::BI__builtin_ia32_cmpordpd:
17111751 llvm_unreachable (" cmpordps NYI" );
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