Improve docs

Author: romancardenas

riscv/src/interrupt/machine.rs

@@ -107,8 +107,7 @@ pub fn disable_interrupt<I: CoreInterruptNumber>(interrupt: I) {
 ///
 /// # Note
 ///
-/// Interrupts will only be triggered if interrupts are globally enabled in the hart.
-/// To do this, you must call [`enable`]  after enabling the interrupt.
+/// Interrupts will only be triggered if globally enabled in the hart. To do this, use [`enable`].
 ///
 /// # Safety
 ///
@@ -128,6 +127,11 @@ pub fn disable() {
 
 /// Enables interrupts globally in the current hart (machine mode).
 ///
+/// # Note
+///
+/// Only enabled interrupt sources will be triggered.
+/// To enable specific interrupt sources, use [`enable_interrupt`].
+///
 /// # Safety
 ///
 /// Enabling interrupts might break critical sections or other synchronization mechanisms.

riscv/src/interrupt/supervisor.rs

@@ -99,8 +99,7 @@ pub fn disable_interrupt<I: CoreInterruptNumber>(interrupt: I) {
 ///
 /// # Note
 ///
-/// Interrupts will only be triggered if interrupts are globally enabled in the hart.
-/// To do this, you must call [`enable`]  after enabling the interrupt.
+/// Interrupts will only be triggered if globally enabled in the hart. To do this, use [`enable`].
 ///
 /// # Safety
 ///
@@ -120,6 +119,11 @@ pub fn disable() {
 
 /// Enables interrupts globally in the current hart (supervisor mode).
 ///
+/// # Note
+///
+/// Only enabled interrupt sources will be triggered.
+/// To enable specific interrupt sources, use [`enable_interrupt`].
+///
 /// # Safety
 ///
 /// Enabling interrupts might break critical sections or other synchronization mechanisms.

riscv/src/register/mie.rs

@@ -1,7 +1,7 @@
 //! mie register
 
-use riscv_pac::CoreInterruptNumber;
 use crate::bits::{bf_extract, bf_insert};
+use riscv_pac::CoreInterruptNumber;
 
 read_write_csr! {
     /// `mie` register

riscv/src/register/sie.rs

@@ -1,7 +1,7 @@
 //! sie register
 
+use crate::bits::{bf_extract, bf_insert};
 use riscv_pac::CoreInterruptNumber;
-use crate::bits::{bf_insert, bf_extract};
 
 read_write_csr! {
 /// sie register