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Rename all instances of riscv-pac to riscv-types besides docs
1 parent 729a18f commit 38fcabe

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18 files changed

+22
-22
lines changed

18 files changed

+22
-22
lines changed

riscv-peripheral/src/aclint.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ pub mod mswi;
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pub mod mtimer;
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pub mod sswi;
99

10-
pub use riscv_pac::HartIdNumber; // re-export useful riscv-types traits
10+
pub use riscv_types::HartIdNumber; // re-export useful riscv-types traits
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/// Trait for a CLINT peripheral.
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///

riscv-peripheral/src/lib.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
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#![deny(missing_docs)]
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#![no_std]
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6-
pub use riscv_pac::result; // re-export the result module
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pub use riscv_types::result; // re-export the result module
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pub mod common; // common definitions for all peripherals
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pub mod hal; // trait implementations for embedded-hal

riscv-peripheral/src/macros.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ pub use paste::paste;
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/// ## Base address and per-HART mtimecmp registers, private `fn new()` function
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///
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/// ```
34-
/// use riscv_pac::result::{Error, Result};
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/// use riscv_types::result::{Error, Result};
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///
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/// /// HART IDs for the target CLINT peripheral
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/// #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -142,7 +142,7 @@ macro_rules! clint_codegen {
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/// ## Base address and per-HART context proxies, private `fn new()` function
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///
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/// ```
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/// use riscv_pac::result::{Error, Result};
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/// use riscv_types::result::{Error, Result};
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///
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/// /// HART IDs for the target CLINT peripheral
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/// #[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ pub mod priorities;
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pub mod threshold;
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// re-export useful riscv-types traits
12-
pub use riscv_pac::{HartIdNumber, InterruptNumber, PriorityNumber};
12+
pub use riscv_types::{HartIdNumber, InterruptNumber, PriorityNumber};
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1414
use riscv::register::{mhartid, mie, mip};
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@@ -200,7 +200,7 @@ impl<P: Plic> CTX<P> {
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#[cfg(test)]
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pub(crate) mod test {
202202
use crate::test::HartId;
203-
use riscv_pac::HartIdNumber;
203+
use riscv_types::HartIdNumber;
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#[allow(dead_code)]
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#[test]

riscv-peripheral/src/plic/claim.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
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//! Interrupt claim/complete register
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33
use crate::common::unsafe_peripheral;
4-
use riscv_pac::ExternalInterruptNumber;
4+
use riscv_types::ExternalInterruptNumber;
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66
unsafe_peripheral!(CLAIM, u32, RW);
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@@ -32,7 +32,7 @@ impl CLAIM {
3232
mod test {
3333
use super::*;
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use crate::test::Interrupt;
35-
use riscv_pac::InterruptNumber;
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use riscv_types::InterruptNumber;
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#[test]
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fn test_claim() {

riscv-peripheral/src/plic/enables.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
//! Interrupt enables register of a PLIC context.
22
33
use crate::common::{Reg, RW};
4-
use riscv_pac::ExternalInterruptNumber;
4+
use riscv_types::ExternalInterruptNumber;
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66
/// Enables register of a PLIC context.
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic/pendings.rs

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Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
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//! Interrupt pending bits register.
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use crate::common::{Reg, RO};
4-
use riscv_pac::ExternalInterruptNumber;
4+
use riscv_types::ExternalInterruptNumber;
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66
/// Interrupts pending bits register.
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic/priorities.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
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//! Interrupts Priorities register.
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use crate::common::{Reg, RW};
4-
use riscv_pac::{ExternalInterruptNumber, PriorityNumber};
4+
use riscv_types::{ExternalInterruptNumber, PriorityNumber};
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66
/// Interrupts priorities register.
77
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -71,7 +71,7 @@ impl PRIORITIES {
7171
mod test {
7272
use super::*;
7373
use crate::test::{Interrupt, Priority};
74-
use riscv_pac::InterruptNumber;
74+
use riscv_types::InterruptNumber;
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7676
#[test]
7777
fn test_priorities() {

riscv-rt/src/lib.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -662,7 +662,7 @@ use riscv::register::{
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mtvec::{self as xtvec, Mtvec as Xtvec, TrapMode},
663663
};
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665-
pub use riscv_pac::*;
665+
pub use riscv_types::*;
666666
pub use riscv_rt_macros::{core_interrupt, entry, exception, external_interrupt};
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668668
#[cfg(feature = "post-init")]

riscv/src/interrupt.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
use crate::result::Result;
66

77
// re-export useful riscv-types traits
8-
pub use riscv_pac::{CoreInterruptNumber, ExceptionNumber, InterruptNumber};
8+
pub use riscv_types::{CoreInterruptNumber, ExceptionNumber, InterruptNumber};
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1010
pub mod machine;
1111
pub mod supervisor;

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