Rename all instances of riscv-pac to riscv-types besides docs

Author: KushalMeghani1644

riscv-peripheral/src/aclint.rs

@@ -7,7 +7,7 @@ pub mod mswi;
 pub mod mtimer;
 pub mod sswi;
 
-pub use riscv_pac::HartIdNumber; // re-export useful riscv-types traits
+pub use riscv_types::HartIdNumber; // re-export useful riscv-types traits
 
 /// Trait for a CLINT peripheral.
 ///

riscv-peripheral/src/lib.rs

@@ -3,7 +3,7 @@
 #![deny(missing_docs)]
 #![no_std]
 
-pub use riscv_pac::result; // re-export the result module
+pub use riscv_types::result; // re-export the result module
 
 pub mod common; // common definitions for all peripherals
 pub mod hal; // trait implementations for embedded-hal

riscv-peripheral/src/macros.rs

@@ -31,7 +31,7 @@ pub use paste::paste;
 /// ## Base address and per-HART mtimecmp registers, private `fn new()` function
 ///
 /// ```
-/// use riscv_pac::result::{Error, Result};
+/// use riscv_types::result::{Error, Result};
 ///
 /// /// HART IDs for the target CLINT peripheral
 /// #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -142,7 +142,7 @@ macro_rules! clint_codegen {
 /// ## Base address and per-HART context proxies, private `fn new()` function
 ///
 /// ```
-/// use riscv_pac::result::{Error, Result};
+/// use riscv_types::result::{Error, Result};
 ///
 /// /// HART IDs for the target CLINT peripheral
 /// #[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic.rs

@@ -9,7 +9,7 @@ pub mod priorities;
 pub mod threshold;
 
 // re-export useful riscv-types traits
-pub use riscv_pac::{HartIdNumber, InterruptNumber, PriorityNumber};
+pub use riscv_types::{HartIdNumber, InterruptNumber, PriorityNumber};
 
 use riscv::register::{mhartid, mie, mip};
 
@@ -200,7 +200,7 @@ impl<P: Plic> CTX<P> {
 #[cfg(test)]
 pub(crate) mod test {
     use crate::test::HartId;
-    use riscv_pac::HartIdNumber;
+    use riscv_types::HartIdNumber;
 
     #[allow(dead_code)]
     #[test]

riscv-peripheral/src/plic/claim.rs

@@ -1,7 +1,7 @@
 //! Interrupt claim/complete register
 
 use crate::common::unsafe_peripheral;
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 unsafe_peripheral!(CLAIM, u32, RW);
 
@@ -32,7 +32,7 @@ impl CLAIM {
 mod test {
     use super::*;
     use crate::test::Interrupt;
-    use riscv_pac::InterruptNumber;
+    use riscv_types::InterruptNumber;
 
     #[test]
     fn test_claim() {

riscv-peripheral/src/plic/enables.rs

@@ -1,7 +1,7 @@
 //! Interrupt enables register of a PLIC context.
 
 use crate::common::{Reg, RW};
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 /// Enables register of a PLIC context.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic/pendings.rs

@@ -1,7 +1,7 @@
 //! Interrupt pending bits register.
 
 use crate::common::{Reg, RO};
-use riscv_pac::ExternalInterruptNumber;
+use riscv_types::ExternalInterruptNumber;
 
 /// Interrupts pending bits register.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]

riscv-peripheral/src/plic/priorities.rs

@@ -1,7 +1,7 @@
 //! Interrupts Priorities register.
 
 use crate::common::{Reg, RW};
-use riscv_pac::{ExternalInterruptNumber, PriorityNumber};
+use riscv_types::{ExternalInterruptNumber, PriorityNumber};
 
 /// Interrupts priorities register.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
@@ -71,7 +71,7 @@ impl PRIORITIES {
 mod test {
     use super::*;
     use crate::test::{Interrupt, Priority};
-    use riscv_pac::InterruptNumber;
+    use riscv_types::InterruptNumber;
 
     #[test]
     fn test_priorities() {

riscv-rt/src/lib.rs

@@ -662,7 +662,7 @@ use riscv::register::{
     mtvec::{self as xtvec, Mtvec as Xtvec, TrapMode},
 };
 
-pub use riscv_pac::*;
+pub use riscv_types::*;
 pub use riscv_rt_macros::{core_interrupt, entry, exception, external_interrupt};
 
 #[cfg(feature = "post-init")]

riscv-types/Cargo.toml

@@ -7,7 +7,7 @@ repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to RISC-V processors"
-documentation = "https://docs.rs/riscv-pac"
+documentation = "https://docs.rs/riscv-types"
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"