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1 parent 33f7d31 commit 7f3fe23Copy full SHA for 7f3fe23
riscv/src/register/mcounteren.rs
@@ -113,29 +113,9 @@ mod tests {
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fn test_mcounteren() {
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let mut m = Mcounteren { bits: 0 };
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- assert!(!m.cy());
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-
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- m.set_cy(true);
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- assert!(m.cy());
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- m.set_cy(false);
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- assert!(!m.tm());
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- m.set_tm(true);
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- assert!(m.tm());
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- m.set_tm(false);
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- assert!(!m.ir());
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- m.set_ir(true);
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- assert!(m.ir());
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- m.set_ir(false);
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+ test_csr_field!(m, cy);
+ test_csr_field!(m, tm);
+ test_csr_field!(m, ir);
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(3..32).for_each(|i| {
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assert!(!m.hpm(i));
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