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1 parent 785eb92 commit 90cfc5fCopy full SHA for 90cfc5f
riscv/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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+- Allow all bits to be set in Mcause::from_bits on 64-bit targets.
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+
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## [v0.14.0] - 2025-06-10
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### Added
riscv/src/register/mcause.rs
@@ -5,7 +5,7 @@ pub use crate::interrupt::Trap;
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read_only_csr! {
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/// `mcause` register
Mcause: 0x342,
- mask: 0xffff_ffff,
+ mask: usize::MAX,
}
#[cfg(target_arch = "riscv32")]
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