riscv: define mideleg using CSR macros

Uses CSR helper macros to define the `mideleg` register.

Author: rmsyn

riscv/src/register/mideleg.rs

@@ -1,38 +1,29 @@
 //! mideleg register
 
-/// mideleg register
-#[derive(Clone, Copy, Debug)]
-pub struct Mideleg {
-    bits: usize,
+read_write_csr! {
+    /// `mideleg` register
+    Mideleg: 0x303,
+    mask: 0x222,
 }
 
-impl Mideleg {
-    /// Returns the contents of the register as raw bits
-    #[inline]
-    pub fn bits(&self) -> usize {
-        self.bits
-    }
-
+read_write_csr_field! {
+    Mideleg,
     /// Supervisor Software Interrupt Delegate
-    #[inline]
-    pub fn ssoft(&self) -> bool {
-        self.bits & (1 << 1) != 0
-    }
+    ssoft: 1,
+}
 
+read_write_csr_field! {
+    Mideleg,
     /// Supervisor Timer Interrupt Delegate
-    #[inline]
-    pub fn stimer(&self) -> bool {
-        self.bits & (1 << 5) != 0
-    }
+    stimer: 5,
+}
 
+read_write_csr_field! {
+    Mideleg,
     /// Supervisor External Interrupt Delegate
-    #[inline]
-    pub fn sext(&self) -> bool {
-        self.bits & (1 << 9) != 0
-    }
+    sext: 9,
 }
 
-read_csr_as!(Mideleg, 0x303);
 set!(0x303);
 clear!(0x303);