`riscv-rt`: reconfigurable trap frame

[romancardenas]

We need to reconfigure the trap frame via feature flags. This is especially relevant for:

1. RV32E targets (see riscv-rt: Assembly algorithm for RAM init incompatible with upcoming RVE extension (future proofing) #189)
2. ESP32Cx targets (see this issue in esp-hal)

Additionally, I foresee another breaking change: changing the order of the trap frame to follow the x order (from x0 to x31). As far as I know, this is required for ESP32Cx devices. Maybe @bjoernQ can confirm this to us.

[bjoernQ]

Additionally, I foresee another breaking change: changing the order of the trap frame to follow the x order (from x0 to x31). As far as I know, this is required for ESP32Cx devices. Maybe @bjoernQ can confirm this to us.

The order of the registers in the trap frame is not strictly required anymore on our side (it was required when we included atomic emulation via a trap handler - we don't do that anymore)