From 6c4a2d8e6fede158224d1e2ad3e6a0d384b008cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Quentin?= Date: Tue, 22 Jul 2025 17:16:22 +0200 Subject: [PATCH 1/3] Support chips which don't support MIE/MIP CSRs --- riscv-rt/CHANGELOG.md | 1 + riscv-rt/Cargo.toml | 1 + riscv-rt/src/asm.rs | 7 ++++--- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index 6cd21c5a..d3eb9bd5 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function. - Added `.uninit` section to the linker file. Due to its similarities with `.bss`, the linker will place this new section in `REGION_BSS`. +- Additional feature `no-mie-mip` to work on chips without the MIE and MIP CSRs (e.g. ESP32-C2, ESP32-C3) ### Changed diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml index e400473c..dfe99012 100644 --- a/riscv-rt/Cargo.toml +++ b/riscv-rt/Cargo.toml @@ -40,5 +40,6 @@ v-trap = ["riscv-rt-macros/v-trap"] u-boot = ["riscv-rt-macros/u-boot", "single-hart"] no-interrupts = [] no-exceptions = [] +no-mie-mip = [] device = [] memory = [] diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs index bec41067..db38b987 100644 --- a/riscv-rt/src/asm.rs +++ b/riscv-rt/src/asm.rs @@ -68,10 +68,11 @@ _abs_start: #[cfg(feature = "s-mode")] "csrw sie, 0 csrw sip, 0", - #[cfg(not(feature = "s-mode"))] + #[cfg(all(not(feature = "s-mode"), not(feature = "no-mie-mip")))] "csrw mie, 0 - csrw mip, 0 - csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode + csrw mip, 0", + #[cfg(not(feature = "s-mode"))] + "csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode // Set pre-init trap vector "la t0, _pre_init_trap", #[cfg(feature = "s-mode")] From 15151fb462dd30eac3111618bfa079bb31cfaa3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Quentin?= Date: Wed, 23 Jul 2025 08:54:29 +0200 Subject: [PATCH 2/3] Rename feature `no-mie-mip` to `no-xie-xip` --- riscv-rt/Cargo.toml | 2 +- riscv-rt/src/asm.rs | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml index dfe99012..44d74586 100644 --- a/riscv-rt/Cargo.toml +++ b/riscv-rt/Cargo.toml @@ -40,6 +40,6 @@ v-trap = ["riscv-rt-macros/v-trap"] u-boot = ["riscv-rt-macros/u-boot", "single-hart"] no-interrupts = [] no-exceptions = [] -no-mie-mip = [] +no-xie-xip = [] device = [] memory = [] diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs index db38b987..b3041bfc 100644 --- a/riscv-rt/src/asm.rs +++ b/riscv-rt/src/asm.rs @@ -65,10 +65,10 @@ _abs_start: .cfi_startproc .cfi_undefined ra", // Disable interrupts - #[cfg(feature = "s-mode")] + #[cfg(all(feature = "s-mode", not(feature = "no-xie-xip")))] "csrw sie, 0 csrw sip, 0", - #[cfg(all(not(feature = "s-mode"), not(feature = "no-mie-mip")))] + #[cfg(all(not(feature = "s-mode"), not(feature = "no-xie-xip")))] "csrw mie, 0 csrw mip, 0", #[cfg(not(feature = "s-mode"))] From c60992981c40cb381c1bc4ac5330c7f2a0a16bbf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Quentin?= Date: Wed, 23 Jul 2025 09:59:05 +0200 Subject: [PATCH 3/3] Adapt changelog entry --- riscv-rt/CHANGELOG.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index d3eb9bd5..58d924b5 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -13,7 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function. - Added `.uninit` section to the linker file. Due to its similarities with `.bss`, the linker will place this new section in `REGION_BSS`. -- Additional feature `no-mie-mip` to work on chips without the MIE and MIP CSRs (e.g. ESP32-C2, ESP32-C3) +- Additional feature `no-xie-xip` to work on chips without the XIE and XIP CSRs (e.g. ESP32-C2, ESP32-C3) ### Changed