diff --git a/.github/workflows/riscv-peripheral.yaml b/.github/workflows/riscv-peripheral.yaml index 571e383f..d43d1802 100644 --- a/.github/workflows/riscv-peripheral.yaml +++ b/.github/workflows/riscv-peripheral.yaml @@ -11,8 +11,8 @@ jobs: build-riscv: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.75.0 - toolchain: [ stable, nightly, 1.75.0 ] + # All generated code should be running on stable now, MRSV is 1.81.0 + toolchain: [ stable, nightly, 1.81.0 ] target: - riscv32i-unknown-none-elf - riscv32imc-unknown-none-elf diff --git a/.github/workflows/riscv-rt.yaml b/.github/workflows/riscv-rt.yaml index da2e7940..bcd146bd 100644 --- a/.github/workflows/riscv-rt.yaml +++ b/.github/workflows/riscv-rt.yaml @@ -10,8 +10,8 @@ jobs: build-riscv: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.68.0 - toolchain: [ stable, nightly, 1.68.0 ] + # All generated code should be running on stable now, MRSV is 1.81.0 + toolchain: [ stable, nightly, 1.81.0 ] target: - riscv32i-unknown-none-elf - riscv32im-unknown-none-elf @@ -27,11 +27,6 @@ jobs: # Nightly is only for reference and allowed to fail - toolchain: nightly experimental: true - exclude: - - toolchain: 1.68.0 - target: riscv32im-unknown-none-elf - - toolchain: 1.68.0 - target: riscv32imafc-unknown-none-elf runs-on: ubuntu-latest continue-on-error: ${{ matrix.experimental || false }} steps: diff --git a/.github/workflows/riscv.yaml b/.github/workflows/riscv.yaml index 0a7ffc2b..eb31f260 100644 --- a/.github/workflows/riscv.yaml +++ b/.github/workflows/riscv.yaml @@ -11,8 +11,8 @@ jobs: build-riscv: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.68.0 - toolchain: [ stable, nightly, 1.68.0 ] + # All generated code should be running on stable now, MRSV is 1.81.0 + toolchain: [ stable, nightly, 1.81.0 ] target: - riscv32i-unknown-none-elf - riscv32imc-unknown-none-elf diff --git a/.github/workflows/tests.yaml b/.github/workflows/tests.yaml index 954efc2a..05b3b03f 100644 --- a/.github/workflows/tests.yaml +++ b/.github/workflows/tests.yaml @@ -20,8 +20,8 @@ jobs: run-build: strategy: matrix: - # All generated code should be running on stable now, MRSV is 1.68.0 - toolchain: [ stable, nightly, 1.68.0 ] + # All generated code should be running on stable now, MRSV is 1.81.0 + toolchain: [ stable, nightly, 1.81.0 ] target: - riscv32i-unknown-none-elf - riscv32im-unknown-none-elf @@ -36,11 +36,6 @@ jobs: # Nightly is only for reference and allowed to fail - toolchain: nightly experimental: true - exclude: - - toolchain: 1.68.0 - target: riscv32im-unknown-none-elf - - toolchain: 1.68.0 - target: riscv32imafc-unknown-none-elf runs-on: ubuntu-latest continue-on-error: ${{ matrix.experimental || false }} steps: diff --git a/README.md b/README.md index 3314bbee..33cafd06 100644 --- a/README.md +++ b/README.md @@ -3,11 +3,11 @@ This repository contains various crates useful for writing Rust programs on RISC-V microcontrollers: * [`riscv`]: CPU registers access and intrinsics -* [`riscv-pac`]: Common traits to be implemented by RISC-V PACs * [`riscv-peripheral`]: Interfaces for standard RISC-V peripherals * [`riscv-rt`]: Startup code and interrupt handling * [`riscv-semihosting`]: Semihosting for RISC-V processors * [`riscv-target-parser`]: Utility crate for parsing RISC-V targets in build scripts +* [`riscv-types`]: Common traits to be implemented by RISC-V PACs This project is developed and maintained by the [RISC-V team][team]. @@ -24,7 +24,7 @@ Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises to intervene to uphold that code of conduct. [`riscv`]: https://crates.io/crates/riscv -[`riscv-pac`]: https://crates.io/crates/riscv-pac +[`riscv-types`]: https://crates.io/crates/riscv-types [`riscv-peripheral`]: https://crates.io/crates/riscv-peripheral [`riscv-rt`]: https://crates.io/crates/riscv-rt [`riscv-semihosting`]: https://crates.io/crates/riscv-semihosting diff --git a/riscv-pac/CHANGELOG.md b/riscv-pac/CHANGELOG.md index 606bec23..ef360639 100644 --- a/riscv-pac/CHANGELOG.md +++ b/riscv-pac/CHANGELOG.md @@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- This crate has been deprecated. Use `riscv-types` instead. - Updated the license to `MIT or Apache-2.0` ## [v0.2.0] - 2024-10-19 diff --git a/riscv-pac/Cargo.toml b/riscv-pac/Cargo.toml index 18be9de1..01c9d9be 100644 --- a/riscv-pac/Cargo.toml +++ b/riscv-pac/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "riscv-pac" -version = "0.2.0" +version = "0.3.0" edition = "2021" rust-version = "1.60" repository = "https://github.com/rust-embedded/riscv" diff --git a/riscv-pac/README.md b/riscv-pac/README.md index 56cf819f..b4f7ecaa 100644 --- a/riscv-pac/README.md +++ b/riscv-pac/README.md @@ -1,6 +1,10 @@ [![crates.io](https://img.shields.io/crates/d/riscv-pac.svg)](https://crates.io/crates/riscv-pac) [![crates.io](https://img.shields.io/crates/v/riscv-pac.svg)](https://crates.io/crates/riscv-pac) +# Deprecation notice + +This crate has been deprecated. Use [`riscv-types`](https://crates.io/crates/riscv-types) instead. + # `riscv-pac` > Target-specific traits to be implemented by PACs diff --git a/riscv-pac/src/lib.rs b/riscv-pac/src/lib.rs index f0929b3d..a694cdd9 100644 --- a/riscv-pac/src/lib.rs +++ b/riscv-pac/src/lib.rs @@ -1,3 +1,7 @@ +//! # Deprecation notice +//! +//! This crate has been deprecated. Use [`riscv-types`](https://crates.io/crates/riscv-types) instead. + #![no_std] pub mod result; diff --git a/riscv-peripheral/CHANGELOG.md b/riscv-peripheral/CHANGELOG.md index 51a93e53..6c8aeb33 100644 --- a/riscv-peripheral/CHANGELOG.md +++ b/riscv-peripheral/CHANGELOG.md @@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Bump MSRV to 1.81 due to `riscv` - Update license to `MIT or Apache-2.0` ### Fixed diff --git a/riscv-peripheral/Cargo.toml b/riscv-peripheral/Cargo.toml index 0a7006cc..7b55f3aa 100644 --- a/riscv-peripheral/Cargo.toml +++ b/riscv-peripheral/Cargo.toml @@ -2,7 +2,7 @@ name = "riscv-peripheral" version = "0.4.0" edition = "2021" -rust-version = "1.75" +rust-version = "1.81" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"] @@ -17,7 +17,6 @@ license = "MIT OR Apache-2.0" embedded-hal = "1.0.0" paste = "1.0" riscv = { path = "../riscv", version = "0.15.0" } -riscv-pac = { path = "../riscv-pac", version = "0.2.0" } [package.metadata.docs.rs] all-features = true diff --git a/riscv-peripheral/README.md b/riscv-peripheral/README.md index 45e483d8..1331d0ac 100644 --- a/riscv-peripheral/README.md +++ b/riscv-peripheral/README.md @@ -11,12 +11,12 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.75 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.81 and up. It *might* compile with older versions but that may change in any new patch release. ## License -Copyright 2023-2024 [RISC-V team][team] +Copyright 2023-2025 [RISC-V team][team] Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice diff --git a/riscv-peripheral/src/aclint.rs b/riscv-peripheral/src/aclint.rs index 3354431a..c0cac652 100644 --- a/riscv-peripheral/src/aclint.rs +++ b/riscv-peripheral/src/aclint.rs @@ -7,7 +7,7 @@ pub mod mswi; pub mod mtimer; pub mod sswi; -pub use riscv_pac::HartIdNumber; // re-export useful riscv-pac traits +pub use riscv::HartIdNumber; // re-export useful riscv-types traits /// Trait for a CLINT peripheral. /// diff --git a/riscv-peripheral/src/lib.rs b/riscv-peripheral/src/lib.rs index be677477..7e71ae08 100644 --- a/riscv-peripheral/src/lib.rs +++ b/riscv-peripheral/src/lib.rs @@ -3,7 +3,7 @@ #![deny(missing_docs)] #![no_std] -pub use riscv_pac::result; // re-export the result module +pub use riscv::result; // re-export the result module pub mod common; // common definitions for all peripherals pub mod hal; // trait implementations for embedded-hal diff --git a/riscv-peripheral/src/macros.rs b/riscv-peripheral/src/macros.rs index c5c559dd..c44c594a 100644 --- a/riscv-peripheral/src/macros.rs +++ b/riscv-peripheral/src/macros.rs @@ -31,7 +31,7 @@ pub use paste::paste; /// ## Base address and per-HART mtimecmp registers, private `fn new()` function /// /// ``` -/// use riscv_pac::result::{Error, Result}; +/// use riscv::result::{Error, Result}; /// /// /// HART IDs for the target CLINT peripheral /// #[derive(Clone, Copy, Debug, Eq, PartialEq)] @@ -142,7 +142,7 @@ macro_rules! clint_codegen { /// ## Base address and per-HART context proxies, private `fn new()` function /// /// ``` -/// use riscv_pac::result::{Error, Result}; +/// use riscv::result::{Error, Result}; /// /// /// HART IDs for the target CLINT peripheral /// #[derive(Clone, Copy, Debug, Eq, PartialEq)] diff --git a/riscv-peripheral/src/plic.rs b/riscv-peripheral/src/plic.rs index af0300b8..a3a5c9ea 100644 --- a/riscv-peripheral/src/plic.rs +++ b/riscv-peripheral/src/plic.rs @@ -8,8 +8,8 @@ pub mod pendings; pub mod priorities; pub mod threshold; -// re-export useful riscv-pac traits -pub use riscv_pac::{HartIdNumber, InterruptNumber, PriorityNumber}; +// re-export useful riscv-types traits +pub use riscv::{HartIdNumber, InterruptNumber, PriorityNumber}; use riscv::register::{mhartid, mie, mip}; @@ -200,7 +200,7 @@ impl CTX

{ #[cfg(test)] pub(crate) mod test { use crate::test::HartId; - use riscv_pac::HartIdNumber; + use riscv::HartIdNumber; #[allow(dead_code)] #[test] diff --git a/riscv-peripheral/src/plic/claim.rs b/riscv-peripheral/src/plic/claim.rs index 945f2b35..ec9c6005 100644 --- a/riscv-peripheral/src/plic/claim.rs +++ b/riscv-peripheral/src/plic/claim.rs @@ -1,7 +1,7 @@ //! Interrupt claim/complete register use crate::common::unsafe_peripheral; -use riscv_pac::ExternalInterruptNumber; +use riscv::ExternalInterruptNumber; unsafe_peripheral!(CLAIM, u32, RW); @@ -32,7 +32,7 @@ impl CLAIM { mod test { use super::*; use crate::test::Interrupt; - use riscv_pac::InterruptNumber; + use riscv::InterruptNumber; #[test] fn test_claim() { diff --git a/riscv-peripheral/src/plic/enables.rs b/riscv-peripheral/src/plic/enables.rs index 016eb863..f2edeefd 100644 --- a/riscv-peripheral/src/plic/enables.rs +++ b/riscv-peripheral/src/plic/enables.rs @@ -1,7 +1,7 @@ //! Interrupt enables register of a PLIC context. use crate::common::{Reg, RW}; -use riscv_pac::ExternalInterruptNumber; +use riscv::ExternalInterruptNumber; /// Enables register of a PLIC context. #[derive(Clone, Copy, Debug, Eq, PartialEq)] diff --git a/riscv-peripheral/src/plic/pendings.rs b/riscv-peripheral/src/plic/pendings.rs index 12b170ce..c9f61f2d 100644 --- a/riscv-peripheral/src/plic/pendings.rs +++ b/riscv-peripheral/src/plic/pendings.rs @@ -1,7 +1,7 @@ //! Interrupt pending bits register. use crate::common::{Reg, RO}; -use riscv_pac::ExternalInterruptNumber; +use riscv::ExternalInterruptNumber; /// Interrupts pending bits register. #[derive(Clone, Copy, Debug, Eq, PartialEq)] diff --git a/riscv-peripheral/src/plic/priorities.rs b/riscv-peripheral/src/plic/priorities.rs index 725cd6d9..6d90e988 100644 --- a/riscv-peripheral/src/plic/priorities.rs +++ b/riscv-peripheral/src/plic/priorities.rs @@ -1,7 +1,7 @@ //! Interrupts Priorities register. use crate::common::{Reg, RW}; -use riscv_pac::{ExternalInterruptNumber, PriorityNumber}; +use riscv::{ExternalInterruptNumber, PriorityNumber}; /// Interrupts priorities register. #[derive(Clone, Copy, Debug, Eq, PartialEq)] @@ -71,7 +71,7 @@ impl PRIORITIES { mod test { use super::*; use crate::test::{Interrupt, Priority}; - use riscv_pac::InterruptNumber; + use riscv::InterruptNumber; #[test] fn test_priorities() { diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index bb82c85d..b8eacb18 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -14,6 +14,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Bump MSRV to 1.81 due to `riscv-types` +- Use `riscv-types` instead of `riscv-pac` - Update license to `MIT or Apache-2.0` - Fix clippy warnings in riscv_rt_macros::strip_type_path - Bump MSRV to 1.68 for latest syn 2.0 release diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml index f81c0191..91694a05 100644 --- a/riscv-rt/Cargo.toml +++ b/riscv-rt/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "riscv-rt" version = "0.16.0" -rust-version = "1.68" +rust-version = "1.81" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "no-std"] @@ -25,7 +25,7 @@ riscv-target-parser = { path = "../riscv-target-parser", version = "0.1.2" } [dependencies] riscv = { path = "../riscv", version = "0.15.0", features = ["rt"] } -riscv-pac = { path = "../riscv-pac", version = "0.2.0" } +riscv-types = { path = "../riscv-types", version = "0.1.0" } riscv-rt-macros = { path = "macros", version = "0.6.0" } defmt = { version = "1.0.1", optional = true } diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs index 8760495e..d1dbc458 100644 --- a/riscv-rt/src/lib.rs +++ b/riscv-rt/src/lib.rs @@ -671,8 +671,8 @@ use riscv::register::{ mtvec::{self as xtvec, Mtvec as Xtvec, TrapMode}, }; -pub use riscv_pac::*; pub use riscv_rt_macros::{core_interrupt, entry, exception, external_interrupt}; +pub use riscv_types::*; #[cfg(feature = "post-init")] pub use riscv_rt_macros::post_init; diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 2e709014..594591fa 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -21,9 +21,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Bump MSRV to 1.81 due to `riscv-types` +- Use `riscv-types` instead of `riscv-pac` +- Reexport only `pac_enum` macro from `riscv-macros` - Moved macros from `./macros/` to `../riscv-macros/` - Updated the license to `MIT or Apache-2.0` -- Bump MSRV to 1.68 for latest version of syn 2.0 - Now, `riscv::pac_enum` macro only includes trap-related code if `rt` or `rt-v-trap` features are enabled. ## [v0.15.0] - 2025-09-08 diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml index f4e87491..61ea5faf 100644 --- a/riscv/Cargo.toml +++ b/riscv/Cargo.toml @@ -2,7 +2,7 @@ name = "riscv" version = "0.15.0" edition = "2021" -rust-version = "1.68" +rust-version = "1.81" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"] @@ -29,6 +29,6 @@ rt-v-trap = ["rt", "riscv-macros/rt-v-trap"] [dependencies] critical-section = "1.2.0" embedded-hal = "1.0.0" -riscv-pac = { path = "../riscv-pac", version = "0.2.0" } +riscv-types = { path = "../riscv-types", version = "0.1.0" } riscv-macros = { path = "../riscv-macros", version = "0.3.0", optional = true } paste = "1.0.15" diff --git a/riscv/README.md b/riscv/README.md index 2df65fe2..e7595504 100644 --- a/riscv/README.md +++ b/riscv/README.md @@ -11,12 +11,12 @@ This project is developed and maintained by the [RISC-V team][team]. ## Minimum Supported Rust Version (MSRV) -This crate is guaranteed to compile on stable Rust 1.61 and up. It *might* +This crate is guaranteed to compile on stable Rust 1.81 and up. It *might* compile with older versions but that may change in any new patch release. ## License -Copyright 2019-2022 [RISC-V team][team] +Copyright 2019-2025 [RISC-V team][team] Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice diff --git a/riscv/src/interrupt.rs b/riscv/src/interrupt.rs index 93fda11c..d837f201 100644 --- a/riscv/src/interrupt.rs +++ b/riscv/src/interrupt.rs @@ -5,7 +5,7 @@ use crate::result::Result; // re-export useful riscv-pac traits -pub use riscv_pac::{CoreInterruptNumber, ExceptionNumber, InterruptNumber}; +pub use crate::{CoreInterruptNumber, ExceptionNumber, InterruptNumber}; pub mod machine; pub mod supervisor; diff --git a/riscv/src/interrupt/machine.rs b/riscv/src/interrupt/machine.rs index b8a54fb8..9de36c0a 100644 --- a/riscv/src/interrupt/machine.rs +++ b/riscv/src/interrupt/machine.rs @@ -1,8 +1,6 @@ use crate::{ interrupt::Trap, register::{mcause, mepc, mie, mip, mstatus}, -}; -use riscv_pac::{ result::{Error, Result}, CoreInterruptNumber, ExceptionNumber, InterruptNumber, }; diff --git a/riscv/src/interrupt/supervisor.rs b/riscv/src/interrupt/supervisor.rs index 33266f2c..59ef39d5 100644 --- a/riscv/src/interrupt/supervisor.rs +++ b/riscv/src/interrupt/supervisor.rs @@ -1,8 +1,6 @@ use crate::{ interrupt::Trap, register::{scause, sepc, sie, sip, sstatus}, -}; -use riscv_pac::{ result::{Error, Result}, CoreInterruptNumber, ExceptionNumber, InterruptNumber, }; diff --git a/riscv/src/lib.rs b/riscv/src/lib.rs index 0704f75b..8e230b24 100644 --- a/riscv/src/lib.rs +++ b/riscv/src/lib.rs @@ -58,8 +58,8 @@ pub mod register; // Re-export crates of the RISC-V ecosystem #[cfg(feature = "riscv-macros")] -pub use riscv_macros::*; -pub use riscv_pac::*; +pub use riscv_macros::pac_enum; +pub use riscv_types::*; #[macro_use] mod macros; diff --git a/riscv/src/register/mie.rs b/riscv/src/register/mie.rs index 0ca87677..a3896433 100644 --- a/riscv/src/register/mie.rs +++ b/riscv/src/register/mie.rs @@ -1,7 +1,9 @@ //! mie register -use crate::bits::{bf_extract, bf_insert}; -use riscv_pac::CoreInterruptNumber; +use crate::{ + bits::{bf_extract, bf_insert}, + CoreInterruptNumber, +}; read_write_csr! { /// `mie` register diff --git a/riscv/src/register/mip.rs b/riscv/src/register/mip.rs index 10e66526..8336818f 100644 --- a/riscv/src/register/mip.rs +++ b/riscv/src/register/mip.rs @@ -1,7 +1,6 @@ //! mip register -use crate::bits::bf_extract; -use riscv_pac::CoreInterruptNumber; +use crate::{bits::bf_extract, CoreInterruptNumber}; read_only_csr! { /// `mip` register diff --git a/riscv/src/register/mvien.rs b/riscv/src/register/mvien.rs index af162063..53a8a9f3 100644 --- a/riscv/src/register/mvien.rs +++ b/riscv/src/register/mvien.rs @@ -1,8 +1,10 @@ //! mvien register -use crate::bits::{bf_extract, bf_insert}; -use riscv_pac::result::{Error, Result}; -use riscv_pac::InterruptNumber; +use crate::{ + bits::{bf_extract, bf_insert}, + result::{Error, Result}, + InterruptNumber, +}; #[cfg(target_arch = "riscv32")] const MASK: usize = 0xffff_e222; diff --git a/riscv/src/register/mvienh.rs b/riscv/src/register/mvienh.rs index 9ec5438f..d409bcf9 100644 --- a/riscv/src/register/mvienh.rs +++ b/riscv/src/register/mvienh.rs @@ -1,8 +1,10 @@ //! mvienh register -use crate::bits::{bf_extract, bf_insert}; -use riscv_pac::result::{Error, Result}; -use riscv_pac::InterruptNumber; +use crate::{ + bits::{bf_extract, bf_insert}, + result::{Error, Result}, + InterruptNumber, +}; read_write_csr! { /// `mvienh` register diff --git a/riscv/src/register/scause.rs b/riscv/src/register/scause.rs index 2d42646f..1221b7ec 100644 --- a/riscv/src/register/scause.rs +++ b/riscv/src/register/scause.rs @@ -1,7 +1,6 @@ //! scause register -pub use crate::interrupt::Trap; -pub use riscv_pac::{CoreInterruptNumber, ExceptionNumber, InterruptNumber}; // re-export useful riscv-pac traits +pub use crate::{interrupt::Trap, CoreInterruptNumber, ExceptionNumber, InterruptNumber}; // re-export useful artifacts read_write_csr! { /// scause register diff --git a/riscv/src/register/sie.rs b/riscv/src/register/sie.rs index dfeecdaa..30724670 100644 --- a/riscv/src/register/sie.rs +++ b/riscv/src/register/sie.rs @@ -1,7 +1,9 @@ //! sie register -use crate::bits::{bf_extract, bf_insert}; -use riscv_pac::CoreInterruptNumber; +use crate::{ + bits::{bf_extract, bf_insert}, + CoreInterruptNumber, +}; read_write_csr! { /// sie register diff --git a/riscv/src/register/sip.rs b/riscv/src/register/sip.rs index c72602b9..159c87c3 100644 --- a/riscv/src/register/sip.rs +++ b/riscv/src/register/sip.rs @@ -1,7 +1,6 @@ //! sip register -use crate::bits::bf_extract; -use riscv_pac::CoreInterruptNumber; +use crate::{bits::bf_extract, CoreInterruptNumber}; read_only_csr! { /// sip register