help please

[Iversat]

Firmware Version :
ROM: 3.2 Stage: 0.0
Need Password: 0 Password OK: 1
Configuring DDR...
[DDR Configuration Complete]
Writing aml.img at 0xfffa0000...
[DONE]
Running at 0xfffa0000...
[DONE]
AMLC dataSize=16384, offset=65536, seq=0...
[DONE]
AMLC dataSize=49152, offset=393216, seq=1...
[DONE]
AMLC dataSize=16384, offset=229376, seq=2...
[DONE]
AMLC dataSize=49152, offset=81920, seq=3...
[DONE]
AMLC dataSize=49152, offset=131072, seq=4...
USB Error: [Errno None] b'libusb0-dll:err [_usb_reap_async] timeout error\n'. Retrying...
USB Error: [Errno None] b'libusb0-dll:err [_usb_reap_async] timeout error\n'. Retrying...
USB Error: [Errno None] b'libusb0-dll:err [_usb_reap_async] timeout error\n'. Retrying...
USB Error: [Errno None] b'libusb0-dll:err [_usb_reap_async] timeout error\n'. Retrying...
USB Error: [Errno None] b'libusb0-dll:err [_usb_reap_async] timeout error\n'. Retrying...

[Iversat]

I'm trying to load a temporary boot, everything works on the other board, but not on this one. The main difference is memory. That one costs SEC 304 and on the other board (which loads SEC 201)

[Iversat]

   l2_stage_init 0x01

bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:0000000f
L1:00000701
L2:00008067
L3:04000000
S1:00000000
B2:00012020
B1:f0f931b0

TE: 23242412

BL2 Built : 10:28:35, Apr 14 2019. g12a gb1cc8f0 - luan.yuan@droid15-sz

Board ID = 6
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
DDR driver_vesion: LPDDR4_PHY_V_0_1_11 build time: Apr 14 2019 10:28:31
board id: 6
Cfg max: 5, cur: 1. Board id: 255. Force loop cfg
DATA transfer complete...
fw parse done
DATA transfer complete...
AML DDR FW load done
DATA transfer complete...
PIEI prepare done
DDR4 probe
ddr clk to 1200MHz
DATA transfer complete...
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D init succeed
DATA transfer complete...
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

R0_RxClkDly_Margin==104 ps 8
R0_TxDqDly_Margi==143 ps 11

R1_RxClkDly_Margin==0 ps 0
R1_TxDqDly_Margi==0 ps 0

dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):000
2D init succeed
ddr init done, boot next stage
result report
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 0040002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass
STOP FOR AMLC dataSize=49152, offset=131072, seq=4.