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Add design name to CI label

Status: Open.

#52 In ChipFlow/chipflow-examples;

· robtaylor opened on Aug 7, 2025

Move simulation and software infrastructure to chipflow-lib

Status: Open.

#32 In ChipFlow/chipflow-examples;

· robtaylor opened on Apr 29, 2025

Fix FPGA board deployment and move to chipflow-lib

Status: Open.

#31 In ChipFlow/chipflow-examples;

· robtaylor opened on Apr 29, 2025

Fix importlib.resources usage in simulation

Status: Open.

#30 In ChipFlow/chipflow-examples;

· robtaylor opened on Apr 29, 2025

Use chipflow-lib for target software build step

Status: Open.

#27 In ChipFlow/chipflow-examples;

· gatecat opened on Apr 14, 2025

Get the FPGA stuff working on ULX3S and reduce duplicated code as much as possible

Status: Open.

#26 In ChipFlow/chipflow-examples;

· gatecat opened on Apr 14, 2025

Split out sim models and main.cc sim cxxrtl driver generation to chipflow-lib

Status: Open.

#25 In ChipFlow/chipflow-examples;

· gatecat opened on Apr 14, 2025

Test frontend side on Windows

Status: Open.

#24 In ChipFlow/chipflow-examples;

· gatecat opened on Apr 14, 2025

Add User Docs

Status: Open.

#15 In ChipFlow/chipflow-examples;

· robtaylor opened on Mar 17, 2025