Skip to content
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
28 changes: 28 additions & 0 deletions docs/chapter3/properties.md
Original file line number Diff line number Diff line change
Expand Up @@ -192,3 +192,31 @@ Table 3.8: Brief description of the different settings available on the **LAYOUT
</td>
</tr>
</table>

## Lite Mode in Simulator

![drawing](/img/img_chapter3/3.24.png)

<div align="center">
<em>Figure 3.24</em>
</div>

The Lite Mode is a performance mode that trades visual quality and features for better performance on resource-constrained devices. The Lite mode does the following things:

1. Reduces Canvas Resolution: Sets DPR to 1 regardless of device (no retina/high-DPI rendering)
2. Slows Down Updates: Makes UI updates 5x less frequent (time *= 5)
3. Disables Minimap: Completely disables minimap rendering and setup
4. Reduces Scaling Complexity: Simplifies canvas scaling calculations

### Changes due to Lite Mode

Visual Changes:
1. Lower Resolution: Circuit elements appear less crisp on high-DPI displays
2. No Minimap: The navigation minimap is hidden
3. Slower Responsiveness: UI updates happen less frequently

When to use Lite mode:
1. Low-end devices with limited graphics performance
2. Battery saving on mobile devices
3. Older computers that struggle with high-resolution rendering
4. Large circuits where performance becomes an issue
2 changes: 1 addition & 1 deletion docs/chapter6/delayvsclock.md
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ description: "Delayvsclock page in Chapter6 of CircuitVerse documentation."

Before exploring how to visualize a timing diagram for a given circuit, this section explores some key concepts that define the working of the **TIMING DIAGRAM** panel.

## Clock Time (ms):
## Clock Time (ms)

The **Clock Time** property attribute in Figure 6.1 refers to the time interval for the half cycle of a circuit. Changing the clock time interval speeds up or slows down the circuit simulation. However, it should be noted that changing the **Delay** attribute for any circuit element doesn't change circuit behavior. This clock frequency is only for demonstration purposes.

Expand Down
Binary file added static/img/img_chapter3/3.24.png
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.