util: Add mmio helpers functions for riscv

[zzSunil]

Fix the issue where using intrinsics generated atomic load/store instructions on RISC-V caused SEGFAULT when accessing MMIO regions, by adding a RISC-V specific implementation to resolve the problem.

Tested on SG2044 with MT28908 RDMA(mlx5) card.

[jgunthorpe]

Please explain in more detail what the actual problem is?

This seems like a codegen issue in the compiler as memory_order_relaxed should not generate instructions any different from what your version has.

[zzSunil]

Please explain in more detail what the actual problem is?

This seems like a codegen issue in the compiler as memory_order_relaxed should not generate instructions any different from what your version has.

Please explain in more detail what the actual problem is?

This seems like a codegen issue in the compiler as memory_order_relaxed should not generate instructions any different from what your version has.

Thanks for reviewing this PR :) I will explain more details about this patch.

before this patch(on the right side), I'm trying to setup rdma-core in a new coming riscv64 soc(next gen of XuanTie C910/C920 series), and when i tried to test rdma functionality with rdma-core example program, every single one of them breaks, and i launch up gdb then find out that is one atomic swap instruction(generated by gcc intrinsics) in mmio_read/write function cause all the problems. according to riscv privileged spec section 3.6.3.1. AMO PMA Main memory and I/O regions may only support a subset or none of the processor-supported atomic operations. We recommend providing at least AMOLogical support for I/O regions where possible. So i assume atomic instruction can't operate on MMIO memory region on my platform and made this patch to avoid atomic instruction with regular load/store with fence, and it solve the problem(for at least my platform).I think it's more like a standard implementation issue😂but i can't get the soc datasheet to verify this(sorry about this)

BR