[CIR][AMDGPU] Add lowering for amdgcn ds swizzle builtin

Author: skc7

clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp

@@ -92,6 +92,8 @@ mlir::Value CIRGenFunction::emitAMDGPUBuiltinExpr(unsigned builtinId,
     llvm_unreachable("div_fmas_* NYI");
   }
   case AMDGPU::BI__builtin_amdgcn_ds_swizzle:
+    return emitBuiltinWithOneOverloadedType<2>(expr, "amdgcn.ds.swizzle")
+        .getScalarVal();
   case AMDGPU::BI__builtin_amdgcn_mov_dpp8:
   case AMDGPU::BI__builtin_amdgcn_mov_dpp:
   case AMDGPU::BI__builtin_amdgcn_update_dpp: {

clang/test/CIR/CodeGen/HIP/builtins-amdgcn.hip

@@ -218,3 +218,13 @@ __device__ void test_wave_reduce_add_u32_iterative_i32(int* out, int in) {
 __device__ void test_wave_reduce_add_u32_dpp_i32(int* out, int in) {
   *out = __builtin_amdgcn_wave_reduce_add_u32(in, 2);
 }
+
+// CIR-LABEL: @_Z19test_ds_swizzle_i32Pii
+// CIR: cir.llvm.intrinsic "amdgcn.ds.swizzle" {{.*}} : (!s32i, !s32i) -> !s32i
+// LLVM: define{{.*}} void @_Z19test_ds_swizzle_i32Pii
+// LLVM: call i32 @llvm.amdgcn.ds.swizzle(i32 %{{.*}}, i32 32)
+// OGCG: define{{.*}} void @_Z19test_ds_swizzle_i32Pii
+// OGCG: call i32 @llvm.amdgcn.ds.swizzle(i32 %{{.*}}, i32 32)
+__device__ void test_ds_swizzle_i32(int* out, int a) {
+  *out = __builtin_amdgcn_ds_swizzle(a, 32);
+}

clang/test/CIR/CodeGen/OpenCL/builtins_amdgcn.cl

@@ -220,3 +220,13 @@ void test_wave_reduce_add_u32_iterative(global int* out, int in) {
 void test_wave_reduce_add_u32_dpp(global int* out, int in) {
   *out = __builtin_amdgcn_wave_reduce_add_u32(in, 2);
 }
+
+// CIR-LABEL: @test_ds_swizzle
+// CIR: cir.llvm.intrinsic "amdgcn.ds.swizzle" {{.*}} : (!s32i, !s32i) -> !s32i
+// LLVM: define{{.*}} void @test_ds_swizzle
+// LLVM: call i32 @llvm.amdgcn.ds.swizzle(i32 %{{.*}}, i32 32)
+// OGCG: define{{.*}} void @test_ds_swizzle
+// OGCG: call i32 @llvm.amdgcn.ds.swizzle(i32 %{{.*}}, i32 32)
+void test_ds_swizzle(global int* out, int a) {
+  *out = __builtin_amdgcn_ds_swizzle(a, 32);
+}