[CIR][AMDGPU] Add lowering for amdgcm readlane readfirstlane builtins

Author: skc7

clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp

@@ -102,9 +102,13 @@ mlir::Value CIRGenFunction::emitAMDGPUBuiltinExpr(unsigned builtinId,
   case AMDGPU::BI__builtin_amdgcn_permlane64: {
     llvm_unreachable("permlane_* NYI");
   }
-  case AMDGPU::BI__builtin_amdgcn_readlane:
+  case AMDGPU::BI__builtin_amdgcn_readlane: {
+    return emitBuiltinWithOneOverloadedType<2>(expr, "amdgcn.readlane")
+        .getScalarVal();
+  }
   case AMDGPU::BI__builtin_amdgcn_readfirstlane: {
-    llvm_unreachable("readlane_* NYI");
+    return emitBuiltinWithOneOverloadedType<1>(expr, "amdgcn.readfirstlane")
+        .getScalarVal();
   }
   case AMDGPU::BI__builtin_amdgcn_div_fixup:
   case AMDGPU::BI__builtin_amdgcn_div_fixupf:

clang/test/CIR/CodeGen/HIP/builtins-amdgcn.hip

@@ -218,3 +218,23 @@ __device__ void test_wave_reduce_add_u32_iterative_i32(int* out, int in) {
 __device__ void test_wave_reduce_add_u32_dpp_i32(int* out, int in) {
   *out = __builtin_amdgcn_wave_reduce_add_u32(in, 2);
 }
+
+// CIR-LABEL: @_Z13test_readlanePiii
+// CIR: cir.llvm.intrinsic "amdgcn.readlane" {{.*}} : (!s32i, !s32i) -> !s32i
+// LLVM: define{{.*}} void @_Z13test_readlanePiii
+// LLVM: call i32 @llvm.amdgcn.readlane.i32(i32 %{{.*}}, i32 %{{.*}})
+// OGCG: define{{.*}} void @_Z13test_readlanePiii
+// OGCG: call i32 @llvm.amdgcn.readlane.i32(i32 %{{.*}}, i32 %{{.*}})
+__device__ void test_readlane(int* out, int a, int b) {
+  *out = __builtin_amdgcn_readlane(a, b);
+}
+
+// CIR-LABEL: @_Z18test_readfirstlanePii
+// CIR: cir.llvm.intrinsic "amdgcn.readfirstlane" {{.*}} : (!s32i) -> !s32i
+// LLVM: define{{.*}} void @_Z18test_readfirstlanePii
+// LLVM: call i32 @llvm.amdgcn.readfirstlane.i32(i32 %{{.*}})
+// OGCG: define{{.*}} void @_Z18test_readfirstlanePii
+// OGCG: call i32 @llvm.amdgcn.readfirstlane.i32(i32 %{{.*}})
+__device__ void test_readfirstlane(int* out, int a) {
+  *out = __builtin_amdgcn_readfirstlane(a);
+}

clang/test/CIR/CodeGen/OpenCL/builtins_amdgcn.cl

@@ -220,3 +220,24 @@ void test_wave_reduce_add_u32_iterative(global int* out, int in) {
 void test_wave_reduce_add_u32_dpp(global int* out, int in) {
   *out = __builtin_amdgcn_wave_reduce_add_u32(in, 2);
 }
+
+
+// CIR-LABEL: @test_readlane
+// CIR: cir.llvm.intrinsic "amdgcn.readlane" {{.*}} : (!s32i, !s32i) -> !s32i
+// LLVM: define{{.*}} void @test_readlane
+// LLVM: call i32 @llvm.amdgcn.readlane.i32(i32 %{{.*}}, i32 %{{.*}})
+// OGCG: define{{.*}} void @test_readlane
+// OGCG: call i32 @llvm.amdgcn.readlane.i32(i32 %{{.*}}, i32 %{{.*}})
+void test_readlane(global int* out, int a, int b) {
+  *out = __builtin_amdgcn_readlane(a, b);
+}
+
+// CIR-LABEL: @test_readfirstlane
+// CIR: cir.llvm.intrinsic "amdgcn.readfirstlane" {{.*}} : (!s32i) -> !s32i
+// LLVM: define{{.*}} void @test_readfirstlane
+// LLVM: call i32 @llvm.amdgcn.readfirstlane.i32(i32 %{{.*}})
+// OGCG: define{{.*}} void @test_readfirstlane
+// OGCG: call i32 @llvm.amdgcn.readfirstlane.i32(i32 %{{.*}})
+void test_readfirstlane(global int* out, int a) {
+  *out = __builtin_amdgcn_readfirstlane(a);
+}