[dv] Enable Zcb and Zcmp extension in compiler

Author: SamuelRiedel

dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv

@@ -53,7 +53,7 @@ bit support_unaligned_load_store = 1'b1;
 
 // ISA supported by the processor
 // TODO: Determine how Ibex RV32B types map to RISCV-DV ISA names
-riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C
+riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32ZCB, RV32ZCMP
 % if ibex_config['RV32B'] == 'ibex_pkg::RV32BNone':
     };
 % else:

dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml

@@ -1157,3 +1157,12 @@
   rtl_test: core_ibex_base_test
   rtl_params:
     RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BOTEarlGrey", "ibex_pkg::RV32BBalanced"]
+
+- test: riscv_zcb_balanced_test
+  desc: >
+    Random instruction test with zcb instructions in balanced configuration
+  iterations: 10
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +enable_zcb_extension=1
+  rtl_test: core_ibex_base_test

dv/uvm/core_ibex/scripts/ibex_cmd.py

@@ -114,8 +114,9 @@ def get_isas_for_config(cfg: Config) -> Tuple[str, str]:
 
     has_bitmanip = cfg.rv32b != 'ibex_pkg::RV32BNone'
     toolchain_isa = base_isa + ('b' if has_bitmanip else '')
+    toolchain_isa = toolchain_isa + ('_zicsr_zifencei_zcb_zcmp')
 
-    return (toolchain_isa, '_'.join([base_isa] + bitmanip_isa))
+    return (toolchain_isa, '_'.join([base_isa] + ['Zicsr','Zifencei','Zcb','Zcmp'] + bitmanip_isa))
 
 
 _TestEntry = Dict[str, object]

dv/uvm/core_ibex/tests/core_ibex_base_test.sv

@@ -70,6 +70,10 @@ class core_ibex_base_test extends uvm_test;
     isa = {"rv32", RV32E ? "e" : "i"};
     if (RV32M != RV32MNone) isa = {isa, "m"};
     isa = {isa, "c"};
+    isa = {isa, "_Zicsr"};
+    isa = {isa, "_Zifencei"};
+    isa = {isa, "_Zcb"};
+    isa = {isa, "_Zcmp"};
     case (RV32B)
       RV32BNone:
         ;