[dv] Pass expanded instruction to cosim

Author: SamuelRiedel

dv/cosim/cosim.h

@@ -74,9 +74,12 @@ class Cosim {
   // In this case the instruction doesn't retire so no register write occurs (so
   // `write_reg` must be 0).
   //
+  // `expanded_insn` is the 32-bit instruction that is being expanded or zero.
+  //
   // Returns false if there are any errors; use `get_errors` to obtain details
   virtual bool step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
-                    bool sync_trap, bool suppress_reg_write) = 0;
+                    bool sync_trap, bool suppress_reg_write,
+                    uint32_t expanded_insn) = 0;
 
   // When more than one of `set_mip`, `set_nmi` or `set_debug_req` is called
   // before `step` which one takes effect is chosen by the co-simulator. Which

dv/cosim/cosim_dpi.cc

@@ -12,11 +12,12 @@
 
 int riscv_cosim_step(Cosim *cosim, const svBitVecVal *write_reg,
                      const svBitVecVal *write_reg_data, const svBitVecVal *pc,
-                     svBit sync_trap, svBit suppress_reg_write) {
+                     svBit sync_trap, svBit suppress_reg_write,
+                     const svBitVecVal *expanded_insn) {
   assert(cosim);
 
   return cosim->step(write_reg[0], write_reg_data[0], pc[0], sync_trap,
-                     suppress_reg_write)
+                     suppress_reg_write, expanded_insn[0])
              ? 1
              : 0;
 }

dv/cosim/cosim_dpi.h

@@ -16,7 +16,8 @@
 extern "C" {
 int riscv_cosim_step(Cosim *cosim, const svBitVecVal *write_reg,
                      const svBitVecVal *write_reg_data, const svBitVecVal *pc,
-                     svBit sync_trap, svBit suppress_reg_write);
+                     svBit sync_trap, svBit suppress_reg_write,
+                     const svBitVecVal *expanded_insn);
 void riscv_cosim_set_mip(Cosim *cosim, const svBitVecVal *pre_mip,
                          const svBitVecVal *post_mip);
 void riscv_cosim_set_nmi(Cosim *cosim, svBit nmi);

dv/cosim/cosim_dpi.svh

@@ -11,7 +11,8 @@
 `define COSIM_DPI_SVH
 
 import "DPI-C" function int riscv_cosim_step(chandle cosim_handle, bit [4:0] write_reg,
-  bit [31:0] write_reg_data, bit [31:0] pc, bit sync_trap, bit suppress_reg_write);
+  bit [31:0] write_reg_data, bit [31:0] pc, bit sync_trap, bit suppress_reg_write,
+  bit [31:0] expanded_insn);
 import "DPI-C" function void riscv_cosim_set_mip(chandle cosim_handle, bit [31:0] pre_mip,
   bit [31:0] post_mip);
 import "DPI-C" function void riscv_cosim_set_nmi(chandle cosim_handle, bit nmi);

dv/cosim/spike_cosim.cc

@@ -170,7 +170,8 @@ bool SpikeCosim::backdoor_read_mem(uint32_t addr, size_t len,
 //   processor, and when we call step() again we start executing in the new
 //   context of the trap (trap handler, new MSTATUS, debug rom, etc. etc.)
 bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
-                      bool sync_trap, bool suppress_reg_write) {
+                      bool sync_trap, bool suppress_reg_write,
+                      uint32_t expanded_insn) {
   assert(write_reg < 32);
 
   // The DUT has just produced an RVFI item
@@ -320,7 +321,8 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
 
 bool SpikeCosim::check_retired_instr(uint32_t write_reg,
                                      uint32_t write_reg_data, uint32_t dut_pc,
-                                     bool suppress_reg_write) {
+                                     bool suppress_reg_write,
+                                     uint32_t expanded_insn) {
   // Check the retired instruction and all of its side-effects match those from
   // the DUT
 
@@ -355,7 +357,8 @@ bool SpikeCosim::check_retired_instr(uint32_t write_reg,
       assert(!gpr_write_seen);
 
       if (!suppress_reg_write &&
-          !check_gpr_write(reg_change, write_reg, write_reg_data)) {
+          !check_gpr_write(reg_change, write_reg, write_reg_data,
+                           expanded_insn)) {
         return false;
       }
 
@@ -433,7 +436,8 @@ bool SpikeCosim::check_sync_trap(uint32_t write_reg, uint32_t dut_pc,
 }
 
 bool SpikeCosim::check_gpr_write(const commit_log_reg_t::value_type &reg_change,
-                                 uint32_t write_reg, uint32_t write_reg_data) {
+                                 uint32_t write_reg, uint32_t write_reg_data,
+                                 uint32_t expanded_insn) {
   uint32_t cosim_write_reg = (reg_change.first >> 4) & 0x1f;
 
   if (write_reg == 0) {

dv/cosim/spike_cosim.h

@@ -77,7 +77,8 @@ class SpikeCosim : public simif_t, public Cosim {
   bool check_debug_ebreak(uint32_t write_reg, uint32_t pc, bool sync_trap);
 
   bool check_gpr_write(const commit_log_reg_t::value_type &reg_change,
-                       uint32_t write_reg, uint32_t write_reg_data);
+                       uint32_t write_reg, uint32_t write_reg_data,
+                       uint32_t expanded_insn);
 
   bool check_suppress_reg_write(uint32_t write_reg, uint32_t pc,
                                 uint32_t &suppressed_write_reg);
@@ -120,10 +121,12 @@ class SpikeCosim : public simif_t, public Cosim {
                           const uint8_t *data_in) override;
   bool backdoor_read_mem(uint32_t addr, size_t len, uint8_t *data_out) override;
   bool step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
-            bool sync_trap, bool suppress_reg_write) override;
+            bool sync_trap, bool suppress_reg_write,
+            uint32_t expanded_insn) override;
 
   bool check_retired_instr(uint32_t write_reg, uint32_t write_reg_data,
-                           uint32_t dut_pc, bool suppress_reg_write);
+                           uint32_t dut_pc, bool suppress_reg_write,
+                           uint32_t expanded_insn);
   bool check_sync_trap(uint32_t write_reg, uint32_t pc,
                        uint32_t initial_spike_pc);
   void set_mip(uint32_t pre_mip, uint32_t post_mip) override;

dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv

@@ -163,7 +163,7 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
       riscv_cosim_set_ic_scr_key_valid(cosim_handle, rvfi_instr.ic_scr_key_valid);
 
       if (!riscv_cosim_step(cosim_handle, rvfi_instr.rd_addr, rvfi_instr.rd_wdata, rvfi_instr.pc,
-                            rvfi_instr.trap, rvfi_instr.rf_wr_suppress)) begin
+                            rvfi_instr.trap, rvfi_instr.rf_wr_suppress, rvfi_instr.expanded_insn)) begin
         // cosim instruction step doesn't match rvfi captured instruction, report a fatal error
         // with the details
         if (cfg.relax_cosim_check) begin

dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_monitor.sv

@@ -45,6 +45,7 @@ class ibex_rvfi_monitor extends uvm_monitor;
       trans_collected.rf_wr_suppress   = vif.monitor_cb.ext_rf_wr_suppress;
       trans_collected.mcycle           = vif.monitor_cb.ext_mcycle;
       trans_collected.ic_scr_key_valid = vif.monitor_cb.ext_ic_scr_key_valid;
+      trans_collected.expanded_insn    = vif.monitor_cb.ext_expanded_insn;
 
       for (int i=0; i < 10; i++) begin
        trans_collected.mhpmcounters[i]  = vif.monitor_cb.ext_mhpmcounters[i];

dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_seq_item.sv

@@ -21,6 +21,8 @@ class ibex_rvfi_seq_item extends uvm_sequence_item;
   bit [31:0] mhpmcountersh [10];
   bit        ic_scr_key_valid;
 
+  bit [31:0] expanded_insn;
+
   `uvm_object_utils_begin(ibex_rvfi_seq_item)
     `uvm_field_int (trap, UVM_DEFAULT)
     `uvm_field_int (pc, UVM_DEFAULT)
@@ -37,6 +39,7 @@ class ibex_rvfi_seq_item extends uvm_sequence_item;
     `uvm_field_sarray_int (mhpmcounters, UVM_DEFAULT)
     `uvm_field_sarray_int (mhpmcountersh, UVM_DEFAULT)
     `uvm_field_int (ic_scr_key_valid, UVM_DEFAULT)
+    `uvm_field_int (expanded_insn, UVM_DEFAULT)
   `uvm_object_utils_end
 
   `uvm_object_new

dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv

@@ -40,6 +40,8 @@ interface core_ibex_rvfi_if(input logic clk);
 
   logic        ext_ic_scr_key_valid;
 
+  logic [31:0] ext_expanded_insn;
+
   clocking monitor_cb @(posedge clk);
     input reset;
     input valid;
@@ -74,6 +76,7 @@ interface core_ibex_rvfi_if(input logic clk);
     input ext_mhpmcountersh;
     input ext_ic_scr_key_valid;
     input ext_irq_valid;
+    input ext_expanded_insn;
   endclocking
 
   task automatic wait_clks(input int num);