Add Zcb and Zcmp extensions #2324
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SamuelRiedel
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Lots of nitty comments on the draft (sorry, but I'd started reading so thought I may as well review it properly...)
I really like this though! Thank you all so much for the improvement.
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Thank you for the feedback. Sorry for the delay in implementing it. I just pushed an updated version that should address all your comments. |
rswarbrick
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Nov 7, 2025
This is required to ensure we can trace all expanded instructions but also already advance the PC on the last expanded instruction
Tracking also the original instruction, not only the micro-op, allows the DV to track whether and which instruction we are expanding
The tracer usually only sees the instructions that reach the ID stage. Since the Zcmp instructions are expanded in the IF stage, they will be traced as their micro-ops. This adds information in the trace from which expanded instruction those micro-ops come from.
The handshake only considered whether the ID stage would be ready. But the actual pipeline register will also take the `pc_set_i` signal into account, which signals a jump. Since the compressed decoder has state now (through the Zcmp extension), this improper handshake led to some of the expanded instructions to get lost. At the same time, we also take this signal into account for the enable signal of the pipeline stage to avoid unnecessary switching.
Add a function and state to process multiple Ibex instructions that are modeled as a single instruction in riscv-isa-sim. The current function checks that the same registers are written overall.
Merge the two cm.mv* states into a single one. This should still be easy to understand and saves us an extra bit in the encoding.
This indicates that the current instruction is the last instruction of a sequence belonging to an expanded one.
Instead of stepping Spike once at the beginning of the expanded instruction and then comparing each next operation with Spike's changes, this commit logs all of Ibex's changes and then steps spike at the last expanded instruction, i.e., the committing instruction. This then allows checking a list of changes from Ibex with a list of changes from Spike. The reason to do it this way around is that the memory access checks are triggered by Spike. Therefore, when Spike steps through the expanded instruction, it simultaneously checks all memory accesses. Previously, only the first instructions on Ibex were executed at this stage and only those memory accesses were visible. Now, Ibex will also have completed the entire instruction and memory accesses, and the check initiated by Spike will succeed.
This reverts commit 69083c1.
Update code from upstream repository https://github.com/SamuelRiedel/riscv-dv to revision 31bc39ffcf2a9920c652462671e9a549331260e7 Signed-off-by: Samuel Riedel <[email protected]>
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This PR adds support for the Zcb and Zcmp code-saving extensions. This support is implemented in a parameterizable way via the
RV32ZCparameter, which allows choosing none, either, or both extensions. By default, both extensions are enabled because their combined hardware overhead is small, approximately 800 gate equivalents.The Zcb extension introduces new compressed encodings for common instructions already supported in Ibex. The Zcmp extension introduces single compressed instructions that expand into multiple existing instructions within Ibex. For example, a stack push expands into multiple store instructions and a stack pointer update. Therefore, both extensions are implemented in the IF stage.
Adding these new instructions requires updates to the following components:
riscv-isa-sim(Spike): Updated Spike to support those new extensions Add the Zc* extensions riscv-isa-sim#27riscv-dv: Add both extensions to riscv-dv. We can either try to upstream those or create a fork. I didn't open a PR yet, but the diff is here: chipsalliance/riscv-dv@master...SamuelRiedel:riscv-dv:zcbzcmpMissing Components and Known Issues: