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[mxfp8 moe training] add CUDA kernel for per-group conversion of scale factors to blocked layout #3504
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/ao/3504
Note: Links to docs will display an error until the docs builds have been completed. ✅ You can merge normally! (1 Unrelated Failure)As of commit 243017f with merge base 7035fb7 ( BROKEN TRUNK - The following job failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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…e factors to blocked layout stack-info: PR: #3504, branch: danielvegamyhre/stack/86
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Stacked PRs:
[mxfp8 moe training] add CUDA kernel for per-group conversion of scale factors to blocked layout
TL;DR this PR adds a new CUDA kernel for blocked layout scale factors with groups along K for 2d2d grouped GEMM that is ~2x to 3.5x faster than existing Triton kernel. For the DSV3 shapes we care most about, it's about 2.5x to 3x faster than Triton.
Kernel design
Summary
tile_xor).superrow_xor)tile_xor ^ superrow_xorto avoid bank conflicts on both reads and writes.Benchmarks
total_M(local batch size * seq len) ranges from 32768 to 131072 (scale widths of 1024 and 4096, respectively)Note: memory bandwidth utilization is not the best metric for this kernel since the ALU pipelines are heavily utilized as well. I am just using it as a proxy here while also referencing NCU to verify there's no substantial performance issues remaining.
Super detailed explanation for anyone interested
Loads from GMEM
Stores to SMEM (ignoring XOR swizzle for avoiding bank conflicts on writes)
Dual XOR swizzle to base SMEM address for each thread to resolve bank conflicts on both writes and reads
(pasting from a google doc blog post draft for this description, so the bit highlighting is visible)

Copy SMEM to GMEM
Here we are doing a linear read pattern from SMEM, doing vectorized coalesced uint4 loads from shared memory and storing in global memory. The issue here is 4 way bank conflicts, but I found no good solution here. We have 32 banks of 4 bytes each, so that's 128 total bytes before wrapping around and hitting the first bank again. This means with 8 threads reading 16 bytes each, 8 * 16 = 128, so every 8 threads in a warp will wrap around and experience a bank conflict for a total of a 4-way bank conflict per warp.
The best solution I found for this was a suggestion from Claude, actually, to basically add a second layer of XOR that shifts the bank every 128 bytes within a 512-byte tile (128 * 4 = 512). Composing this XOR with the existing XOR does avoid bank conflicts for both reads and writes. Composing two XORs like this forms a "Latin square" kind of like Sudoku where given a tile_xor, we have unique banks for every superrow xor (and vice versa).
(diagram coming)
Pipeline async load of chunk N+1 with processing of chunk N
This kernel is instruction-heavy and has a lot of complicated pointer math. It does the prefix sums, then does the lookup of which group this thread block is operating on and block layout transformations. With NCU, I saw the ALU was highly utilized. Therefore, I thought it would be useful to not block the next load from global memory on all of this heavy pointer math going on. So I implemented a pipelined approach with double buffering where we can overlap the load of the next chunk from global memory with the computation needed on the current chunk. Compared to a non-pipelined approach, this approach showed solid improvements on large shapes and neutral for small and medium shapes.
I templated the number of chunks per thread block, benchmarked a few values, and have just hard-coded the config that was best.