Support chips which don't support MIE/MIP CSRs #332
Conversation
rmsyn
left a comment
rmsyn
left a comment
There was a problem hiding this comment.
Is this only needed for the riscv-rt crate on the platforms you mention? For example, would we also want to remove the mie/mip modules in riscv::register?
Otherwise, LGTM.
|
I don't think we need to remove registers from riscv. As long as you don't use it, it should be OK. Otherwise, we would also need to add numerous features for supervisor mode or other anomalies |
romancardenas
left a comment
romancardenas
left a comment
There was a problem hiding this comment.
Thank you so much! For completeness, could you rename the feature to no-xie-xip and apply the same scheme for supervisor mode too?
riscv-rt/Cargo.toml
Outdated
| u-boot = ["riscv-rt-macros/u-boot", "single-hart"] | ||
| no-interrupts = [] | ||
| no-exceptions = [] | ||
| no-mie-mip = [] |
There was a problem hiding this comment.
| no-mie-mip = [] | |
| no-xie-xip = [] |
There was a problem hiding this comment.
Sure - that makes sense 👍
romancardenas
left a comment
romancardenas
left a comment
There was a problem hiding this comment.
LGTM! I sugggested a small update in the changelog to align with the new feature name
riscv-rt/CHANGELOG.md
Outdated
| - New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function. | ||
| - Added `.uninit` section to the linker file. Due to its similarities with `.bss`, the | ||
| linker will place this new section in `REGION_BSS`. | ||
| - Additional feature `no-mie-mip` to work on chips without the MIE and MIP CSRs (e.g. ESP32-C2, ESP32-C3) |
There was a problem hiding this comment.
| - Additional feature `no-mie-mip` to work on chips without the MIE and MIP CSRs (e.g. ESP32-C2, ESP32-C3) | |
| - Additional feature `no-xie-xip` to work on chips without the XIE and XIP CSRs (e.g. ESP32-C2, ESP32-C3) |
There was a problem hiding this comment.
🤦♂️ ofc ... sorry I missed that
romancardenas
left a comment
romancardenas
left a comment
There was a problem hiding this comment.
LGTM! Thank you so much
3 participants
We'd love to use
riscv-rtfor ESP32-Cx / Hx - unfortunately C2 and C3 don't support the MIE/MIP CSRs.This adds a feature "no-mie-mip" (which should fit the naming - e.g. "no-interrupts","no-exceptions")