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Support chips which don't support MIE/MIP CSRs #332

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Merged
romancardenas merged 3 commits into from
Jul 23, 2025
Merged

Support chips which don't support MIE/MIP CSRs #332

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6c4a2d8
Support chips which don't support MIE/MIP CSRs
bjoernQ Jul 22, 2025
15151fb
Rename feature `no-mie-mip` to `no-xie-xip`
bjoernQ Jul 23, 2025
c609929
Adapt changelog entry
bjoernQ Jul 23, 2025
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1 change: 1 addition & 0 deletions riscv-rt/CHANGELOG.md
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Expand Up @@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function.
- Added `.uninit` section to the linker file. Due to its similarities with `.bss`, the
linker will place this new section in `REGION_BSS`.
- Additional feature `no-mie-mip` to work on chips without the MIE and MIP CSRs (e.g. ESP32-C2, ESP32-C3)
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@romancardenas romancardenas Jul 23, 2025

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Suggested change
- Additional feature `no-mie-mip` to work on chips without the MIE and MIP CSRs (e.g. ESP32-C2, ESP32-C3)
- Additional feature `no-xie-xip` to work on chips without the XIE and XIP CSRs (e.g. ESP32-C2, ESP32-C3)

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@bjoernQ bjoernQ Jul 23, 2025

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🤦‍♂️ ofc ... sorry I missed that


### Changed

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1 change: 1 addition & 0 deletions riscv-rt/Cargo.toml
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Expand Up @@ -40,5 +40,6 @@ v-trap = ["riscv-rt-macros/v-trap"]
u-boot = ["riscv-rt-macros/u-boot", "single-hart"]
no-interrupts = []
no-exceptions = []
no-mie-mip = []
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@romancardenas romancardenas Jul 22, 2025

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Suggested change
no-mie-mip = []
no-xie-xip = []

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@bjoernQ bjoernQ Jul 23, 2025

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Sure - that makes sense 👍

device = []
memory = []
7 changes: 4 additions & 3 deletions riscv-rt/src/asm.rs
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Expand Up @@ -68,10 +68,11 @@ _abs_start:
#[cfg(feature = "s-mode")]
"csrw sie, 0
csrw sip, 0",
#[cfg(not(feature = "s-mode"))]
#[cfg(all(not(feature = "s-mode"), not(feature = "no-mie-mip")))]
"csrw mie, 0
csrw mip, 0
csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode
csrw mip, 0",
#[cfg(not(feature = "s-mode"))]
"csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode
// Set pre-init trap vector
"la t0, _pre_init_trap",
#[cfg(feature = "s-mode")]
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