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changelog.yaml
329 workflow run results
329 workflow run results

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Changelog check Changelog check #664: Merge group checks requested
8s
8s
Allow 64-bit Mcause::from_bits on rv64 Changelog check #663: Pull request #334 synchronize by jsgf
32s jsgf:fix-mcause-interrupt
jsgf:fix-mcause-interrupt
32s
riscv: Use riscv_pac::CoreInterruptNumber in xip registers Changelog check #662: Pull request #331 synchronize by romancardenas
7s riscv-interrupts
riscv-interrupts
7s
Allow 64-bit Mcause::from_bits on rv64 Changelog check #661: Pull request #334 synchronize by jsgf
22s jsgf:fix-mcause-interrupt
jsgf:fix-mcause-interrupt
22s
Allow 64-bit Mcause::from_bits on rv64 Changelog check #660: Pull request #334 opened by jsgf
9s jsgf:fix-mcause-interrupt
jsgf:fix-mcause-interrupt
9s
Changelog check Changelog check #659: Merge group checks requested
36s
36s
Support chips which don't support MIE/MIP CSRs Changelog check #658: Pull request #332 synchronize by bjoernQ
1m 2s bjoernQ:support-chips-wo-mie-mip
bjoernQ:support-chips-wo-mie-mip
1m 2s
Support chips which don't support MIE/MIP CSRs Changelog check #656: Pull request #332 opened by bjoernQ
12s bjoernQ:support-chips-wo-mie-mip
bjoernQ:support-chips-wo-mie-mip
12s
riscv: Use riscv_pac::CoreInterruptNumber in xip registers Changelog check #655: Pull request #331 opened by romancardenas
38s riscv-interrupts
riscv-interrupts
38s
Changelog check Changelog check #654: Merge group checks requested
43s
43s
riscv: Use riscv_pac::CoreInterrupt in mie register Changelog check #653: Pull request #330 synchronize by romancardenas
11s riscv-interrupts
riscv-interrupts
11s
riscv: Use riscv_pac::CoreInterrupt in mie register Changelog check #652: Pull request #330 synchronize by romancardenas
9s riscv-interrupts
riscv-interrupts
9s
riscv: Use riscv_pac::CoreInterrupt in mie register Changelog check #651: Pull request #330 synchronize by romancardenas
7s riscv-interrupts
riscv-interrupts
7s
riscv: Use riscv_pac::CoreInterrupt in mie register Changelog check #650: Pull request #330 synchronize by romancardenas
23s riscv-interrupts
riscv-interrupts
23s
riscv: Use riscv_pac::CoreInterrupt in mie register Changelog check #649: Pull request #330 opened by romancardenas
25s riscv-interrupts
riscv-interrupts
25s
Changelog check Changelog check #648: Merge group checks requested
7s
7s
riscv-rt: Add uninit section Changelog check #647: Pull request #329 opened by romancardenas
8s post-init
post-init
8s
Changelog check Changelog check #646: Merge group checks requested
12s
12s
riscv-rt: Add __post_init Rust function Changelog check #645: Pull request #328 synchronize by romancardenas
11s post-init
post-init
11s
riscv-rt: Add __post_init Rust function Changelog check #644: Pull request #328 opened by romancardenas
10s post-init
post-init
10s
Changelog check Changelog check #643: Merge group checks requested
9s
9s
riscv-rt: Preserve a0-a2 in startup only when startup functions are expected Changelog check #642: Pull request #326 synchronize by romancardenas
12s rvrt-asm-alternative
rvrt-asm-alternative
12s
riscv-rt: Preserve a0-a2 in startup only when startup functions are expected Changelog check #641: Pull request #326 opened by romancardenas
27s rvrt-asm-alternative
rvrt-asm-alternative
27s
riscv-rt: Use callee-saved registers for preserving arguments Changelog check #640: Pull request #325 opened by romancardenas
13s rvrt-asm
rvrt-asm
13s
Changelog check Changelog check #639: Merge group checks requested
12s
12s